config.h

VxWorks下 Cpv3060的BSP源代码

 *   PCI_SLV_MEM_SIZE	- Size of Window for Local space access
 *
 * Map PCI I/O access to local CPU space (not used)
 * 
 *   PCI_SLV_IO_LOCAL
 *   PCI_SLV_IO_BUS
 *   PCI_SLV_IO_SIZE
 *
 * Map QSPAN windows between CPU and PCI space
 *
 *   QSPAN_MSTR_IO_SIZE	- Size of I/O window for QSPAN setup
 *   QSPAN_MSTR_MEM_SIZE- Size of MEM window for QSPAN setup
 *   QSPAN_SLV_MEM_SIZE	- Size of Translation Address window for QSPAN
 *   QSPAN_SLV_IO_SIZE  - not used
 */

/*
 *
 * Base address of ISA I/O space as seen by CPU,
 * This address is directly used by the hardware to map the base address
 * of PCI Mem space.
 *
 *   (PCI_MSTR_MEMIO_LOCAL = ISA_MSTR_IO_LOCAL + 0x40000000).
 */

#define ISA_MSTR_IO_LOCAL	0x80000000	/* Set by BR5/CR5 */

/*
 * PCI_MSTR_SIZE is used for setting the window sizes of both PCI I/O
 * space and PCI Mem space when setting up the Chip Select registers.
 *
 * Only one chip select register is available for PCI space, so I/O space and
 * Mem space must be the same.  PCI_MSTR_MEM_SIZE is automatically set to the
 * value defined here.  Minimum size is 64 KB, maximum size is 512MB.
 */

#define PCI_MSTR_SIZE		0x20000000	/* defaults to max size */

/* 
 * This macro defines the base of PCI Mem on the PCI bus.  This is the
 * address that the QSPAN will translate the PCI_MSTR_MEMIO_LOCAL value to
 * 
 * This value must be 0 if adding ISA devices in MEM space.
 */

#define PCI_MSTR_MEMIO_BUS	0x00000000

/* 
 * The macro PCI_SLV_MEM_LOCAL is the base at which local memory will appear
 * in PCI space. 
 */ 

#define PCI_SLV_MEM_LOCAL	LOCAL_MEM_LOCAL_ADRS

/*
 * The macro PCI_SLV_MEM_BUS sets the base value for PCI Mem space access of
 * local memory.  A PCI memory device that puts this address onto the bus will
 * access local memory at the address specified by PCI_SLV_MEM_LOCAL
 */

#define PCI_SLV_MEM_BUS		0x80000000

/*
 * The macro QSPAN_MSTR_IO_SIZE defines the window size that the QSPAN chip
 * opens for PCI I/O space onto the PCI Bus -- the QSPAN SLAVE Translation
 * address size).
 * 
 * The size can range up to the size specified for PCI_MSTR_SIZE, but
 * ideally should be set to the same value.  Setting it a smaller value will
 * limit the amount of PCI I/O space available.
 * 
 * This define requires a coded value (QSPAN_QBSI_xxxx) from qspanPic.h.
 */

#define QSPAN_MSTR_IO_SIZE	QSPAN_QBSI_512MB 	/* default = 512MB */

/*
 * The macro QSPAN_MSTR_MEM_SIZE defines the window size that the QSPAN chip
 * opens for PCI Mem space onto the PCI Bus -- the QSPAN SLAVE Translation
 * address size.
 *
 * The size can range up to the size specified for PCI_MSTR_SIZE, but
 * ideally should be set to the same value.  Setting it a smaller value will
 * limit the amount of PCI Mem space available.
 *
 * This define requires a coded value (QSPAN_QBSI_xxxx) from qspanPic.h.
 */
	
#define QSPAN_MSTR_MEM_SIZE	QSPAN_QBSI_512MB 	/* default = 512MB */

/*
 * The macro PCI_SLV_MEM_SIZE and QSPAN_SLV_MEM_SIZE specify the range of
 * local memory space as it appears on the PCI bus.  These should be the same.
 */

#define PCI_SLV_MEM_SIZE	0x80000000	/* max is 2GB */
#define QSPAN_SLV_MEM_SIZE	QSPAN_QBTI_2GB	/* for setting the QSPAN */
						/* Translation Address size */
						/* use the QBTI_ size codes */

/*
 * The following PTE_xxx macros are used for setting the sizes of the 4
 * PCI/ISA windows defined in the Page Table Entries. These windows determine
 * where access to PCI I/O amd Mem space and ISA I/O and Mem space will occur.
 * They also define the true amount of space accessible for each space (from a
 * programming point of view ).
 *
 * Care must be taken when expanding the PCI I/O and PCI MEM window sizes.
 * 64KB of local memory is used for page tables per 8MB of PCI space mapped.
 *
 * The total size for (PTE_ISA_IO_SIZE + PTE_PCI_IO_SIZE) must be less
 * than or equal to PCI_MSTR_SIZE.
 *
 * The total size for (PTE_ISA_MEMIO_SIZE + PTE_PCI_MEM_SIZE) must be
 * less than or equal to PCI_MSTR_SIZE.
 *
 */

#define PTE_ISA_IO_SIZE		0x00010000	/* default = 64 KB */
#define PTE_PCI_IO_SIZE		0x02000000	/* default = 32 MB */
#define PTE_ISA_MEMIO_SIZE	PCI_MSTR_MEMIO_SIZE
#define PTE_PCI_MEM_SIZE	0x00800000	/* default = 8 MB */

/*
 * Change PCI_MSTR_MEMIO_SIZE to reflect the size of the PCI memory space
 * that is mapped in the sysPhysMemDesc[] array (in sysLib.c) for PCI
 * autoconfiguration.
 *
 * Be aware that all of the space starting with PCI_MSTR_MEMIO_LOCAL
 * (0xc0000000) and continuing for PCI_MSTR_MEMIO_SIZE bytes will be
 * mapped with MMU tables.  For each 128K of memory in this region,
 * a 1K piece of RAM will be used for MMU tables.  If the region is very
 * large, modifications to sysLib.c can be made to use BAT (Block Address
 * Translation) registers instead of MMU page tables to map the memory.
 * Note that the window defined by altering PCI_MSTR_MEMIO_SIZE must be
 * large enough to accomodate all of the PCI memory space found during
 * PCI autoconfiguration.  If it is not, some devices will not be
 * autoconfigured.
 */

#define PCI_MSTR_MEMIO_SIZE	0x04000000	/* 64 MB */

#ifdef INCLUDE_QSPAN
#   undef  PCI_MAX_DEV
#   define PCI_MAX_DEV		16	/* QSpan repeats all devices at 0x1x */
#endif  /* INCLUDE_QSPAN */


#ifdef INCLUDE_END

    /* PHY device configuration definitions */

#    define PHY_CNFG_AUTO_NEGOTIATE	0
#    define PHY_CNFG_10M_HALF_DUPLEX	1
#    define PHY_CNFG_10M_FULL_DUPLEX	2
#    define PHY_CNFG_100M_HALF_DUPLEX	3
#    define PHY_CNFG_100M_FULL_DUPLEX	4

#define	PHY_CNFG_MODE	PHY_CNFG_AUTO_NEGOTIATE
#endif /* INCLUDE_END */

#ifdef INCLUDE_DEC2155X
    /* Dec2155x (Drawbridge) configuration parameters */

#   define DEC2155X_SUB_VNDR_ID_VAL     MOT_SUB_VNDR_ID_VAL
#   define DEC2155X_SUB_SYS_ID_VAL      CPV3060_SUB_SYS_ID_VAL

    /*
     * The following must be a value between 0 and 15.  It represents the
     * bit number of the primary doorbell register used to interrupt the
     * MCP750 for shared memory * bus interrupts.
     */

#   define DEC2155X_SM_DOORBELL_BIT 0


#   define DEC2155X_PCI_DEV_NUMBER 0x03
#   define DEC2155X_PCI_BUS_NUMBER 0x00

    /*
     * the following define assigns all PCI arbiter inputs to the high-priority
     * group. for details, consult the 21554 user's manual.
     */

#   define DEC2155X_ARB_CTRL_VAL    DEC2155X_ARB_CTRL_MSK

    /*
     * a PCI read from the following cPCI memory address is used to flush the
     * Dec2155x write post buffer. It must be a valid location and free of
     * side effects. The default value targets location 0x00000000 in host DRAM.
     */

#   define CPCI_FLUSH_ADDR CPCI_MSTR_MEM_BUS

    /*
     * NOTE: Window sizes must be an integral power of 2 and translation
     * values must be an even multiple of the window size. To enable
     * prefetch on a memory window "or" in PCI_BAR_MEM_PREFETCH.
     */

    /* Downstream windows (for access from Compact PCI backpanel) */

    /*
     * note that downstream translation values are relative to the local PCI
     * memory map not the local processor address map. PCI_SLV_MEM_BUS is
     * the base of the local DRAM as seen from the local PCI bus (secondary
     * side of the 2155x).  Raven will translate this into a local DRAM address.
     */

    /*
     * 4MB window into local DRAM (first 4KB accesses 2155x CSR register set).
     */

#   define DEC2155X_CSR_AND_DS_MEM0_SIZE 0x00400000

#   define DEC2155X_CSR_AND_DS_MEM0_TYPE (PCI_BAR_SPACE_MEM | \
                                          PCI_BAR_MEM_ADDR32)

#   define DEC2155X_CSR_AND_DS_MEM0_TRANS PCI_SLV_MEM_BUS

    /* Downstream windows 1, 2 and 3 not used (disabled) */

#   define DEC2155X_DS_IO_OR_MEM1_SIZE   0x00000000
#   define DEC2155X_DS_IO_OR_MEM1_TYPE   (PCI_BAR_SPACE_MEM | \
                                          PCI_BAR_MEM_ADDR32)
#   define DEC2155X_DS_IO_OR_MEM1_TRANS   0x00000000

#   define DEC2155X_DS_MEM2_SIZE         0x00000000
#   define DEC2155X_DS_MEM2_TYPE         (PCI_BAR_SPACE_MEM| \
                                          PCI_BAR_MEM_ADDR32 )
#   define DEC2155X_DS_MEM2_TRANS        0x00000000

#   define DEC2155X_DS_MEM3_SIZE         0x00000000
#   define DEC2155X_DS_MEM3_TYPE         (PCI_BAR_SPACE_MEM| \
                                          PCI_BAR_MEM_ADDR32 )
#   define DEC2155X_DS_MEM3_TRANS        0x00000000

    /* Upstream windows (for access to Compact PCI backpanel) */

    /*
     * note that upstream translation values are relative to the Compact PCI
     * memory map not the local processor address map. 0x00000000 is the
     * base of PCI memory space as seen from the Compact PCI bus (primary
     * side of the 2155x).
     */

    /* 4MB window into host (system slot) DRAM. */

#   define DEC2155X_US_IO_OR_MEM0_SIZE 0x00400000
#   define DEC2155X_US_IO_OR_MEM0_TYPE (PCI_BAR_SPACE_MEM | \
                                        PCI_BAR_MEM_ADDR32)

#   define DEC2155X_US_IO_OR_MEM0_TRANS CPCI_MSTR_MEM_BUS /* map to DRAM */

    /*
     * 32MB window into Compact PCI memory space to access non-system boards
     * NOTE: this window must be large enough to cover the pci memory area
     * configured in the host for dynamic pci device allocation. the
     * translation value for this window should equal the pci memory base
     * address for this area.
     */

#   define DEC2155X_US_MEM1_SIZE 0x02000000
#   define DEC2155X_US_MEM1_TYPE (PCI_BAR_SPACE_MEM | \
                                  PCI_BAR_MEM_ADDR32)

#   define DEC2155X_US_MEM1_TRANS 0x00000000 /* 0xc0000000 from pci bus */

#   define DEC2155X_US_MEM2_PG_SZ 0x00000000 /* close window */

#endif /* INCLUDE_DEC2155X */

/*
 * PMC Configuration (CMC Capabilities):
 * The PMCs can be configured to support different CMC capabilities by
 * configuring the BUSMODE bits in the control registers.  The default
 * will be configured to support PCI protocol (PMC_PCI_PROTOCOL).
 *
 * By setting PMC1_CNFG_MODE and PMC2_CNFG_MODE to the desired configuration,
 * each PMC can be setup for the desired type of module:
 *
 * PMC_CMC_INDEPENDENT	- Independent of CMC capabilities
 * PMC_PCI_PROTOCOL	- Capable of performing PCI protocol (PMC)
 * PMC_SBUS_PROTOCOL	- Capable of performing SBus protocol
 */

#define	PMC_CMC_INDEPENDENT		0
#define	PMC_PCI_PROTOCOL		1
#define	PMC_SBUS_PROTOCOL		2

#define	PMC_CNFG_MODE			PMC_PCI_PROTOCOL

/*
 * PCI autoconfiguration "roll call" list:
 * Each entry in the "roll call" list defined below, consists of two
 * separate components: a "count" component followed by a PCI header
 * "vendor/ID value" component.  During the first phase of PCI
 * autoconfiguration, the "enumeration" phase, the PCI busses are
 * dynamically probed and a list of devices actually found is
 * constructed.  After the enumeration pass is complete, the
 * dynamically created list of actual devices is compared against the
 * "roll call" list.  For each defined "device/vendor ID" in the roll
 * call list, the corresponding entry in the dynamically created
 * enumeration list is queried.  If the dynamic list indicates fewer
 * devices of the desired type than the "roll call" list does, the PCI
 * enumeration pass is performed again and a new dynamic list is
 * created.  This process will continue until the roll call list is
 * actually satisfied by devices found during dynamic enumeration or
 * until a timeout value (specified by ROLL_CALL_MAX_DURATION) is
 * exceeded.  After the enumeration phase is completed (by satisfying
 * the "roll call" list or by exceeding the roll call timeout), the
 * second phase of PCI autoconfiguration (address assignment) is
 * performed.
 * 
 * The roll call list is useful for holding off autoconfiguration while
 * devices make themselves visible on the cPCI bus.
 * 
 * ROLL_CALL_MAX_DURATION defines the maximum number of seconds that
 * the enumeration process will run before PCI configuration proceeds.  
 * That is, even if the roll call repeatedly fails, the configuration 
 * will proceed anyway after ROLL_CALL_MAX_DURATION seconds.
 * 
 * To eliminate roll call checking altogether, simply make sure that
 * PCI_ROLL_CALL_LIST_ENTRIES is not defined.
 *
 * The example below, which is commented out, shows how to set up the
 * roll call list to specify one Dec21554 device with a roll call
 * timeout value of 100 seconds.
 *
 * #define ROLL_CALL_MAX_DURATION 100 
 *
 * #define DEC21554_COUNT 1
 *
 * #define PCI_ROLL_CALL_LIST_ENTRIES \
 *     { DEC21554_COUNT, PCI_ID_BR_DEC21554 }, 
 */ 

#include "cpv3060.h"				/* include cpv3060 params */

#ifdef __cplusplus
    }
#endif

#endif	/* INCconfigh */

#if defined(PRJ_BUILD)
#  include "prjParams.h"
#endif


#if defined(PRJ_BUILD)
#include "prjParams.h"
#endif