config.h

VxWorks下 Cpv3060的BSP源代码

/* cpv3060/config.h - Motorola CPV3060 board configuration header */

/* Copyright 1984-2000 Wind River Systems, Inc. */
/* Copyright 1997-2000 Motorola, Inc., All Rights Reserved */

/*
modification history
--------------------
01u,30apr03,jtp  Correct BSP Revision to WR standard
01t,05dec00,rhk  Cleanup to comply with WRS coding standards.
01s,03oct00,rhk  Changed BSP_REV to 0.3 due to SBRAM size check fix.
01r,30sep99,srr  Changed BSP_REV to 0.2 for latest release.
01q,13sep99,rhk  removed CPM ethernet defines.
01p,01sep99,rhk  moved SBRAM_SIZE define to cpv3060.h as part of SBRAM
		 autosizing implementation.
01o,31aug99,rhk  changed ethernet driver support from if_fec to motFecEnd.
01n,25aug99,srr  Updated support for non-MCPN750 cPCI boards.
01m,28jul99,srr  Added support for non-Sitka cPCI boards.
01l,13jul99,rhk  code review changes.
01k,12jul99,rhk  added define to allow manual sizing of SBRAM.
01j,16jun99,rhk  changed RAM_HIGH_ADRS to start at 0x00800000, changed the
		 the 2 PMC config mode defines to be 1 generic define.
01i,14jun99,srr  removed PCI Auto Config exclusion list in place of WRS version,
                 changed to support WRS PCI naming conventions.
                 Made SM_INT_ARG2 for mailbox ints byte-long, not word-long.
                 removed global flag setting to indicate non ROM based.
                 define PCI_MAX_DEV to remove entries above dev #15 for QSpan.
01h,11jun99,srr  Replaced SM_INT_ARG2 calculation with a function call.
                 Modify drawbridge translation window to match with new
                 address used for dynamic pci allocation.
                 Added INCLUDE_BSD so attach is called for netif sm driver only.
                 Added Tornado 2.0 support: BSP_VER_1_2, project build.
                 Changed RAM_HIGH_ADRS to 8 MB,
                 Changed BSP revisions.
                 Changed to WRS address space naming convention.
                 Removed NETIF driver references.
                 Remove INCLUDE_DC references and support.
01g,09jun99,srr  changed to support cpv3060.
01f,30nov98,rhk  added defines to support the Shared Memory interface.
01e,11nov98,rhk  added defines to support Drawbridge chip.
01d,02oct98,srr  added support for PCI Auto Configuration.
01c,22sep98,srr  disabled data cache due to MPC860 Rev B errata
                 which caused problems with the FEC.
01b,10sep98,rhk  added CPV3160 specific defines, removed MBX defines.
01a,27aug98,rhk  ported to CPV3160 from MBX version 01q.
*/

/*
This file contains the configuration parameters for the Motorola CPV3060
boards.
*/

#ifndef	INCconfigh
#define	INCconfigh

#ifdef __cplusplus
    extern "C" {
#endif

/* 
 * BSP version/revision identification, should be placed
 * before #include "configAll.h"
 */

#define BSP_VER_1_1     1
#define BSP_VER_1_2     1
#define BSP_VERSION     "1.2"	/* Tornado 2.2 is 1.2 */
#define BSP_REV         "/3"	/* increment by whole numbers */

#include "configAll.h"
#include "sysMotCpci.h"

#define DEFAULT_BOOT_LINE \
"fec(0,0)host:/tor/target/config/cpv3060/vxWorks h=90.0.0.3 e=90.0.0.50 u=target"
#define WRONG_CPU_MSG "This must be a CPV3060 VxWorks image!\n";

/*
 * The following cPCI address accesses the beginning of system
 * (cPCI master) DRAM.  This should be set to:
 *     0x80000000 if the cPCI master is an MCP750;
 *     0x00000000 if the cPCI master is a CPV5000.
 */

#define CPCI_MSTR_MEM_BUS	0x80000000

/* define, if SHOW routines are to be included */

#undef INCLUDE_SHOW_ROUTINES

/*
 * NONFATAL_VPD_ERRORS is a debug build switch which, when defined, allows
 * the BSP to tolerate what would otherwise be fatal VPD errors.
 */

#undef NONFATAL_VPD_ERRORS 		/* define to debug VPD info */

#define MPC860T				/* Identify if processor is MPC860T */

/* 
 * Define the serial port to use
 * Available port settings:
 * SERIAL_PORT_SMC
 * SERIAL_PORT_SCC
 */

#define SERIAL_PORT 		SERIAL_PORT_SMC

/* Cache and MMU supported */

#define USER_I_MMU_ENABLE
#define USER_D_MMU_ENABLE
#define INCLUDE_MMU_BASIC

#undef USER_D_CACHE_ENABLE              /* disable due to MPC860 Rev B errata */

/* add necessary drivers */

#define INCLUDE_PCI			/* include the PCI library support */

#define INCLUDE_END              /* Enhanced Network Driver see configNet.h */

#if defined (MPC860T) && defined (INCLUDE_END)
#   define INCLUDE_MOT_FEC              /* define if you are using the FEC. */
#else
#    undef INCLUDE_MOT_FEC
#endif  /* MPC860T */

/* Optional Drivers */

#undef  INCLUDE_TIMESTAMP		/* Optional timestamp support */
#define INCLUDE_DEC2155X
#define INCLUDE_QSPAN

/*
 * INCLUDE_SM_NET and INCLUDE_SM_SEQ_ADDR are the shared memory backplane
 * driver and the auto address setup which are defined in configAll.h.
 * To exclude them, uncomment the following lines:
 *
 * #undef INCLUDE_SM_NET
 * #undef INCLUDE_SM_SEQ_ADDR
 */

/* remove unnecessary drivers */

#undef INCLUDE_BP
#undef INCLUDE_EX
#undef INCLUDE_ENP

/* Shared-memory Backplane Network parameters */

#if defined(INCLUDE_SM_NET)

#   define SM_INT_TYPE  SM_INT_MAILBOX_1  /* "doorbell" register int. */
#   define SM_INT_ARG3  (1 << (DEC2155X_SM_DOORBELL_BIT % 8))
#   define SM_OFF_BOARD TRUE       /* Memory pool is off-board */
#   define STANDALONE_NET
#   define INCLUDE_NET_SHOW
#   define INCLUDE_BSD

   /*
    * If the anchor is offboard (SM_OFF_BOARD == TRUE) then place the
    * anchor SM_ANCHOR_OFFSET at 0x4100 if the actual anchor is on an
    * MCP750 or CPV3060, or place it at 0x1100 if the actual anchor is
    * on a CPV5000.
    */

#   undef SM_ANCHOR_ADRS
#   if (SM_OFF_BOARD == TRUE)
#      undef SM_ANCHOR_OFFSET
#      define SM_ANCHOR_OFFSET 0x4100  /* define as 0x1100 for CPV5000 master */
#      define SM_ANCHOR_ADRS		(sysSmAnchorAdrs())
#      define SM_MEM_ADRS    (SM_ANCHOR_ADRS + (0x4d00 - SM_ANCHOR_OFFSET))
#   else
#      define SM_MEM_ADRS    0x00004d00
#      define SM_ANCHOR_ADRS ((char *)(LOCAL_MEM_LOCAL_ADRS + SM_ANCHOR_OFFSET))
#   endif

#   if (SM_OFF_BOARD == TRUE)
#      define SYS_SM_ANCHOR_POLL_LIST \
	    SYS_MOT_SM_ANCHOR_POLL_LIST
#   endif /* (SM_OFF_BOARD == TRUE */

    /*
     * The following defines are only used by the master.
     * The slave only uses the "Anchor" address.
     */

#   define SM_MEM_SIZE		0x00010000
#   define SM_OBJ_MEM_ADRS      (SM_MEM_ADRS+SM_MEM_SIZE) /* SM Objects pool */
#   define SM_OBJ_MEM_SIZE      0x00010000

    /*
     * Finding the shared memory anchor:
     *
     * There are three ways to communicate the location of the anchor to the
     * initialization code:
     *
     * 1) If "sm=xxxxxxxx" is specified as a boot parameter, then "xxxxxxxx"
     *    is used as the local address of the anchor.
     *
     * 2) If case (1) above is not satisfied, then if SM_OFF_BOARD is FALSE,
     *    the address LOCAL_MEM_LOCAL_ADRS + SM_ANCHOR_OFFSET is used as the
     *    local address of the anchor.
     *
     * 3) If neither (1) or (2) above is satisfied (that is "sm=xxxxxxxx" is
     *    NOT specified AND SM_OFF_BOARD is defined as TRUE) then the shared
     *    memory anchor is found via a polling algorithm as described below:
     *
     *    Devices on the compactPCI bus (defined by SYS_SM_CPCI_BUS_NUMBER)
     *    are queried through the first memory BAR.  Memory at offset
     *    SM_ANCHOR_OFFSET is examined to determine if the anchor is there.
     *
     *
     *    If SYS_SM_ANCHOR_POLL_LIST is defined then only those
     *    devices whose device/vendorID and subsystem device/vendorID
     *    are defined in this list are queried.  If SYS_SM_ANCHOR_POLL_LIST
     *    is NOT defined then ALL devices found on SYS_SM_CPCI_BUS_NUMBER
     *    are queried.
     *
     *    In addition if SYS_SM_SYSTEM_MEM_POLL is defined, the
     *    system memory (at compact PCI address CPCI_MSTR_MEM_BUS +
     *    SM_ANCHOR_OFFSET) is also queried for a possible location for
     *    the anchor.  If SYS_SM_SYSTEM_MEM_POLL is not defined, then
     *    system memory is not polled.  This option would typically be
     *    used if the anchor resided on an MCP750 and the initialization
     *    code was running on an MCPN750.
     */

#   define SYS_SM_SYSTEM_MEM_POLL

    /*
     * When shared memory anchor polling is enabled, the following defines the
     * PCI bus number on which to poll devices for the shared memory anchor.
     */

#   define SYS_SM_CPCI_BUS_NUMBER    1

    /*
     * SM_INT_ARG1 is calculated in sysSmParamsCompute(), "sysLib.c"
     * SM_INT_ARG2 is dynamically calculated in sysSmArg2Compute(), "sysLib.c"
     */
 
#   ifndef _ASMLANGUAGE
        IMPORT  char * sysSmAnchorAdrs();
        IMPORT	int    smIntArg1;
	int	sysSmArg2Compute (void);
#   endif

#   define SM_INT_ARG1     (smIntArg1)
#   define SM_INT_ARG2	   (sysSmArg2Compute())

#endif /* defined(INCLUDE_SM_NET) */


/*
 * Note: CPV3060 requires a modified software Test and Set algorithm.
 * SM_TAS_TYPE is set to SM_TAS_HARD despite the lack of a hardware TAS
 * mechanism to force the use of a BSP-specific software TAS algorithm. The
 * modified algorithm is required to work around a problem encountered with
 * PCI-to-PCI bridges.
 */

#undef SM_TAS_TYPE
#define SM_TAS_TYPE		SM_TAS_HARD

/* Memory addresses */

#define LOCAL_MEM_LOCAL_ADRS	0x00000000	/* Base of RAM */
#define LOCAL_MEM_SIZE		0x01000000	/* 16 Mbyte is the default */ 

/*
 * To have the kernel perform dynamic memory sizing, add the define for
 * LOCAL_MEM_AUTOSIZE.  
 * Warning: when building the bootrom with this define enabled,
 * it can take up to 16 seconds for the boot prompt to appear
 * after power is applied.  ( The kernel clears all unused memory )
 */

#define  LOCAL_MEM_AUTOSIZE

/*
 * The constants ROM_TEXT_ADRS, ROM_SIZE, and RAM_HIGH_ADRS are defined
 * in config.h, and Makefile.
 * All definitions for these constants must be identical.
 */

#define ROM_BASE_ADRS		0xFE000000	/* base address of ROM */
#define ROM_TEXT_ADRS		(ROM_BASE_ADRS + 0x100)

#define ROM_SIZE		0x00080000 	/* 512K ROM space */

/* RAM address for ROM boot */

#define RAM_HIGH_ADRS		(LOCAL_MEM_LOCAL_ADRS + 0x00800000)

/* RAM address for sys image */

#define RAM_LOW_ADRS		(LOCAL_MEM_LOCAL_ADRS + 0x00100000)

#define USER_RESERVED_MEM	0x00000000	/* user reserved memory size */

/*
 * Select default CPU power management mode. Power management
 * modes available on PPC860 are,
 * 
 *   VX_POWER_MODE_DISABLE,  disable power management
 *   VX_POWER_MODE_FULL,  all CPU units are active
 *   VX_POWER_MODE_DOZE,  `doze'  mode
 *   VX_POWER_MODE_SLEEP,  `sleep' mode
 *   VX_POWER_MODE_DEEP_SLEEP,  `deep-sleep' mode
 *   VX_POWER_MODE_DOWN,  all units are down
 *
 * The CPU is set to DEFAULT_POWER_MGMT_MODE in sysHwInit().
 */

#define DEFAULT_POWER_MGT_MODE  VX_POWER_MODE_DISABLE

/* 
 * The following macros define access to PCI space from the CPU,
 * and access to local DRAM from the PCI bus.  
 *
 * See target.nr for descriptions of PCI Space configurations.
 *
 * NOTE: when changing address bases or size values, be careful not
 * to overlap with any other address spaces defined for the system.
 *
 * Map local access to PCI ISA I/O Space
 *
 *   ISA_MSTR_IO_LOCAL 	- Base address for ISA I/O access
 *   ISA_MSTR_IO_BUS	- Base address of ISA I/O space on Bus
 *   ISA_MSTR_IO_SIZE	- Size of ISA I/O window
 *
 * Map local access to PCI I/O Space (above ISA I/O space)
 *
 *   PCI_MSTR_IO_LOCAL 	- Base address for PCI I/O access
 *   PCI_MSTR_IO_BUS	- Base address of PCI I/O space on Bus
 *   PCI_MSTR_IO_SIZE	- Size of PCI I/O window
 *
 * Map local access to ISA Mem Space (non-prefetchable)
 *
 *   PCI_MSTR_MEMIO_LOCAL	- Base address for ISA Mem access
 *   PCI_MSTR_MEMIO_BUS		- Base address of ISA Mem space on Bus
 *   PCI_MSTR_MEMIO_SIZE	- Size of ISA Mem window
 *
 * Map local access to PCI Mem Space
 *
 *   PCI_MSTR_MEM_LOCAL	- Base address for PCI Mem access
 *   PCI_MSTR_MEM_BUS	- Base address of PCI Mem space on Bus
 *   PCI_MSTR_MEM_SIZE	- Size of PCI Mem window
 *
 * Map PCI memory access to local CPU space
 *
 *   PCI_SLV_MEM_LOCAL	- Base address of Local CPU space
 *   PCI_SLV_MEM_BUS	- Base address of local memory as seen from PCI Bus