target.nr

VxWorks下 Cpv3060的BSP源代码

Vector#    Assigned to
-------    ---------------------------------------------------------------
  0x20     Error
  0x21     Parallel I/O [4]
  0x22     Parallel I/O [5]
  0x23     SMC 2/PIP
  0x24     SMC 1
  0x25     SPI
  0x26     Parallel I/O [6]
  0x27     Timer 4
  0x28     reserved
  0x29     Parallel I/O [7]
  0x2A     Parallel I/O [8]
  0x2B     Parallel I/O [9]
  0x2C     Timer 3
  0x2D     reserved
  0x2E     Parallel I/O [10]
  0x2F     Parallel I/O [11]
  0x30     I2C
  0x31     Risc Timer Table
  0x32     Timer 2
  0x33     reserved
  0x34     IDMA2
  0x35     IDMA1
  0x36     SDMA bus error
  0x37     Parallel I/O [12]
  0x38     Parallel I/O [13]
  0x39     Timer 1
  0x3A     Parallel I/O [14]
  0x3B     reserved
  0x3C     reserved
  0x3D     SCC2
  0x3E     SCC1
  0x3F     Parallel I/O [15]
.CE

The specific DEC2155X interrupts are:

.CS

Vector#    Assigned to
-------    ---------------------------------------------------------------
  0x60     DEC2155X DOORBELL 0
  0x61     DEC2155X DOORBELL 1
  0x62     DEC2155X DOORBELL 2
  0x63     DEC2155X DOORBELL 3
  0x64     DEC2155X DOORBELL 4
  0x65     DEC2155X DOORBELL 5
  0x66     DEC2155X DOORBELL 6
  0x67     DEC2155X DOORBELL 7
  0x68     DEC2155X DOORBELL 8
  0x69     DEC2155X DOORBELL 9
  0x6a     DEC2155X DOORBELL 10
  0x6b     DEC2155X DOORBELL 11
  0x6c     DEC2155X DOORBELL 12
  0x6d     DEC2155X DOORBELL 13
  0x6e     DEC2155X DOORBELL 14
  0x6f     DEC2155X DOORBELL 15
  0x70     DEC2155X POWER MANAGEMENT
  0x71     DEC2155X I2O
  0x72     DEC2155X PAGE CROSSING
.CE

.SS "Serial Configuration"

The Serial port selections supported are via the SMC1 or the SCC2
interface in the MPC860 communications processor module.

The serial port can be configured in one of two ways:

.IP "1)"
As SMC1 (part of the MPC860 communications processor module).
To configure this way, set SERIAL_PORT to SERIAL_PORT_SMC in "config.h".

.IP "2)"
As SCC2 (part of the MPC860 communications processor module).
To configure this way, set SERIAL_PORT to SERIAL_PORT_SCC in "config.h".
.LP

.SS "SCSI Configuration"
SCSI is not supported as a standard feature on the CPV series boards.

.SS "Network Configuration"
CPV boards with an MPC860T processor provide a 10Base-T/100BaseTX Fast
Ethernet Controller module.  This replaces the Ethernet interface used via the
SCC1 port.  The FEC module will automatically select the fatest transfer rate
available.

Each CPV board is assigned a unique  Media Access Control (ethernet) address.
The address is of the form 0x08003EXXXXXX, where 0x08003E is the 
identification for Motorola MCG and 0xXXXXXX is a unique serial number 
assigned to each CPV board by MCG.  The MAC address is read out of SROM
during sysHwInit.

.SS "VME Access"
Does not apply.

.SS "PCI Access"
The PCI bus is fully supported under rev 2.1 of the standard.  All configuration
space accesses are made with BDF (bus #, device #, function #) format calls in
the pciConfigLib module.

.CS
        CPU to PCI Memory Map (default base addresses)

CPU             PCI           Max Size              Access to
--------------------------------------------------------------
0x80000000      0x00000000       64 KB          ISA I/O space
0x80010000      0x00010000      511 MB          PCI I/O space

0xC0000000      0x00000000       64 MB          ISA MEM space
0xC4000000      0x04000000      448 MB          PCI MEM space

	PCI to CPU Memory Map

PCI             CPU         Max Size             Access to
-----------------------------------------------------------
0x80000000      0x00000000      2 GB            local DRAM
.CE

.SS "PCI Space Configuration (CPU to PCI)"

The CPU to PCI Memory Map can be altered by changing the values of the
PCI_MSTR_xxx defines in config.h.  In specifying the CPU base addresses
that will translate to the PCI bus, only the PCI I/O base can be altered.
The PCI Memory space will automatically be set based on the value from
ISA_MSTR_IO_LOCAL (it will be calculated as ISA_MSTR_IO_LOCAL + 0x40000000).
This is due to the fact that the second most significant bit of the address
lines from the CPU is hardwired to the Image Select (IMSEL) line of the
QSPAN chip.  It is also important to note that this bit must not be set when
used for the PCI I/O base address.

The address being translated to on the PCI bus can be specified for Memory
space only.  The define "PCI_MSTR_MEM_BUS" would be set with the value to
be used on the PCI bus.  The tranlation of PCI I/O space must be to zero
based addressing on the PCI bus due to legacy issues with ISA devices.

Sizing windows can be set for CPU to PCI address translations.  The 
first set specify the window for CPU access to the QBUS, the second specifies
the window for QBUS access to the individual PCI space via the QSPAN.
The size for CPU access to the QBUS is set by the "PCI_MSTR_IO_SIZE"
define.  This value is used for both I/O and MEM space access to the QBUS,
due to the fact that they share a CPU access window.  The size value will
determine how much each space will have available for access to the QBUS
from its respective CPU base address.  The second sizing windows setup
the 4 PCI/ISA windows defined in the Page Table Entries.  These windows 
determine where access to PCI I/O amd Mem space and ISA I/O and Mem
space will occur.  They also define the true amount of space accessible
for each space (from a programming point of view ).  Care must be taken
when expanding the PCI I/O and PCI MEM window sizes, they require
64KB of local memory per 8MB of PCI space mapped.

The total size for (PTE_ISA_IO_SIZE + PTE_PCI_IO_SIZE) must be less
than or equal to PCI_MSTR_IO_SIZE.
The total size for (PTE_ISA_MEM_SIZE + PTE_PCI_MEM_SIZE) must be
less than or equal to PCI_MSTR_IO_SIZE.

The third set of windows are configured by modifying a QSPAN_QBSI_xxxx
code for the defines "QSPAN_MSTR_IO_SIZE" and "QSPAN_SLV_MEM_SIZE" and specifies
how much each of address space will actually be decoded onto the PCI bus by
the QSPAN chip.  The size for these two defines does not have to be the same.
The size should not exceed the value for "PCI_MSTR_IO_SIZE".

.SS "PCI Space Configuration (PCI to CPU)"

The only access from the PCI to CPU space is from PCI Memory space.
The define "PCI_SLV_MEM_BUS" is the base address as seen on the PCI bus,
and the "PCI_SLV_MEM_LOCAL" is the base address of local memory in CPU
space.  The defines "PCI_SLV_MEM_SIZE" and "QSPAN_SLV_MEM_SIZE" are used 
in determining how much CPU space is accessible, and should be set to
the same sizes.

.SS "QSPAN Chip Upgrade"

The QSPAN CPU to PCI bridge chip provides an interface between the CPV
processor bus (called the QBus) and the PCI Bus.  Revisions 1.0 and 1.1
of the QSPAN chip could not support normal termination of PCI configuration
cycles.  This requires the installation of a machine check handler every
time a PCI configuration space access is made, otherwise the kernel will
hang.  Starting with the revision 1.2 QSPAN, a new bit field (MA_BE_D)
has been added to the MISC_CTL register.  Setting this bit will cause PCI
configuration reads and writes to appear as normal terminations on the 
QBus, eliminating the need for the special handling.

The 1.2 revision has also added support for QBus Master burst writes and
prefetch reads.  These will not be implemented as part of the QSPAN driver.
The QSPAN 1.2 addendum recommends that burst write not be used when using
the UPM tables for memory access, which this BSP does implement.

.SS "Boot Devices"
The supported boot devices are:

.CS
motfec  - ethernet (10baseT or 100baseT)
sm      - share memory
.CE

Motorola's EPPC1-Bug can be used to download and run VxWorks.
Consult the respective user's manuals for details.

.SS "Boot Methods"
The boot methods are affected by the boot parameters.  If no password is
specified, RSH (remote shell) protocol is used.  If a password is specified,
FTP protocol is used or, if the flag is set, TFTP protocol is used.

.SS "ROM Considerations"
The following will produce a binary formatted file to be downloaded to
the CPV using EPPC-Bug.

.CS
    make clean
    make bootrom.bin
    cp bootrom.bin /tftpboot/cpv3060/bootrom.bin
    chmod 666 /tftpboot/cpv3060/bootrom.bin
.CE

Using EPPC-Bug on the CPV, the following instructions will flash
the boot.bin (binary image of the bootrom file) into the SOLDERED
FLASH.

To install the boot.bin file in the SOLDERED FLASH parts:

.IP "1)"  
Before you power-up the CPV, make sure the ROM/FLASH jumper (W2) is
installed across pins 1 and 2 to select running from the socketed flash.

	With W2 installed across pins 1 and 2, the:
	- Socketed ROM has an address of 0xFE000000
	- Soldered FLASH has an address of 0xFC000000

If W2 is installed across pins 2 and 3, the above addresses are swapped.
The current, selected device (ROM or FLASH) always is located at 0xFE000000.

.IP "2)"
At the EPPCBug prompt, setup the network transfer from a tftp host using
niot. To use niot, the Client IP Address, Server IP Address, and Gateway
IP Address must be setup for the user's specific environment:

.CS
    EPPC-Bug>niot
    Controller LUN =00? 20
    Device LUN     =00?
    Node Control Memory Address =003C8000?
    Client IP Address      =123.123.10.100? 123.321.12.123
    Server IP Address      =123.123.18.105? 123.321.21.100
    Subnet IP Address Mask =255.255.255.0?
    Broadcast IP Address   =255.255.255.255?
    Gateway IP Address     =123.123.10.254? 123.321.12.254
    Boot File Name ("NULL" for None)     =? .

    Update Non-Volatile RAM (Y/N)? y
    EPPC-Bug>
.CE

.IP "3)"
The file is transferred from the tftp host to the target board using the
niop command. The File Name must be set to the location of the binary file
on the tftp host.

The binary file must be stored in the directory identified for tftp
accesses, but the File Name is a relative path and may not need to include
the /tftpboot directory name:

.CS
    EPPC-Bug>niop
    Controller LUN =20?
    Device LUN     =00?
    Get/Put        =G?
    File Name      =? cpv3060/bootrom.bin
    Memory Address =00004000?
    Length         =00000000?
    Byte Offset    =00000000?

    EPPC-Bug>
.CE

.IP "4)"
After the file is loaded onto the target, use the pflash command to put it 
into the soldered FLASH parts (W2 installed across pins 1 and 2):

    EPPC-Bug>pflash 4000:83fff fc000100

When executing "pflash", you may see eight Data Miscompare Statements in the
verify-phase, this is normal and requires no action.

.IP "5)"
Power down the board, then switch the W2 jumper to 
 pins 2 - 3, and re-apply power to the board.
.LP

.SS "SDRAM Setup"
The SDRAM controller setup is only performed by the boot program. VxWorks
doesn't re-initialize the SDRAM controller when it is executed.
The following are the current SDRAM speed configurations supported:

.bS
        60ns @ 50 MHz
        60ns @ 100 MHz
.bE

To support a different configuration the UpmTable table located in romInit.s
file of the cpv3060 BSP must be changed.

.SS "Dynamic Memory Sizing"
Dynamic sizing of the memory available on the CPV board can be accomplished
by enabling the define for LOCAL_MEM_AUTOSIZE in config.h and then rebuilding
the kernel.  This will automatically make available the full range of
memory on the board.

.SS "Crystal or Oscillator Clock Input"
One of two types of clock input is used on the board.  Either a
32768KHz crystal or a 1:1 oscillator is used as the CPV primary clock
source.  The boot ROM and kernel detect and configure themselves
dynamically to support the configured clock.  No special user
configuration is required.

.SH "SPECIAL CONSIDERATIONS"
This section describes miscellaneous information about the BSP.

.SS "Known Problems"
.PP
1.  The parameter RAM for SCC1 overlaps the parameter RAM
for I2C.  This would normally prevent the ethernet and I2C from
working concurrently.  A microcode patch is installed by i2cMcp.c
during kernel initialization, to work around this problem.  It
relocates the I2C parameter RAM to the location occupied by IDMA1,
which is not used for any other purpose. Thus making both SCC1
and I2C operate concurrently.

.PP
2.  A large switch statement, ( 16 cases for the one tested ) fails to
execute properly when running in ROM.  This appears to be an 860
specific problem, and may only occur with code running in ROM.  When
the same code ( the bootrom ) was executed with a debugger in RAM, the 
error did not occur.

A small switch statement does not exhibit the same failure.  The
reason for this is the way switch statements are compiled into
assembly code.  For small switch statements, the code is compiled as
if it were a series of if-then-else statements.  For a large switch
statement, a jump table is created.  This jump table is the reason 
for the failure in the ROM code.

.PP
3.  In order to use the cpv3060 in a shared memory backplane
configuration with mcp750 and/or mcpn750 boards, the mcp750/mcpn750
Compact PCI backpanel networking patch must be installed on those
boards first.  This will allow the 750 boards to recognize the
version of the DEC21554 Drawbridge chip on the cpv3060.  Contact
your Motorola Sale Representative in order to get a copy of this
patch.

.SH "BOARD LAYOUT"
The diagram below shows jumpers relevant to VxWorks configuration.

.ne 4i

.bS

                           ^                       ^
                           |      To Compact PCI   |
      				     Backplane  
____________________________________________________________________________
|              |             |             |               |               |
|      J5      |             |      J3     |               |      J1       |
|______________|_____________|_____________|_______________|_______________|
|                                                                          |
|  =========== ===========       =========== ===========                   |
|                                                                          |
|  =========== ===========       =========== ===========                   |
|          PMC slot                      PMC slot                          |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                                          |
|         +-----+                                                          |
|         |     |                                                          |
|         |     |                                                          |
|         +-----+                                                          |
|           U21                                                            |
|                                                                          |
| .                                                                        |
| : (W2)                                                                   |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                                          |
|______.......................___.......................____----_____----__|
         PCI Mezzanine Card        PCI Mezzanine Card      10/100    Com1
              Cutout                    Cutout             base T

                                Front of Board
.bE
    Key:
    U21 - Socketed Rom Bank, EPPC1Bug installed
    W2  - three-pin vertical jumper (selects Socketed/Soldered ROM)


.SH "SEE ALSO"
.tG "Getting Started, "
.pG "Configuration"

.SH "BIBLIOGRAPHY"
.iB "Motorola CPV3060 Programmer's Reference Guide,"
.iB "Motorola Computer Group Online Documentation, http://library.mcg.mot.com/mcg/boards"