target.nr

VxWorks下 Cpv3060的BSP源代码

        processor number     : 0
        inet on ethernet (e) : 124.170.16.112:ffffff00
        inet on backplane (b): 124.200.200.1:ffffff00
        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.170.16.233
        target name (tn)     : gamma


   CPV3060-1:

        #define SM_OFF_BOARD TRUE
        #define SYS_CPCI_BUS_NUMBER    1
        #define SYS_SM_SYSTEM_MEM_POLL
        /* #undef INCLUDE_SM_SEQ_ADDR */

        boot device          : sm
        host name            : sunray
        processor number     : 1
        inet on ethernet (e) :
        inet on backplane (b):
        host inet (h)        : 124.170.16.143
        gateway inet (g)     :
        target name (tn)     : alpha


   CPV3060-2:

        (same "config.h" setup as CPV3060-1 above)

        boot device          : sm
        host name            : sunray
        processor number     : 2
        inet on ethernet (e) :
        inet on backplane (b):
        host inet (h)        : 124.170.16.143
        gateway inet (g)     :
        target name (tn)     : beta
.CE

.ne 6
.IP "3)"
CPV3060 master, MCP750 anchor, no sequential addressing:
.CS

   MCP750:

        #define SM_OFF_BOARD TRUE
        #undef  SYS_SM_SYSTEM_MEM_POLL
        #undef  INCLUDE_SM_SEQ_ADDR

        boot device          : sm
        host name            : sunray
        processor number     : 1
        inet on ethernet (e) : 124.170.16.112
        inet on backplane (b): 124.200.200.1
        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.200.200.2
        target name (tn)     : gamma

   CPV3060-1:

        #define SM_OFF_BOARD FALSE
        #define SYS_SM_SYSTEM_MEM_POLL
        #undef  INCLUDE_SM_SEQ_ADDR

        boot device          : motfec
        processor number     : 0
        host name            : sunray
        inet on ethernet (e) : 124.170.16.109
        inet on backplane (b): 124.200.200.2:ffffff00
        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.170.16.233
        target name (tn)     : alpha

   CPV3060-2:

        #define SM_OFF_BOARD TRUE
        #define SYS_SM_SYSTEM_MEM_POLL
        #undef  INCLUDE_SM_SEQ_ADDR

        boot device          : sm
        processor number     : 2
        host name            : sunray
        inet on ethernet (e) : 124.170.16.110
        inet on backplane (b): 124.200.200.3
        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.200.200.2
        target name (tn)     : beta
.CE

.ne 6
.IP "4)"
CPV3060 master, MCP750 anchor, sequential addressing:
.CS

   MCP750:

        #define SM_OFF_BOARD TRUE
        #undef  SYS_SM_SYSTEM_MEM_POLL
        /* #undef  INCLUDE_SM_SEQ_ADDR */

        boot device          : sm
        processor number     : 1
        host name            : sunray
        inet on ethernet (e) :
        inet on backplane (b):
        host inet (h)        : 124.170.16.143
        gateway inet (g)     :
        target name (tn)     : gamma


   CPV3060-1:

        #define SM_OFF_BOARD FALSE
        #define SYS_CPCI_BUS_NUMBER    1
        #define SYS_SM_SYSTEM_MEM_POLL
        /* #undef  INCLUDE_SM_SEQ_ADDR */

        boot device          : motfec
        processor number     : 0
        host name            : sunray
        inet on ethernet (e) : 124.170.16.109:ffffff00
        inet on backplane (b): 124.200.200.1:ffffff00
        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.170.16.233
        target name (tn)     : alpha

   CPV3060-2:

        #define SM_OFF_BOARD TRUE
        #define SYS_CPCI_BUS_NUMBER    1
        #define SYS_SM_SYSTEM_MEM_POLL
        /* #undef  INCLUDE_SM_SEQ_ADDR */

        boot device          : sm
        processor number     : 2
        host name            : sunray
        inet on ethernet (e) :
        inet on backplane (b):
        host inet (h)        : 124.170.16.143
        gateway inet (g)     :
        target name (tn)     : beta
.CE

.ne 6
.IP "5)"
CPV3060 master, CPV3060 anchor, no sequential addressing:
.CS

   MCP750:

        #define SM_OFF_BOARD TRUE
        #undef  SYS_SM_SYSTEM_MEM_POLL
        #undef  INCLUDE_SM_SEQ_ADDR

        boot device          : sm
        processor number     : 1
        host name            : sunray
        inet on ethernet (e) : 124.170.16.112
        inet on backplane (b): 124.200.200.1
        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.200.200.2
        user (u)             : ball
        ftp password (pw) (blank = use rsh):
        flags (f)            : 0x0
        target name (tn)     : gamma


   CPV3060-1:

        #define SM_OFF_BOARD FALSE
        #undef  SYS_SM_SYSTEM_MEM_POLL
        #undef  INCLUDE_SM_SEQ_ADDR

        boot device          : motfec
        processor number     : 0
        host name            : sunray
        inet on ethernet (e) : 124.170.16.109
        inet on backplane (b): 124.200.200.2:ffffff00
        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.170.16.233
        target name (tn)     : alpha

   CPV3060-2:

        #define SM_OFF_BOARD TRUE
        #undef  SYS_SM_SYSTEM_MEM_POLL
        #undef  INCLUDE_SM_SEQ_ADDR

        boot device          : sm
        processor number     : 2
        host name            : sunray
        inet on ethernet (e) : 124.170.16.110
        inet on backplane (b): 124.200.200.3
        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.200.200.2
        target name (tn)     : beta
.CE

.ne 6
.IP "6)"
CPV3060 master, CPV3060 anchor, sequential addressing:
.CS

   MCP750:

        #define SM_OFF_BOARD TRUE
        #undef  SYS_SM_SYSTEM_MEM_POLL
        /* #undef  INCLUDE_SM_SEQ_ADDR */

        boot device          : sm
        processor number     : 1
        host name            : sunray
        inet on ethernet (e) :
        inet on backplane (b):
        host inet (h)        : 124.170.16.143
        gateway inet (g)     :
        target name (tn)     : gamma

   CPV3060-1:

        #define SM_OFF_BOARD FALSE
        #undef  SYS_SM_SYSTEM_MEM_POLL
        /* #undef  INCLUDE_SM_SEQ_ADDR */

        boot device          : motfec
        processor number     : 0
        host name            : sunray
        inet on ethernet (e) : 124.170.16.109:ffffff00
        inet on backplane (b): 124.200.200.1:ffffff00
        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.170.16.233
        target name (tn)     : alpha

   CPV3060-2:

        #define SM_OFF_BOARD TRUE
        #undef  SYS_SM_SYSTEM_MEM_POLL
        /* #undef  INCLUDE_SM_SEQ_ADDR */

        boot device          : sm
        processor number     : 2
        host name            : sunray
        inet on ethernet (e) :
        inet on backplane (b):
        host inet (h)        : 124.170.16.143
        gateway inet (g)     :
        flags (f)            : 0x0
        target name (tn)     : beta
.CE

.SS "Tornado 1.0.1 FEC END Driver Support"
The current BSP only supports the Motorola FEC END driver.

.SS "Memory Map
On-board RAM for these boards always appears at address 0x0 locally
Dynamic memory sizing is supported.  By default, LOCAL_MEM_AUTOSIZE is
defined so that the memory will be auto-sized at hardware initialization 
time.
When auto-sizing is not selected, LOCAL_MEM_SIZE should be set to the size
of DRAM memory available on the board so as to ensure full memory availability
and proper VME addressing.  The default fixed RAM size is set to 16 MB (see
LOCAL_MEM_SIZE in config.h).

The base addresses for the CPV memory setup are programmed in romInit.s,
using the BR and OR registers.

.SS "Default Memory Map"

.CS
        Memory Map from CPU point of view

Start               Size          Access to
------------------------------------------------------------------
0x0                16MB (min)    DRAM
0x0C000000        128KB (min)    optional Burst RAM
0x80000000         64KB (min)    PCI ISA I/O space
0x80010000        511MB (max)    PCI I/O space
0xC0000000         64MB (min)    PCI ISA MEM space
0xC4000000        448MB (max)    PCI MEM space
0xFA000000          2MB          NVRAM, Board Control Registers
0xFA200000         16KB          CPV internal memory resources, DPRAM
0xFA210000         64KB          PCI Bus Bridge registers (QSPAN)
0xFC000000          1MB (min)    FLASH memory
0xFE000000        128KB (min)    Boot ROM
.CE


.SS "Data Parameter RAM (DPRAM) MAP"
The diagram below shows the Data Parameter Ram layout for the VxWorks
configuration:
.bS
           ----------------------------- DPRAM base (address = IMMR + 0x2000)
           | 0x200 (512) bytes         |
           | I2C/SCC1 conflict         |
           | microcode patch part 1    |
           |---------------------------| end microcode patch (0x2200)
           | 8 bytes per descriptor    | UART Tx Buffer Descriptor (0x2200)
           |===========================|
           | 16 descriptors @          | UART Rx Buffer Descriptors (0x2210)
           | 8 bytes per descriptor    | 
           |===========================| end UART Rx BDs (0x2290)
           | 80 hex bytes allowed      | UART Tx Buffer (0x2300)
           |===========================|
           | one receive char/buffer   | UART Rx Buffer (0x2380)
           |===========================| 
           | 16 bytes allowed          | I2C Buffer Descriptors (0x2400)
           |---------------------------|
           | 32 bytes allowed          | I2C Buffer (0x2410)
           |===========================|
           | 256 bytes allowed         | SROM temp. buffer (0x2600)
           |---------------------------|
           | 256 bytes allowed         | SROM temp. system values (0x2700)
           |===========================| 
           | 512 bytes                 | romInit temp. stack frame (0x2D00)
           |===========================| 
           | 0x200 (512) bytes         | microcode patch (0x2F00)
           | I2C/SCC1 conflict         |
           | microcode patch part 2    |
           |===========================|
           | 66 hex bytes of parameter | SCC2 Parameter Area (0x3d00) UART
           | info incl. Rx and Tx BD   | 
           | pointers, func codes etc. |
           |===========================|
           | 3A hex bytes of parameter | SMC1 Parameter Area (0x3e80) UART
           | info including Rx and Tx  | 
           | BD pointers, func codes   |
           | etc...                    |
           |---------------------------|
.bE

.SS "Interrupts"
The PowerPC architecture defines a series of 48 vectored exceptions (see the
"PowerPC Microprocessor Family: The Programming Environments" for details).
Of these, all but two are handled by the synchronous exception handler:
External Interrupt and Decrementer which are handled by the asynchronous
exception handler.

By default, the exception handling task excTask() handles all synchronous
exceptions.  It reports an exception and terminates the offending task.

Of the 48 exceptions, only five are of immediate interest:

.CS
Machine Check       - exceptions from probed addresses handled here.
Data Access         - exceptions from unmapped MMU addresses handled here.
Alignment           - alignment exceptions handled here.
Decrementer         - used as system clock interrupt.
External Interrupt  - off-CPU interrupts arrive here.
.CE

The Machine Check exception is used by the vxMemProbe() routine.  It is not
used in any other context.  By default it is handled by excTask().

The Data Access and Alignment exceptions are by default handled by excTask().
The vxMemProbe routine installs it's own handlers here while probing.

The Decrementer and External Interrupt exceptions each have their own 'C'
service stubs.  The Decrementer exception is used solely by the system clock
routine to service the periodic 'tick' interrupts.

The External Interrupt exception stub is connected at startup to the system-
maintained interrupt vector table and BSP-specific intConnect() routine.  All
SIU, CPM, PCI, and ISA interrupts are vectored through this table.

All other exceptions are handled by default by the exception handler task,
excTask().

The system interrupt vector table has 256 entries.  Vectors for the various
devices on the busses are assigned hierarchically as follows:

.CS
Vector#    Assigned to
-------    ---------------------------------------------------------------
00 - 0f    SIU interrupts
10 - 1f    RESERVED
20 - 3f    CPM interrupts
40 - 5f    USER DEFINED
60 - 72    Dec2155x interrupts
73 - ff    USER DEFINED
.CE

The specific SIU vector number assignments are:

.CS
Vector#    Interrupt    Assigned to
-------    --------     --------------------------------------------------
  0x0      IRQ0         Power Fail, non-maskable intr
  0x1      LEVEL0       real-time clock
  0x2      IRQ1         Battery low warning
  0x3      LEVEL1       periodic interrupt timer
  0x4      IRQ2         QSPAN interrupt
  0x5      LEVEL2       timebase counter
  0x6      IRQ3         PMC1 Interrupt C, PMC2 Interrupt B, QSPAN (PCI)
  0x7      LEVEL3       Fast Ethernet (FEC - on the MPC860T chip)
  0x8      IRQ4         PMC1 Interrupt B, PMC2 Interrupt A
  0x9      LEVEL4       CPM controller
  0xA      IRQ5         PMC1 Interrupt A, PMC2 Interrupt D
  0xB      LEVEL5       Unused
  0xC      IRQ6         PMC1 Interrupt D, PMC2 Interrupt C, DEC21554
  0xD      LEVEL6       parallel interface port
  0xE      IRQ7         stop/abort
  0xF      LEVEL7       Unused
.CE

Note: On boards using an MPC860T chip (containing the FEC), the IRQ7 line
is shared with the MII_TX_CLK signal.  When the ETHER_EN bit is set in the
Ethernet Control Register of the FEC, the IRQ7 line will fire incessantly
unless the IRQ7 interrupt mask bit is cleared in the SIU Interrupt Mask 
Register.

The specific CPM vector number assignments are:

.CS