target.nr

VxWorks下 Cpv3060的BSP源代码

    /* calculate the local PCI address of the scratchpad 0
       register */

    bar += DEC2155X_CSR_SCRATCHPAD0;

    /* convert the result to the CPU equivalent address */

    if (sysBusToLocalAdrs (PCI_LOCAL_MEMORY_SPACE, (char *)bar,
                         (char **)&bar) != OK)
        {
        return (ERROR);
        }

    return (bar);
.CE

\f3NOTE:\f1
Using the constant DEC2155X_PCI_DEV_NUMBER ensures that the
on-board Dec2155x is read. If a search of the local PCI bus had
been performed using the Dec2155x device ID, the returned Bus,
Device and Function numbers may have corresponded to a Dec2155x
part found on an installed PMC card.

Once the local CPU address is known, the cPCI address can be derived by
adding the following code fragment before returning the result:
.CS
    if (sysLocalToBusAdrs (PCI_BACKPANEL_MEMORY_SPACE,
                           (char *)bar,
                           (char **)&bar) != OK)
        return (ERROR);
    else
        return (bar);
.CE

.SS "Internal Dec2155x Interrupt Sources"
At start-up, all Dec2155x interrupt sources are masked and cleared.
Before unmasking an interrupt, an application ISR service routine must be
attached to the appropriate Dec2155x interrupt vector using intConnect().
Multiple ISR service routines can be connected to each vector if required
by the application. Once the handler is attached, the interrupt can be
enabled and disabled by calling sysDec2155xIntEnable() or
sysDec2155xIntDisable() as required. Interrupt vector definitions for the
Dec2155x internal interrupt sources are defined in cpv3060.h.

Unique interrupt vectors are provided for each of the 16 bits in the
Dec2155x Secondary IRQ register. Bit 0 (LSB) corresponds to
DEC2155X_DOORBELL0_INT_VEC with the remaining bits mapped in sequence.
These doorbell interrupts can be used for host-to-CPV3060 or
CPV3060-to-CPV3060 event notification. The Dec2155x interrupt handler
clears these interrupts which simplifies the application ISR.

Individual interrupt vectors are also provided for Dec2155x Hot Swap
Power State and I2O in-bound list events. The Dec2155x interrupt handler
also clears these interrupts.

The 64 Upstream Memory 2 BAR Page Crossing interrupts are all presented
on a single interrupt vector and the application ISR is responsible for
clearing the bits serviced. Calls to sysDec2155xIntEnable() and
sysDec2155xIntDisable() enable or disable all 64 interrupts.

The Dec2155x interrupt handler provides a default service routine for all
unclaimed interrupt vectors, including the Upstream Memory 2 BAR Page
Crossing interrupt. The default routine reports the event and clears the
interrupt source.

.SS "Compact PCI Backpanel Interrupts"
The Dec2155x can generate cPCI backpanel interrupts using any of the bits
in the Primary IRQ register if they have been un-masked by the host. The
following code fragment generates a compact PCI backpanel interrupt by
setting bit 15 (MSB) of the Primary IRQ register:

    if (sysBusIntGen (DEC2155X_DOORBELL15_INT_LVL,
                      DEC2155X_DOORBELL15_INT_VEC) != OK)
        return (ERROR);

Note that the cPCI bus does not provide an interrupt vector to the host.
The vector number passed to sysBusIntGen() simply identifies which bit in
the register to set. It is the host's responsibility to locate the
interrupt source and clear the interrupt.

In-bound cPCI backpanel interrupts are routed directed to the CPV3060
CPU via the SIU.  They can be enabled, disabled and handled by calling
sysIntEnable(), sysIntDisable() and intConnect() with the vector
number of the desired backpanel interrupt line.

\f3NOTE:\f1
Great care must be exercised when cPCI backpanel interrupts are
being generated and received simultaneously. If the packpanel
interrupt line driven by the CPV3060 is also enabled for receiving
interrupts, the CPV3060 will be interrupted by its own backpanel
interrupt. This scenario causes complications because the backpanel
interrupts are configured as level sensitive and difficulties are
encountered in determining the party responsible for clearing the
interrupt source. In general, backpanel interrupt generation is
useful for signaling an event to the host, but in-bound packpanel
interrupts have limited usefulness.

.SS "Altering the Default Dec2155x Configuration:

Altering the Dec2155x configuration requires the careful consideration of
several items:

.IP
Dec2155x window sizes and alignment.
.IP
Dec2155x translation values.
.IP
The size and alignment of the host's dynamic PCI configuration area.
.IP
The size and alignment of the CPV3060's dynamic PCI configuration area.
.LP
The Dec2155x window parameters are controlled by #defines in config.h.
There are three defines associated with each window:

.TS C
center;
rw11 lw(4.0i) .
\&..._SIZE	T{
determines the size of the window in bytes and must be an
integral power of two. The minimum size for a PCI I/O
space window is 64 bytes. The minimum size for a PCI
memory space window is 4KB. To disable a window, set the
size to 0. Note that the Dec2155x will not allow the
Primary CSR and Downstream Memory 0 BAR to 0 to be
disabled. If the size of this window is set to zero, the
Dec2155x will default to a 4KB window.
T}

NOTE:	T{
If a window value is not a power of 2, or is below the minimum size, sysLib.c
will not compile.
T}
.TE

.TS C
center;
rw11 lw(4.0i) .
\&..._TYPE	T{
determines the type of the window and any placement
restrictions. For proper operation, the window must be
configured for placement anywhere in the 32-bit PCI
address space.
T}
.TE

.TS C
center;
rw11 lw(4.0i) .
\&..._TRANS	T{
determines the base address of the window on the target
PCI bus. It is important to remember that this is a local
PCI address (downstream window) or a cPCI address
(upstream window). The translation value chosen must be
an even multiple if the window size.
T}

NOTE:	T{
If the translation value is not a multiple of the window
size, sysLib.c will not build.
T}
.TE

The default window sizes can be reduced without altering the sizes of the
dynamic PCI configuration area. However, if the required values are
significantly reduced from the default values, reducing the size of the
dynamic PCI configuration area reduces the size of the MMU page tables at
the ratio of 128:1 (a 128KB reduction saves 1KB of MMU table space).

The size of the PCI memory space used for dynamic PCI configuration is
controlled by PCI_MEM_SIZE in config.h and the area's base address is
controlled by CPU_PCI_MEM_ADRS in cpv3060.h. By default, the PCI master
MCP750 BSP allocates a 32MB area aligned to a 32MB boundary for dynamic
PCI configuration. To access peer CPV3060 DRAM areas, an upstream window
must be opened which matches the size of the host's dynamic PCI
configuration area. For translation to work correctly, the host's
dynamic PCI configuration area must be aligned to a multiple of the
area's size and the corresponding Dec2155x upstream translation register
must contain the area's base cPCI address (not CPU address). Since this
BSP supports peer-to-peer access between CPV3060 DRAM areas, the default
dynamic PCI configuration area for the CPV3060 is 64MB aligned to a 32MB
boundary which satisfies these requirements.

In addition to the peer access window, sufficient space must also be
available for mapping the host DRAM upstream window and any space
required by CPV3060-resident PCI devices. A margin must also be allowed
for areas that are unusable due to window alignment requirements.

If the application does not require peer-to-peer CPV3060 DRAM access, the
large 32MB window used to contain the host's dynamic PCI configuration
area can be eliminated with a corresponding decrease in the required
CPV3060 dynamic PCI configuration area. If peer-to-peer doorbell
interrupts are still required, the doorbell interrupt registers of peer
CPV3060s may be accessed through an I/O window which has much smaller
CPU address space requirements. This would require re-configuring the
default BSP to access host DRAM through Upstream Memory 1 BAR and using
the Upstream I/O or Memory 0 BAR to access the peer CPV3060 doorbell
interrupt registers.

.SS "Shared Memory Support"

The CPV3060 supports shared memory backplane communication.
The Wind River documentation provides a great deal of information
regarding shared memory concepts.  The section below provides tutorial
style information regarding the setup of a shared memory system
involving the MCP750 (PCI bus master) and CPV3060(s).

Setting up a working shared memory system involves proper setting of
certain "config.h" parameters and proper setting of boot parameters
via the "c" command from the boot prompt.  There are three components
involved in shared memory communication which must be configured
properly to create a working system:

.IP "Anchor:"
This is an area of memory which must be accessible to all nodes
participating in shared memory backplane communication.  The anchor
points to the actual shared memory buffer pool which must be located
in the same memory space as the anchor itself.  The associated
"config.h" parameter is SM_ANCHOR_ADRS.  In certain configurations,
nonzero nodes will "poll" for the location of the anchor.  "config.h"
defines which comes into play for polling are SM_OFF_BOARD and
SYS_SM_SYSTEM_MEM_POLL.

.IP "Master node:"
This node is always designated as node zero.  It is the node which
sets up the anchor and shared memory pool.  Once the anchor and shared
memory pool is set up, the master node acts as a peer with the other
nodes.  The node number (0 in this case) is one of the boot parameters
which can be set up with the "c" command from the bootline prompt.

.IP "Sequential addressing:"
This is is governed by a "config.h" parameter, INCLUDE_SM_SEQ_ADDR and is
used when sequential IP addresses are assigned to the participating
nodes.  Node zero is assigned the lowest IP address, followed by nodes
1, 2 etc. which are assigned the subsequent and sequential IP addresses.
The advantage of sequential addressing is that fewer boot parameters
must be specified to configure the system.
.LP

The following restrictions apply to shared memory configurations.

.IP "1)"
Node zero must not boot over the shared memory interface.  Only
nonzero nodes are allowed to boot over the shared memory "sm"
interface.

.IP "2)"
The location of the anchor must be statically determinable by the
master node (node 0).  That is, the location of the anchor must
either be a build-time static parameter or it must be able to
be communicated to the master node via the "sm=xxxxxxxx" boot
configuration parameter.  The nonzero nodes need not know the
location of the anchor at build or boot time but can be configured
to poll for the anchor dynamically.
.LP

Note:  Another piece of shared memory terminology is "host node".
The "host node" is the node which configures the compact PCI bus
during startup initialization.  In a system consisting of an MCP750
and one or more CPV3060s, the "host node" is the MCP750.  Don't confuse
"host node" with "master node".  "Master node" is simply a synonym for
"node 0".  The "host node" may or may not be the "master node".  Note
also that the "host node" need not necessarily be a VxWorks node.

Below are the crucial "config.h" parameters involved in shared memory:

.IP "SM_OFF_BOARD (TRUE or FALSE):"
The parameter has a configurable value of either TRUE or FALSE
and directly determines the value of SM_ANCHOR_ADRS (the anchor
address).

If SM_OFF_BOARD is defined as FALSE, then the anchor is on-board
and SM_ANCHOR_ADRS is defined to be
LOCAL_MEM_LOCAL_ADRS + SM_ANCHOR_OFFSET.
LOCAL_MEM_LOCAL_ADRS is defined as 0x0 in "config.h" and
SM_ANCHOR_OFFSET is defined as 0x4100 in "config.h".

If defined as TRUE, then SM_ANCHOR_ADRS is defined as a function
call: sysSmAnchorAdrs() (defined in "sysLib.c").  This function
will dynamically poll, at system startup, various locations
(explained below) for the exact location of the shared memory
anchor.

Note that if "sm=xxxxxxxx" is used as a boot parameter, then
SM_OFF_BOARD has no effect.  The value of "xxxxxxxx" will be used
as the anchor location regardless of the setting of SM_OFF_BOARD.
If simply "sm" is used as a boot parameter, then SM_OFF_BOARD is
queried at initialization time to determine if polling is required
or not.

.IP "SYS_SM_SYSTEM_MEM_POLL (#define or #undef):"
This define only has an effect if anchor polling is called for
(because SM_OFF_BOARD is defined as TRUE and "sm" is used with no
"=xxxxxxxx").  In this case, simply defining SYS_SM_SYSTEM_MEM_POLL
will cause the node to poll for the anchor at compact PCI bus
address PCI2DRAM_BASE_ADRS + SM_ANCHOR_OFFSET (0x80004100).
"System memory" (which is the host node's DRAM) will
be included as one of the locations where the anchor might reside.
Note that other locations my be polled as well (explained later).

Not defining SYS_SM_SYSTEM_MEM_POLL will prevent the polling of
system  memory for the anchor.

.IP "SYS_SM_ANCHOR_POLL_LIST (#define or #undef):"
This define has an effect only if polling is called for (see
SM_OFF_BOARD explained above).  When defined,
SYS_SM_ANCHOR_POLL_LIST allows a list of devices, identified by
device/vendor ID and subsystem ID/subsystem vendor ID to be
specified as candidates for the anchor location.  Devices which
appear directly on the compact PCI bus are found and if they
appear on the list defined by SYS_SM_ANCHOR_POLL_LIST, they are
checked to see if they house the shared memory anchor.  The memory
defined by the first memory BAR is queried at offset
SM_ANCHOR_OFFSET (0x4100 by default, defined in "configAll.h").  If
SYS_SM_ANCHOR_POLL_LIST is not defined, ALL devices on the compact
PCI bus will be considered candidates for the anchor location and
will be polled.  If SYS_SM_ANCHOR_POLL_LIST defined but empty, NO
devices on the compact PCI bus will be considered candidates for
the anchor location.  In that case, the only location polled would
be system memory if SYS_SM_SYSTEM_MEM_POLL (see above) was defined.

.IP "INCLUDE_SM_SEQ_ADDR (#define or #undef)"
If "undef'ed", sequential addressing is disabled.  This symbol
is defined by default.
.LP

Consider a system consisting of an MCP750 (host node) and two CPV3060s.
The following six configurations are the only ones possible:

.TS E
expand;
lf3 lf3 lf3 lf3
l l l l .
.ne 8
.sp .5
	Master node on...	Anchor on...	Sequential Addressing?
_
1.	MCP750	MCP750	NO
2.	MCP750	MCP750	YES
3.	CPV3060	MCP750	NO
4.	CPV3060	MCP750	YES
5.	CPV3060	CPV3060	NO
6.	CPV3060	CPV3060	YES
.TE

Below is a description of how each of the above systems would be
configured.  Crucial "config.h" and boot parameter settings for an
example system are given.  In each example, SYS_SM_ANCHOR_POLL_LIST
was defined to contain information identifying the Dec2155x bridge
chip (present on the CPV3060).  See "config.h" for the example of
how this was done.

.ne 6
.IP "1)"
MCP750 master, MCP750 anchor, no sequential addressing:
.CS

   MCP750:

        #define SM_OFF_BOARD FALSE
        #undef  SYS_SM_SYSTEM_MEM_POLL
        #undef  INCLUDE_SM_SEQ_ADDR

        boot device          : dc
        host name            : sunray
        processor number     : 0
        inet on ethernet (e) : 124.170.16.112
        inet on backplane (b): 124.200.200.1:ffffff00
        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.170.16.233
        target name (tn)     : gamma

   CPV3060-1:

        #define SM_OFF_BOARD TRUE
        #define SYS_SM_SYSTEM_MEM_POLL
        #undef  INCLUDE_SM_SEQ_ADDR

        boot device          : sm
        host name            : sunray
        processor number     : 1
        inet on ethernet (e) : 124.170.16.109
        inet on backplane (b): 124.200.200.2
        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.200.200.1
        target name (tn)     : alpha

   CPV3060-2:

        (same "config.h" setup as CPV3060-1 above)

        boot device          : sm
        host name            : sunray
        processor number     : 2
        inet on ethernet (e) : 124.170.16.110
        inet on backplane (b): 124.200.200.3
        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.200.200.1
        target name (tn)     : beta
.CE

.ne 6
.IP "2)"
MCP750 master, MCP750 anchor, sequential addressing:
.CS

   MCP750:

        #define SM_OFF_BOARD FALSE
        #define SYS_CPCI_BUS_NUMBER    1
        #undef SYS_SM_SYSTEM_MEM_POLL
        /* #undef INCLUDE_SM_SEQ_ADDR */

        boot device          : dc
        host name            : sunray