target.nr

VxWorks下 Cpv3060的BSP源代码

'\" t
.so wrs.an
.\" cpv3060/target.nr - Motorola CPV3060 target specific documentation
.\"
.\" Copyright 1984-2000 Wind River Systems, Inc.
.\" Copyright 1997-2000 Motorola, Inc., All Rights Reserved
.\"
.\" modification history
.\" --------------------
.\" 01l,06feb01,rcs  removed reference to motFecEnd.obj
.\" 01k,22nov00,rhk  cleaned up DPRAM memory map, changed fec to motfec.
.\" 01j,17sep99,rhk  added support information regarding the Motrorola
.\" 		     FEC END driver.
.\" 01i,28jul99,srr  made if_fec driver standalone (if_fec.obj).
.\" 01h,28jul99,rhk  added SENS shared memory support info., made
.\" 		     additional cleanup changes.
.\" 01g,23jul99,rhk  made additional updates to support the cpv3060.
.\" 01f,14jun99,srr  changed to support WRS PCI naming conventions.
.\" 01e,09jun99,srr  changed to support cpv3060.
.\" 01d,07dec98,rhk  added board layout.
.\" 01c,04dec98,rhk  added shared memory and dec2155x driver support
.\"		      information.
.\" 01b,27oct98,srr  added pciAutoConfig support information.
.\" 01a,31aug98,rhk  ported to CPV3160 from MBX version 01j.
.\"
.\"
.TH "cpv3060" T "Motorola CPV3060" "Rev: 09 Jun 99" "VXWORKS REFERENCE MANUAL"

.SH "NAME"
.aX "Motorola CPV3060"

.SH "INTRODUCTION"
This note provides board-specific information necessary to run
VxWorks.  Before running VxWorks, verify that the board runs in the
factory configuration (i.e. EPPC1-Bug (tm) mode).
The cpv3060 BSP produces a VxWorks image running on the PowerPC 
MPC860T processor. 

.SS "Boot ROMs"
The PowerPlus architecture boards have two sets of FLASH memory.  A set of
AMD Am29F040 FLASH ROMs is socketed and contains Motorola's EPPC1-Bug (tm)
and a set of soldered FLASH parts.  The VxWorks boot kernel resides in the
soldered FLASH.  Follow the instructions in the section, "ROM considerations",
below to load and write the boot kernel image to the soldered FLASH.

These boards have non-volatile RAM.  Thus, boot parameters are preserved
whenever the system is powered off.

To load VxWorks, and for more information, follow the instructions in the
"Getting Started"
chapter of the
.I "VxWorks Programmer's Guide."

.SS "Jumpers"
The following jumpers are relevant to VxWorks configuration:

.CS
                Motorola CPV3060

Jumper  Function        
-----------------------------------------------------
W1	On-board Battery

1-2	On-board battery connect (required for operation)
2-3	On-board battery disconnected

W2      Select Boot Device

1-2	ROM - Socket
2-3	ROM - Main Flash

Notes:
When W2 is set for 1-2 Socketed ROM base address   = 0xFE00_0000
                       Main Flash ROM base address = 0xFC00_0000

When W2 is set for 2-3 Main Flash ROM base address = 0xFE00_0000
                       Socketed ROM base address   = 0xFC00_0000

W3	Boot ROM

1-2	Enable writing to Boot ROM
2-3	Boot ROM write protect

.CE

.SH "FEATURES"
This section describes the supported and unsupported features of the CPV
boards.

.SS "Supported Features"
.PP
The supported features of the CPV board are:
    MPC860T processors
    Board Initialization
    MMU support
    Cache support
    Timer driver
    Serial driver
    Fast Ethernet END driver
    PCI Host Bridge (QSPAN)
    I2C Bus
    Optional serial port (SCC2)
    Optional Synchronous Burst RAM
    16MB, 32MB, 64MB or 128MB onboard memory
    50, 100 MHZ CPU speeds

.SS "Unsupported Features"
.PP
The unsupported features of the CPV board are:
    Hot Swap
    64-bit PMC cards
    Watchdog Timers
    TSA/TDM Channels
    SPI
    I2C write capability

.SH "HARDWARE DETAILS"
This section documents the details of the device drivers and hardware
elements for the CPV board.

.SS "Devices"
The chip drivers included are:

.nf
    qspanPci.c          - QSpan PCI to Motorola Bridge
    motFecEnd.c       - Motorola Fast Ethernet Controller END driver
    ppcDecTimer.c       - PowerPC Timer library
    ppc860Sio.c         - Serial Communications library for SMC1 port
    ppc860SioScc.c      - Serial Communications library for SCC2 port
    sysSerial.c         - Serial port configuration file
    ppc860Intr.c        - Interrupt Controller library
    i2cMcp.c            - I2C micro-chip patch
    cpvI2c.c            - I2C bus access
    byteNvRam.c         - NVRAM access routines
.fi

.SS "PCI Autoconfiguration"

The board support package for the CPV3060 handles automatic
detection and configuration of compact PCI devices.  In
particular, it performs the following:

.IP "1)"
Probes the host PCI bridge for all devices on the host
PCI bus (bus zero).  Note that among the devices on bus
zero might be PCI-PCI bridges.  These bridges are probed
as well and recursive probing occurs until all devices
and bridges are found. 

.IP "2)"
Memory is assigned to each device and sub-bridge found.
For devices, each Base Address Register (BAR) is queried.
Memory or I/O space (or both) is allocated for each BAR
which has been implemented.

.IP "3)"
Complete initialization of the devices is performed,
including cache Line size, command register, latency timer,
interrupt line and base address registers (0 through 5).
PCI-PCI bridges are initialized with the correct primary
bus, secondary bus and subordinate bus designation.  In
short, the entire bridge/device "tree" rooted at the host
pci bridge is completely configured and ready for driver
access.
.LP

.SS "PCI Autoconfiguration Roll Call"

A new feature to the PCI autoconfiguration is "roll call".  If you
expect to find a certain number of specific devices identified by
device/vendor ID during PCI autoconfiguration you can enter the
information into a roll call list.  For example assume that you
know that the autoconfiguration process should find 4 different
devices with device/vendor ID of 0x00461011 (this would be the
Dec2155x device).  You want PCI autoconfiguration to "wait" until
it finds at least this many but you don't want it to wait more
than 20 seconds.  If 20 seconds have elapsed and 4 different
Dec2155x chips have not appeared in the bus enumeration process,
you would like the PCI autoconfiguration process to proceed
anyway.

You would construct the "roll call" list in "config.h" as shown
below:

#define ROLL_CALL_MAX_DURATION 20

#define PCI_ROLL_CALL_LIST_ENTRIES \
{ 4, 0x00461011 },


The parameter ROLL_CALL_MAX_DURATION specifies that no more than 20
seconds should elapse before proceeding on with the
autoconfiguration, even though less than 4 Dec2155x devices have
been found.

You can see the entry { 4, 0x00461011 } which says that you expect
to find at least 4 devices whose device/vendor ID is 0x00461011.
Note that "cpv3060.h" contains defines for some device/vendor IDs,
such a define could be used here instead of a hard-coded
device/vendor ID.

Also note that this list can be extended so more than one device/
vendor ID is identified with possibly a different count.

If the list is empty (except for the termination entry) then there
is no roll call waiting performed, regardless of the setting of
ROLL_CALL_MAX_DURATION.

The roll call feature can be useful for devices which are slow to
appear on the cPCI bus.  For example, CPV3060 CPU boards (which
contain the Dec2155x nontransparent PCI bridge) will not be
visible to a cPCI master which is enumerating the bus until the
CPV3060 clears the "primary access lock-out" bit in the Dec2155x chip
control 0 register.  If the master's bus enumeration occurs
before the CPV3060 software unlocks the Dec2155x, then the master
will not know the CPV3060 is present and will not configure it.
The roll call feature allows for bus enumeration polling until the
specified devices actually appear.  Note that roll call may not
always be required for the example just presented.  Some system
configurations and timings may work without using the roll call
feature.

.SS "Dec2155x PCI-to-PCI Non-Transparent Bridge Support"
This BSP contains support for the Dec2155x non-transparent PCI-to-PCI
bridge. This device provides read/write access to and from the Compact
PCI bus (cPCI).

The following support is provided:
.IP
Up to 4 user configurable downstream cPCI to local PCI windows.
.IP
Up to 2 user configurable upstream local PCI to cPCI windows.
.IP
Support for in-bound "doorbell" interrupts.
.IP
Support for cPCI backpanel interrupts.
.IP
cPCI to local CPU address translation.
.IP
Local CPU to cPCI address translation.
.IP
Build-time validation of Dec2155x configuration parameters.
.LP

.SS "Dec2155x Support Limitations"
The PReP standard does not support 64-bit PCI addressing. Therefore, this
BSP does not provide support for 64-bit addressing through the Dec2155x.

There is a limitation when the cPCI to local PCI or cPCI to local CPU
address translation routines are presented with a cPCI address which maps
into a downstream window on the local board. The translation will succeed
and return an address, but when that address is accessed, the Dec2155x
will attempt to access one of its own downstream windows. The transfer
will fail because PCI devices cannot access themselves on the cPCI bus.
Depending on how error detection is configured, the result will be
invalid data or a PCI Master Abort.

Interrupt vectors are provided for the interrupts associated with
Dec2155x Hot Swap Power State transitions, Intelligent I/O (I2O), and the
Upstream Memory 2 Base Address Register but no other support for these
features is provided.

During system startup, the Dec2155x must be configured and unlocked
before the host enumerates the cPCI bus. To meet this timing requirement,
the Dec2155x is configured by the vxWorks boot ROM image. If changes to
the Dec2155x configuration are made, new boot ROMs are required in
addition to a new kernel. For proper operation, the Dec2155x
configuration in the Boot ROMs must match the configuration used by the
kernel.

The Dec2155x places certain limitations on window sizes and translation
values. This BSP adheres to those limitations and provides
build-time parameter checking to help avoid misconfigurations.
Modifications to the default Dec2155x configuration provided in this BSP
must be made with care to avoid invalid configurations. Information on
the default Dec2155x configuration provided by this BSP is presented in
the next section and modification guidelines appear later in this file.

.SS "Dec2155x Default Configuration"
The default Dec2155x configuration supports a host processor (MCP750) and
up to 7 CPV3060s. The following interoperability is supported:

.IP
Host access to CPV3060 CSR and the low 4MB of CPV3060 DRAM.
.IP
CPV3060 access to the low 4MB of host DRAM.
.IP
CPV3060 access to peer CPV3060 CSR and low 4MB of peer CPV3060 DRAM.
.LP

The BSP provides these features using the following Dec2155x
configuration:

.TS C
center;
lf3 s
r lw(3.2i) .
.ne 6
.sp .5
Primary CSR and Downstream Memory 0 BAR:
Size:	T{
4MB
T}
Direction:	T{
In-Bound (cPCI to CPV3060)
T}
cPCI Adrs:	T{
Dynamic (assigned by host)
T}
Local PCI Adrs:	T{
PCI2DRAM_BASE_ADRS (0x80000000 by convention)
T}
Local PCI Adrs:	T{
Dynamic (assigned by CPV3060)
T}
Local CPU Adrs:	T{
Dynamic (based on local PCI adrs)
T}
Use:	T{
R/W access to host DRAM
T}
.TE

.TS C
center;
lf3 s
r lw(3.2i) .
.ne 6
.sp .5
Upstream Memory 1 BAR:
Size:	T{
32MB
T}
Direction:	T{
Out-Bound (CPV3060 to cPCI)
T}
cPCI Adrs:	T{
Base cPCI address of the host's dynamic PCI configuration area (0x02000000 for
the default MCP750 BSP)
T}
Local PCI Adrs:	T{
Dynamic (assigned by CPV3060)
T}
Local CPU Adrs:	T{
Dynamic (based on local PCI adrs)
T}
Use:	T{
R/W access to cPCI devices
T}
.TE

The remaining Dec2155x Base Address Registers are not used by the BSP and
are available for use by the application.

.SS "Dec2155x Address Translation:
Due to the dynamic nature of PCI address allocation, the locations of the
upstream Dec2155x windows move as devices are added to the CPV3060 PCI
bus. Since these windows map the cPCI space into the local CPV3060 PCI
and CPU address spaces, their positions determine where the cPCI
resources appear when viewed by the CPV3060 CPU and any CPV3060 resident
PCI devices. Likewise, the downstream windows move as cPCI devices are
added and removed. The downstream windows are used to map the on-board
PCI and DRAM resources into the cPCI address space for access by the host
and other cPCI devices.

To assist with address translation, two translation routines are
provided by this BSP:

.TS C
center;
rw20 lw(3.2i) .
sysLocalToBusAdrs()	T{
Translates a local CPU address to an equivalent cPCI or local PCI memory or
I/O address.
T}

sysBusToLocalAdrs()	T{
Translates a cPCI or local PCI memory or I/O space address to a local CPU
equivalent address.
T}
.TE

\f3NOTE:\f1
The translations performed by sysLocalToBusAdrs() and
sysBusToLocalAdrs() are not symmetrical if one of the endpoints is the Compact
PCI bus. sysLocalToBusAdrs() translates by locating a downstream window which
makes the local CPU address visible in the cPCI address space.
sysBusToLocalAdrs() performs a similar operation by locating an upstream window
which makes the cPCI address visible in the local CPU address space. Since the
two sets of windows map different areas of the local address space,
the translation is not reversible.

.SS "Accessing Dec2155x CSR Registers"
Due to dynamic PCI address allocation, the PCI address assigned to the
Dec2155x CSR area cannot be known until runtime. To determine the
assigned address, it is necessary to read the Secondary CSR memory
BAR (or the Secondary CSR I/O BAR if I/O space is to be used).

The following code fragment derives the CPU address of the Scratchpad 0
register using its PCI memory space address:

.CS
    UINT32 bar;

    /* get the contents of the secondary CSR memory BAR
       (see note below) */

    if (pciConfigInLong (0, DEC2155X_PCI_DEV_NUMBER, 0,
                         DEC2155X_CFG_SEC_CSR_MEM_BAR,
                         &bar) != OK)
        {
        return (ERROR);
        }