cpc700.h

VxWorks下 Spruce的BSP源代码

#define INT_VEC_EXT_IRQ_11        31

#define INT_LVL_MEM_CTRL          0
#define INT_LVL_60X_PLB           1
#define INT_LVL_PCI_PLB           2
#define INT_LVL_UART0             3
#define INT_LVL_UART1             4
#define INT_LVL_IIC0              5
#define INT_LVL_IIC1              6
#define INT_LVL_GPT_COMP0         7
#define INT_LVL_GPT_COMP1         8
#define INT_LVL_GPT_COMP2         9
#define INT_LVL_GPT_COMP3         10
#define INT_LVL_GPT_COMP4         11
#define INT_LVL_GPT_CAPT0         12
#define INT_LVL_GPT_CAPT1         13
#define INT_LVL_GPT_CAPT2         14
#define INT_LVL_GPT_CAPT3         15
#define INT_LVL_GPT_CAPT4         16
#define INT_LVL_EXT_IRQ_0         20
#define INT_LVL_EXT_IRQ_1         21
#define INT_LVL_EXT_IRQ_2         22
#define INT_LVL_EXT_IRQ_3         23
#define INT_LVL_EXT_IRQ_4         24
#define INT_LVL_EXT_IRQ_5         25
#define INT_LVL_EXT_IRQ_6         26
#define INT_LVL_EXT_IRQ_7         27
#define INT_LVL_EXT_IRQ_8         28
#define INT_LVL_EXT_IRQ_9         29
#define INT_LVL_EXT_IRQ_10        30
#define INT_LVL_EXT_IRQ_11        31

/*
 * CPC700 Universal Interrupt Controller (UIC) register addresses
 */
#define UICSR           0xFF500880       /* status register        */
#define UICSRS          0xFF500884       /* status set register    */
#define UICER           0xFF500888       /* enable register        */
#define UICCR           0xFF50088C       /* critical register      */
#define UICPR           0xFF500890       /* polarity register      */
#define UICTR           0xFF500894       /* trigger register       */
#define UICMSR          0xFF500898       /* masked status register */
#define UICVR           0xFF50089C       /* vector register        */
#define UICVCR          0xFF5008A0       /* vector config register */

/*
 * CPC700 Processor Interface configuration registers.  The PIFCFGADR and
 * PIFCFGDATA indirect register pair are used to access the individual
 * registers.
 */
#define PIFCFGADR       0xFF500000
#define PIFCFGDATA      0xFF500004

#define PRIFOPT1        0x00
#define ERRDET1         0x04
#    define MEM_SEL_ER  0x40000000
#define ERREN1          0x08
#define CPUERAD         0x0C
#define CPUERAT         0x10
#define PLBMIFOPT       0x18
#define PLBMTLSA1       0x20
#define PLBMTLEA1       0x24
#define PLBMTLSA2       0x28
#define PLBMTLEA2       0x2C
#define PLBMTLSA3       0x30
#define PLBMTLEA3       0x34
#define PLBSNSSA0       0x38
#define PLBSNSEA0       0x3C
#define PLBSWRINT       0x80

/*
 * CPC700 Memory Controller configuration registers.  The MEMCFGADR and
 * MEMCFGDATA indirect register pair are used to access the individual
 * registers.
 */
#define MEMCFGADR       0xFF500008   /* Address register */
#define MEMCFGDATA      0xFF50000C   /* Data register */

#define MCOPT1          0x20         /* Misc. memory controller options       */
#define MBEN            0x24         /* memory bank enable                    */
#    define MBEN_BANK0  0x80000000   /* bits */
#    define MBEN_BANK1  0x40000000
#    define MBEN_BANK2  0x20000000
#    define MBEN_BANK3  0x10000000
#    define MBEN_BANK4  0x08000000
#define MEMTYPE         0x28         /* memory type (SDRAM, ROM, etc.)        */
#define RWD             0x2C         /* SDRAM bank active watchdog timer      */
#define RTR             0x30         /* SDRAM refresh timer reg               */
#define DAM             0x34         /* SDRAM address mode register           */
#define MB0SA           0x38         /* start addr for flash bank             */
#define MB1SA           0x3C         /* start addr for 1st SDRAM bank         */
#define MB2SA           0x40         /* start addr for 2nd SDRAM bank         */
#define MB3SA           0x44         /* start addr for Spruce peripherals     */
#define MB4SA           0x48
#define MB0EA           0x58         /* end addr minus 1MB for flash          */
#define MB1EA           0x5C         /* end addr minus 1MB for 1st SDRAM bank */
#define MB2EA           0x60         /* end addr minus 1MB for 2nd SDRAM bank */
#define MB3EA           0x64         /* end addr for Spruce peripherals       */
#define MB4EA           0x68
#define SDTR1           0x80         /* SDRAM timing register                 */
#define RBW             0x88         /* ROM/peripheral bank width             */
#define FWEN            0x90         /* ROM/peripheral write enable           */
#define ECCCF           0x94         /* ECC configuration register            */
#define ECCERR          0x98         /* ECC error status register             */
#define RPB0P           0xE0         /* ROM/peripheral bank timings bank 0    */
#define RPB1P           0xE4
#define RPB2P           0xE8
#define RPB3P           0xEC         /* ROM/perhiheral bank timings bank 3    */
#define RPB4P           0xF0

/*
 * CPC700 IIC0 and IIC1 base register addresses
 * Add an IIC register offset below to obtain the address of a given register.
 */
#define IIC0ADR         0xFF620000   /* IIC port 0 */
#define IIC1ADR         0xFF630000   /* IIC port 1 */

/*
 * IIC register offsets
 */
#define IICMDBUF        0x00
#define IICSDBUF        0x02
#define IICLMADR        0x04
#define IICHMADR        0x05
#define IICCNTL         0x06
#define IICMDCNTL       0x07
#define IICSTS          0x08
#define IICEXTSTS       0x09
#define IICLSADR        0x0A
#define IICHSADR        0x0B
#define IICCLKDIV       0x0C
#define IICINTRMSK      0x0D
#define IICXFRCNT       0x0E
#define IICXTCNTLSS     0x0F
#define IICDIRECTCNTL   0x10

/*
 * CPC700 UART0 and UART1 (16550 compatible) base register addresses
 */
#define UART_REG_ADDR_INTERVAL   1
#define UART0ADR        0xFF600300
#define UART1ADR        0xFF600400

/*
 * CPC700 Clock Management, Power Management, and Reset register address
 * and bit definitions
 */
#define  CPRRESET         0xFF500904             /* Peripheral reset register */
#define      UART0_RST    0x80000000             /* bits */
#define      UART1_RST    0x40000000
#define      IIC0_RST     0x20000000
#define      IIC1_RST     0x10000000
#define      GPT_RST      0x08000000
#define      GPT_TBC_RST  0x04000000             /* reset the CPC700 timebase */

#define  CPRSTRAPREAD     0xFF500914             /* CPC700 strapping pins     */
#define      PCIFREQ0     0x80000000             /* TSIZ[2] pin               */
#define      PCIFREQ1     0x40000000             /* PCI_66_EN pin             */
#define      MUXARBPAR    0x20000000             /* use internal PCI arbiter  */
#define      SYNCASYNC    0x08000000             /* PCI sync = 1, async = 0   */

/*
 * CPC700 Timer register addresses.  There are 5 capture timers and 5 compare
 * timers.  All timers operate at the frequency of the GPTTBC.
 */
#define  GPTTBC      0xFF650000        /* Timebase Counter register           */

#define  GPTCE       0xFF650004        /* Capture Timer Enable                */
#define  GPTEC       0xFF650008        /* Capture Timer Edge-Detection Cntrl  */
#define  GPTSC       0xFF65000C        /* Capture Timer Synchronization Cntrl */

/*
 * Timer Interrupt registers
 */
#define  GPTIM       0xFF650018        /* Timer Interrupt Mask                */
#define  GPTISS      0xFF65001C        /* Timer Interrupt Status Set          */
#define  GPTISC      0xFF650020        /* Timer Interrupt Status Clear        */
#define  GPTIE       0xFF650024        /* Timer Interrupt Enable              */

/* Bit definitions for Timer Interrupt registers */
#define  INT_GPT_CAPTURE_0   0x80000000
#define  INT_GPT_CAPTURE_1   0x40000000
#define  INT_GPT_CAPTURE_2   0x20000000
#define  INT_GPT_CAPTURE_3   0x10000000
#define  INT_GPT_CAPTURE_4   0x08000000

#define  INT_GPT_COMPARE_0   0x00008000
#define  INT_GPT_COMPARE_1   0x00004000
#define  INT_GPT_COMPARE_2   0x00003000
#define  INT_GPT_COMPARE_3   0x00001000
#define  INT_GPT_COMPARE_4   0x00000800

/* Addresses for the actual capture and compare timer registers */
#define  GPTCAPT0    0xFF650040        /* Capture Timer 0                     */
#define  GPTCAPT1    0xFF650044        /* Capture Timer 1                     */
#define  GPTCAPT2    0xFF650048        /* Capture Timer 2                     */
#define  GPTCAPT3    0xFF65004C        /* Capture Timer 3                     */
#define  GPTCAPT4    0xFF650050        /* Capture Timer 4                     */

#define  GPTCOMP0    0xFF650080        /* Compare Timer 0                     */
#define  GPTCOMP1    0xFF650084        /* Compare Timer 1                     */
#define  GPTCOMP2    0xFF650088        /* Compare Timer 2                     */
#define  GPTCOMP3    0xFF65008C        /* Compare Timer 3                     */
#define  GPTCOMP4    0xFF650090        /* Compare Timer 4                     */

#define  GPTMASK0    0xFF6500C0        /* Compare Timer Mask 0                */
#define  GPTMASK1    0xFF6500C4        /* Compare Timer Mask 1                */
#define  GPTMASK2    0xFF6500C8        /* Compare Timer Mask 2                */
#define  GPTMASK3    0xFF6500CC        /* Compare Timer Mask 3                */
#define  GPTMASK4    0xFF6500D0        /* Compare Timer Mask 4                */

#ifdef __cplusplus
    }
#endif

#endif  /* INCcpc700h */