cpc700.h

VxWorks下 Spruce的BSP源代码

/* cpc700.h - IBM CPC700 embedded chipset header */

/*******************************************************************************
   This source and object code has been made available to you by IBM on an
   AS-IS basis.

   IT IS PROVIDED WITHOUT WARRANTY OF ANY KIND, INCLUDING THE WARRANTIES OF
   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE OR OF
   NONINFRINGEMENT OF THIRD PARTY RIGHTS.  IN NO EVENT SHALL IBM OR ITS
   LICENSORS BE LIABLE FOR INCIDENTAL, CONSEQUENTIAL OR PUNITIVE DAMAGES.
   IBM'S OR ITS LICENSOR'S DAMAGES FOR ANY CAUSE OF ACTION, WHETHER IN
   CONTRACT OR IN TORT, AT LAW OR AT EQUITY, SHALL BE LIMITED TO A MAXIMUM
   OF $1,000 PER LICENSE.  Anyone receiving this source or object code is
   licensed under IBM copyrights to use it in any way he or she deems fit,
   including copying it, modifying it, compiling it, and redistributing it
   either with or without modifications.  No license under IBM patents or
   patent applications is to be implied by the copyright license.

   Any user of this software should understand that neither IBM nor its
   licensors will be responsible for any consequences resulting from the
   use of this software.

   Any person who transfers this object code or any derivative work must
   include the IBM copyright notice in the transferred software.

   COPYRIGHT   I B M   CORPORATION 1999
   LICENSED MATERIAL  -  PROGRAM PROPERTY OF  I B M"

*******************************************************************************/

/* Copyright 1984-1999 Wind River Systems, Inc. */

/*
modification history
--------------------
01d,21jun02,pch  revise for use with generic pciConfigLib
01c,12jun02,kab  SPR 74987: cplusplus protection
01b,27mar01,kab  Removed IBM support info per request
01a,10feb99,mcg  created
*/

#ifndef INCcpc700h
#define INCcpc700h

#ifdef __cplusplus
    extern "C" {
#endif

/*
This file contains I/O addresses and related constants for the
IBM CPC700 Chipset.  This chip contains a PowerPC 6xx/7xx interface,
SDRAM controller, PCI bus bridge, 2 UARTs, 2 I2C ports, a Universal
Interrupt Controller, and general purpose timers.
All parameters in this file are fixed.
*/


/* Local PCI address map */
#define PCI_MEMORY_START        0x80000000
#define PCI_MEMORY_END          0xF7FFFFFF
#define PCI_IO_REGION_1_START   0xF8000000
#define PCI_IO_REGION_1_END     0xF800FFFF
#define PCI_IO_REGION_2_START   0xF8800000
#define PCI_IO_REGION_2_END     0xFBFFFFFF

/*
 * Register pair used to generate configuration cycles on the PCI bus
 * and access the CPC700's own PCI configuration registers.
 */
#define PCICFGADR               0xFEC00000
#define PCICFGDATA              0xFEC00004

/*
 * Register addresses for the 3 sets of CPC700 PCI Master Mode (PMM)
 * local configuration registers.  These registers control how local memory
 * addresses are translated to PCI memory addresses when the CPC700 is a
 * PCI bus master (initiator).  The contents of the PMMxLA register must be
 * set to an address that is within the CPC700 PCI memory range
 * (PCI_MEMORY_START - PCI_MEMORY_END).
 */
#define PMM0LA          0xFF400000       /* Local Address                  */
#define PMM0MA          0xFF400004       /* Mask/Attribute register        */
#define PMM0PCILA       0xFF400008       /* Local address is translated to */
#define PMM0PCIHA       0xFF40000C       /* this 64 bit PCI address        */

#define PMM1LA          0xFF400010       /* Local Address                  */
#define PMM1MA          0xFF400014       /* Mask/Attribute register        */
#define PMM1PCILA       0xFF400018       /* Local address is translated to */
#define PMM1PCIHA       0xFF40001C       /* this 64 bit PCI address        */

#define PMM2LA          0xFF400020       /* Local Address                  */
#define PMM2MA          0xFF400024       /* Mask/Attribute register        */
#define PMM2PCILA       0xFF400028       /* Local address is translated to */
#define PMM2PCIHA       0xFF40002C       /* this 64 bit PCI address        */

/*
 * Bit definitions for PMM Mask Attribute registers
 */
#define PMM_MASK        0xFFFFF000
#define PMM_MASK_4KB    0xFFFFF000
#define PMM_MASK_8KB    0xFFFFE000
#define PMM_MASK_16KB   0xFFFFC000
#define PMM_MASK_32KB   0xFFFF8000
#define PMM_MASK_64KB   0xFFFF0000
#define PMM_MASK_128KB  0xFFFE0000
#define PMM_MASK_256KB  0xFFFC0000
#define PMM_MASK_512KB  0xFFF80000
#define PMM_MASK_1MB    0xFFF00000
#define PMM_MASK_2MB    0xFFE00000
#define PMM_MASK_4MB    0xFFC00000
#define PMM_MASK_8MB    0xFF800000
#define PMM_MASK_16MB   0xFF000000
#define PMM_MASK_32MB   0xFE000000
#define PMM_MASK_64MB   0xFC000000
#define PMM_MASK_128MB  0xF8000000
#define PMM_MASK_256MB  0xF0000000
#define PMM_MASK_512MB  0xE0000000
#define PMM_PREFETCH    0x00000002
#define PMM_ENABLE      0x00000001

#define PMM_UNUSED      0x00000000

/*
 * Register addresses for the 2 sets of CPC700 PCI Target Mode (PTM)
 * local configuration registers.  These registers control how PCI memory
 * addresses are translated to Local memory addresses when the CPC700 is a
 * PCI bus target.  PTMxLA must be set to an address that is within the
 * CPC700 Local Memory / Peripheral regions (0x00000000 - 7FFFFFFF, or
 * FF800000 - FFFFFFFF).
 */
#define PTM1MS          0xFF400030       /* Memory Size/Attribute register */
#define PTM1LA          0xFF400034       /* Local Address                  */

#define PTM2MS          0xFF400038       /* Memory Size/Attribute register */
#define PTM2LA          0xFF40003C       /* Local Address                  */

/*
 * Bit definitions for PTM Memory Size/Attribute registers
 */
#define PTM_SIZE        0xFFFFF000
#define PTM_SIZE_4KB    0xFFFFF000
#define PTM_SIZE_8KB    0xFFFFE000
#define PTM_SIZE_16KB   0xFFFFC000
#define PTM_SIZE_32KB   0xFFFF8000
#define PTM_SIZE_64KB   0xFFFF0000
#define PTM_SIZE_128KB  0xFFFE0000
#define PTM_SIZE_256KB  0xFFFC0000
#define PTM_SIZE_512KB  0xFFF80000
#define PTM_SIZE_1MB    0xFFF00000
#define PTM_SIZE_2MB    0xFFE00000
#define PTM_SIZE_4MB    0xFFC00000
#define PTM_SIZE_8MB    0xFF800000
#define PTM_SIZE_16MB   0xFF000000
#define PTM_SIZE_32MB   0xFE000000
#define PTM_SIZE_64MB   0xFC000000
#define PTM_SIZE_128MB  0xF8000000
#define PTM_SIZE_256MB  0xF0000000
#define PTM_SIZE_512MB  0xE0000000
#define PTM_SIZE_1GB    0xC0000000
#define PTM_SIZE_2GB    0x80000000
#define PTM_ENABLE      0x00000001

#define PTM_UNUSED      0x00000000

/*
 * Bus/Device/Function used to access the PCI configuration registers
 * that belong to the CPC700 itself (Bus = Device = Function = 0).
 */
#define CPC700_PCI_BUS	0
#define CPC700_PCI_DEV	0
#define CPC700_PCI_FUNC	0
#define CPC700_PCI_BUSDEVFUNC   0x00000000

/*
 * CPC700-specific PCI configuration register offsets.  These are found
 * immediately following the architected 64 byte PCI configuration header.
 */
#define PCI_CFG_BUS_NUM         0x40
#define PCI_CFG_SUB_BUS_NUM     0x41
#define PCI_CFG_DISC_COUNTER    0x42
#define PCI_CFG_ARBITER_CNTRL   0x44
#define PCI_CFG_ERROR_ENABLE    0x48
#define PCI_CFG_ERROR_STATUS    0x49
#define PCI_CFG_BRIDGE_OPT1     0x4a
#define PCI_CFG_BRIDGE_OPT2     0x60

/*
 * Static interrupt vectors/levels.  These also correspond to bit numbers in
 * many of the registers of the CPC700 Universal Interrupt Controller (UIC).
 */
#define INT_VEC_MEM_CTRL          0
#define INT_VEC_60X_PLB           1
#define INT_VEC_PCI_PLB           2
#define INT_VEC_UART0             3
#define INT_VEC_UART1             4
#define INT_VEC_IIC0              5
#define INT_VEC_IIC1              6
#define INT_VEC_GPT_COMP0         7
#define INT_VEC_GPT_COMP1         8
#define INT_VEC_GPT_COMP2         9
#define INT_VEC_GPT_COMP3         10
#define INT_VEC_GPT_COMP4         11
#define INT_VEC_GPT_CAPT0         12
#define INT_VEC_GPT_CAPT1         13
#define INT_VEC_GPT_CAPT2         14
#define INT_VEC_GPT_CAPT3         15
#define INT_VEC_GPT_CAPT4         16
#define INT_VEC_EXT_IRQ_0         20
#define INT_VEC_EXT_IRQ_1         21
#define INT_VEC_EXT_IRQ_2         22
#define INT_VEC_EXT_IRQ_3         23
#define INT_VEC_EXT_IRQ_4         24
#define INT_VEC_EXT_IRQ_5         25
#define INT_VEC_EXT_IRQ_6         26
#define INT_VEC_EXT_IRQ_7         27
#define INT_VEC_EXT_IRQ_8         28
#define INT_VEC_EXT_IRQ_9         29
#define INT_VEC_EXT_IRQ_10        30