rominit.s

VxWorks下 Spruce的BSP源代码

..meg2:
        addi    r7,0,0x01                    /* note 2**1=2                   */
        b       ..set_mb1ea
..meg4:
        addi    r7,0,0x02                    /* note 2**2=4                   */
        b       ..set_mb1ea
..meg8:
        addi    r7,0,0x03                    /* note 2**3=8                   */
        b       ..set_mb1ea
..meg16:
        addi    r7,0,0x04                    /* note 2**4=16                  */
        b       ..set_mb1ea
..meg32:
        addi    r7,0,0x05                    /* note 2**5=32                  */
        b       ..set_mb1ea
..meg64:
        addi    r7,0,0x06                    /* note 2**6=64                  */
        b       ..set_mb1ea
..meg128:
        addi    r7,0,0x07                    /* note 2**7=128                 */
        b       ..set_mb1ea

..set_mb1ea:
        addis   r8,0,0x000F                  /* set up r8 to calc end addr    */
        ori     r8,r8,0xFFFF
	rlwnm   r8,r8,r7,0,11         /* shift by bank size factor to get     */
                                      /* end address MB1EA(0:11) bit settings */
        addi    r3,0,MB1EA
        stw     r3,0x0000(r10)               /* write index word to Cfg Addr  */
        sync
        stw     r8,0x0000(r2)                /* write word to Config Data     */
        sync
        cmpi    0,0,r5,0x1                /* check # banks in r5 - if 1, done */
        beq     ..mbaddr_done             /* else set MB2SA and MB2EA regs    */
        addi    r3,0,MB2SA
        stw     r3,0x0000(r10)            /* write index word to Cfg Addr     */
        sync
        addis   r9,0,0x0010                  /* set up to add 1 to 0:11 field */
        add     r9,r9,r8                     /* add 1 to MS1EA to get MS2SA   */
        stw     r9,0x0000(r2)                /* write word to Config Data     */
        sync

        add     r9,r9,r8                  /* add MS1EA and MS2SA to get MS2EA */
        addi    r3,0,MB2EA
        stw     r3,0x0000(r10)            /* write index word to Config Addr  */
        sync
        stw     r9,0x0000(r2)             /* write word to Config Data        */
        sync
..mbaddr_done:

        /*
         * Set SDRAM Timing reg, SDTR1. NOTE: If using Autoprecharge
         * (SD_APGE=1), set SD_RTP and SD_WTP appropriately. On Spruce
         * SD_RTP and SD_WTP should be 3 when SD_APGE=1.
         *   Spruce: w/o Autoprecharge: SDTR1 = 0x0004880A
         *   Spruce: w/  Autoprecharge: SDTR1 = 0x0044CC0A
         */
        addi    r3,0,SDTR1
        stw     r3,0x0000(r10)               /* write index word to Cfg Addr  */
        sync
        addis   r3,0,0x0004             /* set SD_APGE=0, SD_PTA=1, SD_WTP=2, */
        ori     r3,r3,0x880A            /* SD_RTP=2, SD_RFTA=2, SD_RCD=2      */
        stw     r3,0x0000(r2)           /* write word to Config Data          */
        sync

        /*
         * Set ECCCF reg. Check r6 value (bank width) to determine
         * if ECC is possible with the SDRAM being used.
         * This code supports 64 bit (non-ECC) and 72 bit (ECC) widths only.
         * NOTE: If ECC SDRAM is being used, ECC correction should be enabled
         * only after the portion of the ECC SDRAM memory to be used has been
         * initialized with ECC enabled both globally (ECC_EN bit) and enabled
         * for the ECC SDRAM bank to be used. That portion of memory must
         * be initialized with ECC enabled but with correction off to ensure
         * the correct ECC checkbits get stored properly. Since ECC does
         * read-modify-writes, if correction was enabled before initializing
         * memory with ECC enabled, the checkbits returned on the read
         * would be garbage and would trigger an ECC error.
         */
        cmpi    0,0,r6,0x40              /* Check bank width, if 0x40 then    */
        beq     ..no_ecc                 /* 64 bit and no ECC, else assume    */
        addis   r4,0,HIADJ(CPRSTRAPREAD) /* 72 bit and continue check for ECC */
        ori     r4,r4,LO(CPRSTRAPREAD)   /* Check strapping pin reg DQMNECC   */
        lwz     r4,0(r4)                 /* bit for ECC                       */
        sync
	rlwinm.	r4,r4,0,5,5
        bne     ..no_ecc                    /* if not = 0 then no ECC         */
        addis   r4,0,HIADJ(FPGA_REG_B)      /* set ECC_MODE_CTL in FPGA_REG_B */
        ori     r4,r4,LO(FPGA_REG_B)
        addi    r3,0,ECC_MODE_CTL           /* set ECC_MODE_CTL to enable ECC */
        stb     r3,0x0000(r4)
        sync
        cmpi    0,0,r5,0x1                /* check # banks in r5              */
        beq     ..ecc_bank1               /* if 1 bank, enable ecc for bank 1 */
        addis   r4,0,0x4060               /* else enable for banks 1 and 2    */
        ori     r4,r4,0x0000              /* set ECC_EN, and enable ecc but   */
                                          /* NOT correction for banks 1 and 2 */
        b       ..set_ecccf               /* SD_WDTH=0(64 bit data width)     */
..ecc_bank1:
        addis   r4,0,0x4040               /* set ECC_EN, and enable ecc but   */
        ori     r4,r4,0x0000              /* NOT correction for bank 1 only   */
        b       ..set_ecccf               /* SD_WDTH=0(64 bit data width)     */
..no_ecc:
        addis   r4,0,0x0000          /* No ECC & SD_WDTH=0(64 bit data width) */
..set_ecccf:
        addi    r3,0,ECCCF
        stw     r3,0x0000(r10)               /* write index word to Cfg Addr  */
        sync
        stw     r4,0x0000(r2)                /* write word to Config Data     */
        sync

        /*
         * Delay to insure 200usec have elapsed since reset.
         */
        addis   r3,r0,0x0001              /* Ensure 200usec have passed since */
        ori     r3,r3,0x5000              /* reset (appx 0x15000 cycles at    */
        mtctr   r3                        /* 400MHz (fastest case)            */
..spinlp:
        bdnz    ..spinlp                  /* spin loop                        */

        /*
         * Set memory controller options reg, MCOPT1.
         */
        addi    r3,0,MCOPT1
        stw     r3,0x0000(r10)          /* write index word to Cfg Addr       */
        sync
        addis   r3,0,0x8500             /* set DC_EN=1, DRAMTYP=2, BOOTROMP=1 */
        stw     r3,0x0000(r2)           /* write word to Config Data          */
        sync

        /*
         * At this point, r4 is non-zero if ECC SDRAM was configured and
         * zero if regular SDRAM was configured.  Also, r11 contains
         * the startType (BOOT_NORMAL, BOOT_CLEAR, etc.).  If startType
         * is BOOT_CLEAR and ECC SDRAM is configured, the ECC SDRAM
         * initialization code below must be run, else branch around it.
         */
        cmplwi   r11,BOOT_CLEAR
        bne      ..sdram_done
        cmplwi   r4,0x0000
        beq      ..sdram_done

        /*
         * Initialize ECC SDRAM for the entire address range by writing
         * it with zeros. This is necessary since memory must be initialized
         * with ECC enabled to ensure the checkbits get initialized correctly.
         * This must occur BEFORE enabling ECC correction. Otherwise, since
         * ECC performs read-modify writes, the checkbits returned on the
         * read would be garbage and an ECC error flagged. ECC correction
         * should only be enabled after initializing the ECC memory space
         * with ECC enabled.
         */
        addi    r4,0,0x1                /* use to calc memory size            */
        rlwnm   r7,r4,r7,0,31           /* use r7 to get bank end addr        */
                                        /* 2**(value in r7)=# of Meg in bank  */
        rlwinm  r4,r7,20,0,31           /* mult by a Meg (2**20=1Meg) to      */
                                        /* calc end addr and place in r4      */
        cmpi    0,0,r5,0x1              /* check # banks in r5                */
        beq     ..bank1                 /* if 1 bank, ok                      */
        rlwinm  r4,r4,1,0,31            /* else double memory size in r4      */
..bank1:
        addis   r3,r0,0xFFFF            /* set r3 to start address (used      */
        ori     r3,r3,0xFFF8            /* to start at addr 0x00000000)       */
        addis   r6,r0,0xFFFF            /* set r6 to start address (used      */
        ori     r6,r6,0xFFFC            /* to start at addr 0x00000004)       */
        addis   r5,r0,0x0000            /* set r5 to test value               */
                                        /* r4 contains the end address        */
        rlwinm  r4,r4,29,0,31     /* r4 contains the end address        */
                                        /* divide by 8 to get loop count      */
        mtctr   r4
..loopz:
        stwu    r5,0x8(r3)              /* store test value                   */
        stwu    r5,0x8(r6)              /* store test value                   */
        bdnz    ..loopz

        /*
         * With memory now initialized, if ECC is enabled, enable ECC
         * correction.
         */
        addi    r3,0,ECCCF
        stw     r3,0x0000(r10)          /* write index word to Config Addr    */
        sync
        lwz     r4,0x0000(r2)           /* read Config Data to get ECCCF value*/
        sync
        rlwinm. r3,r4,0,1,1             /* Check ECC global enable bit (bit 1)*/
	
        beq     ..ecc_disabled
        rlwinm  r3,r4,24,16,20          /* Check which banks enabled for ECC  */

					/* (bits 8:12) and rotate 24 bits to  */
                                        /* set ECC bank correction enable bits*/
                                        /* (bits 16:20)                       */
        or      r4,r3,r4
        stw     r4,0x0000(r2)           /* write ECCCF reg w/ correction      */
        sync				/* enabled                            */

..ecc_disabled:
..sdram_done:
        mtlr    r31                     /* restore lr                         */
        blr
FUNC_END(sdram_init)

/******************************************************************************
*
* iic0_read - Reads one byte from the SDRAM EEPROM via the IIC0 bus.
*             Note that the SDRAM EEPROM is the only device attached
*             to the IIC0 bus on Spruce. The SDRAM EEPROM IIC read
*             device address is 0xA1 for read and 0xA0 for write.
*             You must do a one byte write to the device addr with the
*             device subaddress to be read before doing a read.
*
* char iic0_read
*     (
*       char
*     )
*/
        /*
         * iic_read routine - does 1 byte read from SDRAM EEPROM on IIC0 bus.
         * iic combined format read requires a write of the byte we want to
         * read, before doing the read.
         */
FUNC_BEGIN(iic0_read)
        addis   r10,0,HIADJ(IIC0ADR)             /* r10 <- addr of IIC0 cntrl */
        ori     r10,r10,LO(IIC0ADR)

        addi    r15,0,0x08                       /* clear status              */
        stb     r15,IICSTS(r10)
        sync

        addis   r12,r0,0x0001                    /* set up timeout counter    */
        mtctr   r12
..chk_sts1:
        lbz     r15,IICSTS(r10)                  /* read status               */
        sync
        andi.   r15,r15,0x01                     /* check for pending trnsfer */
        beq     ..sts_ok1                        /* if 0, OK                  */
        bdnz    ..chk_sts1
        /*
         * If we get here, we timed out on clear status
         */
..iic0_timeout_fail_spin:
        b       ..iic0_timeout_fail_spin     /* halt - cannot clear status    */
..sts_ok1:
        lbz     r15,IICMDCNTL(r10)           /* read mode control             */
        sync
        ori     r15,r15,0x40                 /* flush master data buffer      */
        stb     r15,IICMDCNTL(r10)
        sync
        addi    r15,0,0xA0                   /* set device address for        */
        stb     r15,IICLMADR(r10)            /* SDRAM EEPROM write (0xA0)     */
        sync
        stb     r3,IICMDBUF(r10)             /* set device sub address        */
                                             /* which is the byte # to read   */
        addi    r15,0,0x01                   /* start write of 1 byte         */
        stb     r15,IICCNTL(r10)
        sync

        addis   r12,r0,0x0001                /* set up counter for timeout    */
        mtctr   r12
..chk_sts2:
        lbz     r15,IICSTS(r10)              /* read status                   */
        sync
        andi.   r15,r15,0x01                 /* check for pending transfer    */
        beq     ..write_ok                   /* if 0, OK                      */
        bdnz    ..chk_sts2
        /*
         * If we get here, we timed out on writing the SDRAM EEPROM
         * Could be No DIMM. Halt since memory can not be configured
         * properly without the EEPROM data.
         */
..iic0_read_fail_spin:
        b       ..iic0_read_fail_spin        /* halt - read failed            */
..write_ok:
        addi    r15,0,0x08                   /* clear status                  */
        stb     r15,IICSTS(r10)
        sync

        addis   r12,r0,0x0001                /* set up counter for timeout    */
        mtctr   r12
..chk_sts3:
        lbz     r15,IICSTS(r10)              /* read status                   */
        sync
        andi.   r15,r15,0x01                 /* check for pending transfer    */
        beq     ..sts_ok2                    /* if 0, OK                      */
        bdnz    ..chk_sts3
        /*
         * If we get here, we timed out on clear status
         */
        b       ..iic0_timeout_fail_spin       /* halt - can not clear status */
..sts_ok2:
        lbz     r15,IICMDCNTL(r10)             /* read mode control           */
        sync
        ori     r15,r15,0x40                   /* flush master data buffer    */
        stb     r15,IICMDCNTL(r10)
        sync
        addi    r15,0,0xA1                     /* set device address for      */
        stb     r15,IICLMADR(r10)              /* SDRAM EEPROM (0xA1)         */
        sync
        addi    r15,0,0x03                     /* read of 1 byte              */
        stb     r15,IICCNTL(r10)
        sync

        addis   r12,r0,0x0001                  /* set up counter for timeout  */
        mtctr   r12
..chk_sts4:
        lbz     r15,IICSTS(r10)                /* read status                 */
        sync
        andi.   r15,r15,0x01                   /* check for pending transfer  */
        beq     ..read_ok                      /* if 0, OK                    */
        bdnz    ..chk_sts4
        /*
         * If we get here, we timed out on reading the SDRAM EEPROM
         * Could be No DIMM. Halt since memory can not be configured
         * properly without the EEPROM data.
         */
        b       ..iic0_read_fail_spin        /* halt - read failed            */
..read_ok:
        lbz     r3,IICMDBUF(r10)            /* read byte returned from EEPROM */
        sync

        blr                                  /* return with data in R3        */
FUNC_END(iic0_read)