📄 rominit.s
字号:
*/ addi r3,0,RBW stw r3,0x0000(r4) /* write index word to Cfg Addr */ sync lwz r3,0x0(r5) /* read then modify */ sync rlwinm r3,r3,0,8,5 /* set 64N8_3='00' */ stw r3,0x0000(r5) /* write word to Config Data */ sync /* * Enable writes to Memory Bank 3 since these devices are writable. */ addi r3,0,FWEN stw r3,0x0000(r4) /* write index word to Cfg Addr */ sync lwz r3,0x0(r5) /* read then modify */ sync addis r6,0,0x1000 /* set FLSHWEN_3 bit */ or r3,r3,r6 stw r3,0x0000(r5) /* write word to Config Data */ sync /* * Set Memory Bank 3 access mode and timings */ addi r3,0,RPB3P stw r3,0x0000(r4) /* write index word to Cfg Addr */ sync addis r3,0,0x2D03 /* set TWT=0xB, CSON=1, THDRD=6, */ ori r3,r3,0x10F0 /* THDWR=2, FWT=0xF */ stw r3,0x0000(r5) /* write word to Config Data */ sync blrFUNC_END(periph_init)/******************************************************************************** iic0_init - Initializes IIC0 for use of IIC bus during SDRAM configuration.** iic_0init* (** )*/FUNC_BEGIN(iic0_init) addis r3,0,HIADJ(IIC0ADR) /* r3 <- addr of IIC0 controller */ ori r3,r3,LO(IIC0ADR) addi r4,0,0x00 stb r4,IICLMADR(r3) /* clear lo master address */ sync stb r4,IICHMADR(r3) /* clear hi master address */ sync stb r4,IICLSADR(r3) /* clear lo slave address */ sync stb r4,IICHSADR(r3) /* clear hi slave address */ sync addi r4,0,0x08 stb r4,IICSTS(r3) /* clear status */ sync addi r4,0,0x8F stb r4,IICEXTSTS(r3) /* clear extended status */ sync addi r4,0,0x03 /* set clock divisor */ stb r4,IICCLKDIV(r3) /* CPC700 30/33.3Mhz => 3 */ sync /* CPC700 41.25/50Mhz => 4 */ addi r4,0,0x00 stb r4,IICINTRMSK(r3) /* no interrupts */ sync stb r4,IICXFRCNT(r3) /* clear transfer count */ sync addi r4,0,0xF0 stb r4,IICXTCNTLSS(r3) /* clear extended control & stat */ sync addi r4,0,0x43 /* set mode control - flush */ stb r4,IICMDCNTL(r3) /* master data buf, enable hold */ sync /* SCL, exit unknown state */ addi r4,0,0x00 stb r4,IICCNTL(r3) /* clear control reg */ sync blrFUNC_END(iic0_init)/******************************************************************************** sdram_init - Checks SDRAM EEPROM via IIC bus and then configures memory* controller.* sdram_init* (** )*/FUNC_BEGIN(sdram_init) mflr r31 /* save lr in r31 */ /* * One SDRAM DIMM socket exists on the Spruce board. An EEPROM * on the SDRAM DIMM provides information about the DIMM which * helps to configure the SDRAM controller. The information is read * from the EEPROM using the IIC1 port using with iic_read subroutine. * Data will be stored in GPRs 4, 5, 6, and 7. */ addi r4,0,0x00 addi r5,0,0x00 addi r3,0,SDRAM_NUM_ROWS /* set byte to read (# ROWS) */ bl iic0_read ori r4,r3,0x00 /* store value in R4 */ addi r3,0,SDRAM_NUM_COLS /* set byte to read (# COLS) */ bl iic0_read rlwinm r4,r4,8,0,31 /* make room for byte */ or r4,r3,r4 /* store value in R4 */ addi r3,0,SDRAM_NUM_INTBANKS /* set byte to read (# INT BANKS)*/ bl iic0_read rlwinm r4,r4,8,0,31 /* make room for byte */ or r4,r3,r4 /* store value in R4 */ addi r3,0,5 /* set byte to read (# BANKS) */ bl iic0_read ori r5,r3,0x00 /* store value in R5 */ addi r3,0,SDRAM_WIDTH /* set byte to read (DATA WIDTH) */ bl iic0_read ori r6,r3,0x00 /* store value in R6 */ addi r3,0,SDRAM_MOD_DENSITY /* set byte to read (MEM SIZE) */ bl iic0_read ori r7,r3,0x00 /* store value in R7 */ /* * Now we have all the data needed from the SDRAM EEPROM. * r4 has the # rows, # cols, and # internal banks in 3 LSBytes. * r5 has # of banks * r6 has data width * r7 has the bank size * No more iic reads are needed. Now the memory controller needs to * be set up properly based on this SDRAM data. */ addis r3,0,HIADJ(MEMCFGADR) ori r10,r3,LO(MEMCFGADR) ori r2,r3,LO(MEMCFGDATA) /* * Enable banks. Bank 1 if single sided DIMM, banks 1 and 2 if * double-sided DIMM. Use # banks value stored in r5 to determine. */ addi r3,0,MBEN stw r3,0x0000(r10) /* write index word to Cfg Addr */ sync lwz r3,0x0(r2) /* read then modify */ sync cmpi 0,0,r5,0x2 /* check # banks in r5 */ beq ..two_banks addis r8,0,0x4000 /* set MBE_1 to enable bank 1 */ b ..set_mben..two_banks: addis r8,0,0x6000 /* set MBE_1, MBE_2 to enable banks 1,2 */..set_mben: or r3,r3,r8 stw r3,0x0000(r2) /* write word to Config Data */ sync /* * Set memory type. Must be DRAM for banks 1 and 2 on Spruce. OK to * set for bank 2 even if no memory is there. */ addi r3,0,MEMTYPE stw r3,0x0000(r10) /* write index word to Cfg Addr */ sync lwz r3,0x0(r2) /* read then modify */ sync rlwinm r3,r3,0,6,1 /* set MT_1='01', MT_2='01' for DRAM */ oris r3,r3,0x1400 stw r3,0x0000(r2) /* write word to Config Data */ sync /* * Check speed to set RTR (refresh timer) reg properly. */ addis r8,r0,HIADJ(FPGA_REG_A) /* set offset for FPGA_REG_A */ ori r8,r8,LO(FPGA_REG_A) lbz r8,0x0(r8) /* read to get CPC700 clk */ sync /* CPC700 clk = 60x bus speed/2 */ andi. r3,r8,UART_CLK_EXT /* check UART_CLK_EXT bit */ beq ..chk_clk /* if not set,check if 60 or 66.6Mhz */ addis r8,r0,0x04DD /* else assume ext clk of 83.33Mhz */ b ..okay..chk_clk: andi. r3,r8,UART_CLK_33 /* check UART_CLK_33 bit */ beq ..clock_60 /* if not set,assume 60Mhz else 66.6Mz */ addis r8,r0,0x03F8 /* set refresh for 66.66Mhz */ b ..okay..clock_60: addis r8,r0,0x0392 /* set refresh for 60.00Mhz */..okay: addi r3,0,RTR stw r3,0x0000(r10) /* write index word to Cfg Addr */ sync stw r8,0x0000(r2) /* write word to Config Data */ sync /* * Check r4 values to determine mode. Mode is determined by the * num rows, num cols, and num of internal banks. All three of these * parameters are stored in r4. Mode should be set as follows: * rows x cols (internal banks) * mode 1 - 11x9(2), 11X10(2) * mode 2 - 12x9(4), 13x9(2), 12x10(4), 13x10(2) * mode 3 - 13x9(4), 13x10(4), 13x11(4) * mode 4 - 12x8(4), 13x8(2), 12x8(2) */ addis r14,0,0x0B ori r14,r14,0x0902 cmp 0,0,r4,r14 /* 11x9(2) */ beq ..mode1 addis r14,0,0x0B ori r14,r14,0x0A02 cmp 0,0,r4,r14 /* 11x10(2) */ beq ..mode1 addis r14,0,0x0C ori r14,r14,0x0904 cmp 0,0,r4,r14 /* 12x9(4) */ beq ..mode2 addis r14,0,0x0D ori r14,r14,0x0902 cmp 0,0,r4,r14 /* 13x9(2) */ beq ..mode2 addis r14,0,0x0C ori r14,r14,0x0A04 cmp 0,0,r4,r14 /* 12x10(4) */ beq ..mode2 addis r14,0,0x0D ori r14,r14,0x0A02 cmp 0,0,r4,r14 /* 13x10(2) */ beq ..mode2 addis r14,0,0x0D ori r14,r14,0x0904 cmp 0,0,r4,r14 /* 13x9(4) */ beq ..mode3 addis r14,0,0x0D ori r14,r14,0x0A04 cmp 0,0,r4,r14 /* 13x10(4) */ beq ..mode3 addis r14,0,0x0D ori r14,r14,0x0B04 cmp 0,0,r4,r14 /* 13x11(4) */ beq ..mode3 addis r14,0,0x0C ori r14,r14,0x0804 cmp 0,0,r4,r14 /* 12x8(4) */ beq ..mode4 addis r14,0,0x0D ori r14,r14,0x0802 cmp 0,0,r4,r14 /* 13x8(2) */ beq ..mode4 addis r14,0,0x0C ori r14,r14,0x0802 cmp 0,0,r4,r14 /* 12x8(2) */ beq ..mode4 /* * If we get here, then mode bytes read are invalid * Just hang here. */..invalid_dimm_mode_spin: b ..invalid_dimm_mode_spin /* halt - invalid dimm mode */..mode4: addi r4,0,0x3 b ..set_mode..mode3: addi r4,0,0x2 b ..set_mode..mode2: addi r4,0,0x1 b ..set_mode..mode1: addi r4,0,0x0..set_mode: addi r3,0,DAM stw r3,0x0000(r10) /* write index word to Cfg Addr */ sync lwz r3,0x0(r2) /* read then modify */ sync rlwinm r3,r3,0,4,1 /* zero out DAM_1 bits */ rlwinm r8,r4,28,0,31 /* set DAM_1 bits to mode in r4 */ or r3,r8,r3 cmpi 0,0,r5,0x1 /* check # banks in r5 - if 1, done */ beq ..set_dam /* else set DAM_2 bits */ rlwinm r3,r3,0,6,3 /* zero out DAM_2 bits */ rlwinm r8,r4,26,0,31 /* set DAM_2 bits to mode in r4 */ or r3,r8,r3..set_dam: stw r3,0x0000(r2) /* write word to Cfg Data */ sync /* * Set memory bank start and ending addresses. To do this need to * know number of banks (r5) and bank size (r7). Starts memory * at address 0x00000000 and continues contiguously. */ addi r3,0,MB1SA stw r3,0x0000(r10) /* write index word to Cfg Addr */ sync addis r3,0,0x0000 /* set MB1SA='000' */ stw r3,0x0000(r2) /* write word to Config Data */ sync cmpi 0,0,r7,0x00 /* check r7 for bank size */ beq ..meg2 /* and use value to calc bank end addr */ cmpi 0,0,r7,0x01 beq ..meg4 cmpi 0,0,r7,0x02 beq ..meg8 cmpi 0,0,r7,0x04 beq ..meg16 cmpi 0,0,r7,0x08 beq ..meg32 cmpi 0,0,r7,0x10 beq ..meg64 cmpi 0,0,r7,0x20 beq ..meg128 cmpi 0,0,r7,0x40 addi r7,0,0x08 /* must be 256M bank; note 2**8=256 */ b ..set_mb1ea⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -