📄 rominit.s
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bne invalid_caches /* 603 not in 1:1 or 3:2 mode */set_prifopt1: /* * The CPU is running in 1:1 or 3:2 (CPU:bus freq) mode, so * set bit 0 of the CPC700 PRIFOPT1 reg. When this bit is set, * the CPC700 samples the processor address retry (ARTRY) signal * one cycle later than when the processor is not running in 1:1 * or 3:2 mode. This is necessary for data cache snooping to * work correctly at these specific 603 CPU:bus frequency ratios. */ addis r5,0,HIADJ(PIFCFGADR) ori r6,r5,LO(PIFCFGADR) /* r6 <- Processor Interface Cfg Addr */ ori r7,r5,LO(PIFCFGDATA) /* r7 <- Processor Interface Cfg Data */ addi r3,0,PRIFOPT1 /* index word to CPC700 PRIFOPT1 reg */ stw r3,0x0000(r6) /* write index word to Config Addr */ sync lwz r3,0x0(r7) /* read then modify */ sync addis r4,0,0x8000 /* set 603_1_1 bit (bit 0) of PRIFOPT1*/ or r3,r3,r4 stw r3,0x0000(r7) /* write word to Config Data */ sync b invalid_cachescpuIs7xx: /* * For 740/750, set the BTIC and BHT bits in HID) to enable both * the branch history table and branch target instruction cache. */ mfspr r4,HID0 ori r4,r4,0x0024 mtspr HID0,r4 /* * Disable the L2 cache for the 750. This won't hurt the 740. */ mfspr r3, L2CR rlwinm r3, r3, 0, 1, 31 /* turn off the L2 enable bit */ mtspr L2CR, r3invalid_caches: /* * Invalidate the processor data/instruction L1 caches. * For 603/740/750, they do not have to be enabled to invalidate. */ mfspr r4, HID0 ori r3, r4, (_PPC_HID0_ICFI | _PPC_HID0_DCFI) sync isync mtspr HID0, r3 /* Flash invalidate both caches */ isync ori r4, r4, (_PPC_HID0_ICE) isync mtspr HID0, r4 /* enable Icache */ isync /* * Call various routines to set up the memory controller to access * Spruce memory and peripherals */ bl flash_init /* speed up accesses to boot flash */ bl periph_init /* need to access FPGA_REG_A later */ /* for SDRAM initialization */ bl iic0_init /* init iic0 device so we can read */ /* SDRAM DIMM presence detect info */ /* * Configure the SDRAM controller only if this is a cold boot. * If the SDRAM controller is reinitialized on a warm boot, the * boot line will get wiped out because of the ECC SDRAM memory * initialization. */ li r3, BOOT_COLD and. r3, r3, r11 /* r11 contains passed boot parameters */ beq skip bl sdram_init /* configure the SDRAM controller */skip: /* * Set up the CPC700 so that if any address is accessed outside * of what is defined in the memory controller, it activates the * the MCP (machine check) signal to the processor. */ addis r5,0,HIADJ(PIFCFGADR) ori r6,r5,LO(PIFCFGADR) /* r6 <- Processor Interface Cfg Addr */ ori r7,r5,LO(PIFCFGDATA) /* r7 <- Processor Interface Cfg Data */ addi r3,0,ERRDET1 /* index word to CPC700 ERRDET1 reg */ stw r3,0x0000(r6) sync addis r3,0,0xFFFF ori r3,r3,0xFFFF stw r3,0x0000(r7) /* Clear all bits in the ERRDET1 reg */ sync addi r3,0,ERREN1 /* index word to CPC700 ERREN1 reg */ stw r3,0x0000(r6) sync lwz r3,0x0000(r7) sync oris r3,r3,0x4800 /* Set the Memory Select Error Enable */ stw r3,0x0000(r7) /* and the PLB slave error generation */ sync /* enable bits in the ERREN1 reg. */ addi r3,0,PRIFOPT1 /* index word to CPC700 PRIFOPT1 reg */ stw r3,0x0000(r6) sync lwz r3,0x0000(r7) /* read/modify/write */ sync oris r3,r3,0x4000 /* set MCP_enable to enable the */ stw r3,0x0000(r7) /* machine check output pin on CPC700 */ sync /* * Enable the machine check input pin on the processor using the ECMP * bit in HID0. Machine Check exceptions will be enabled later, after * the vectors are set up. */ mfspr r4, HID0 addis r5,0,HIADJ(_PPC_HID0_EMCP) or r4,r4,r5 mtspr HID0,r4 /* enable the machine check pin */#if FALSE /* EABI SDA not supported yet */ /* initialize r2 and r13 according to EABI standard */ lis r2, HIADJ(_SDA2_BASE_) ori r2, r2, LO(_SDA2_BASE_) lis r13, HIADJ(_SDA_BASE_) ori r13, r13, LO(_SDA_BASE_)#endif /* go to C entry point */ or r3, r11, r11 addi r1, r1, -FRAMEBASESZ /* get frame stack */ lis r6, HIADJ(romStart) ori r6, r6, LO(romStart) lis r7, HIADJ(romInit) ori r7, r7, LO(romInit) lis r8, HIADJ(ROM_TEXT_ADRS) ori r8, r8, LO(ROM_TEXT_ADRS) sub r6, r6, r7 add r6, r6, r8 mtlr r6 blrFUNC_END(romInit)/******************************************************************************** flash_init - Changes CPC700 memory controller bank 0 settings for flash so* accesses are faster than power-up default settings.** flash_init* (** )*/FUNC_BEGIN(flash_init) addis r3,0,HIADJ(MEMCFGADR) ori r4,r3,LO(MEMCFGADR) /* r4 <- Memory Config Addr */ ori r5,r3,LO(MEMCFGDATA) /* r5 <- Memory Config Data */ /* * Enable Memory Bank 0 */ addi r3,0,MBEN stw r3,0x0000(r4) /* write index word to Config Addr */ sync lwz r3,0x0(r5) /* read then modify */ sync addis r6,0,0x8000 /* set MBE_0 to enable bank 0 */ or r3,r3,r6 stw r3,0x0000(r5) /* write word to Config Data */ sync /* * Set Memory Bank 0 to ROM memory type */ addi r3,0,MEMTYPE stw r3,0x0000(r4) /* write index word to ConfigAddr */ sync lwz r3,0x0(r5) /* read then modify */ sync rlwinm r3,r3,0,2,31 /* set MT_0='00' for ROM */ stw r3,0x0000(r5) /* write word to Config Data */ sync /* * Set Memory Bank 0 starting address to 0xFFE00000 (2MB from the top) */ addi r3,0,MB0SA stw r3,0x0000(r4) /* write index word to Config Addr */ sync addis r3,0,0xFFE0 /* set MB0SA='FFE' */ stw r3,0x0000(r5) /* write word to Config Data */ sync /* * Set Memory Bank 0 ending address to 0xFFE00000 (top of memory) */ addi r3,0,MB0EA stw r3,0x0000(r4) /* write index word to Config Addr */ sync addis r3,0,0xFFF0 /* set MB0EA='FFF' */ stw r3,0x0000(r5) /* write word to Config Data */ sync /* * Set Memory Bank 0 width to 8 bit. */ addi r3,0,RBW stw r3,0x0000(r4) /* write index word to Config Addr */ sync lwz r3,0x0(r5) /* read then modify */ sync rlwinm r3,r3,0,2,31 /* set 64N8_0='00' */ stw r3,0x0000(r5) /* write word to Config Data */ sync /* * Enable writes to Memory Bank 0 since this is FLASH memory */ addi r3,0,FWEN stw r3,0x0000(r4) /* write index word to Config Addr */ sync lwz r3,0x0(r5) /* read then modify */ sync addis r6,0,0x8000 /* set FLSHWEN_0 bit */ or r3,r3,r6 stw r3,0x0000(r5) /* write word to Config Data */ sync /* * Set Memory Bank 0 access mode and timings (speed it up) */ addi r3,0,RPB0P stw r3,0x0000(r4) /* write index word to Config Addr */ sync addis r3,0,0x1C01 /* set TWT=7 THDRD=3 THDWR=2 FWT=F */ ori r3,r3,0x90F0 stw r3,0x0000(r5) /* write word to Config Data */ sync blrFUNC_END(flash_init)/******************************************************************************** periph_init - Initializes CPC700 memory controller bank 3 so that NVRAM,* the keyboard/mouse controller, and FPGA registers can be* accessed.** periph_init* (** )*/FUNC_BEGIN(periph_init) addis r3,0,HIADJ(MEMCFGADR) ori r4,r3,LO(MEMCFGADR) /* r4 <- Memory Config Addr */ ori r5,r3,LO(MEMCFGDATA) /* r5 <- Memory Config Data */ /* * Enable Memory Bank 3 */ addi r3,0,MBEN stw r3,0x0000(r4) /* write index word to Cfg Addr */ sync lwz r3,0x0(r5) /* read then modify */ sync addis r6,0,0x1000 /* set MBE_3 to enable bank 3 */ or r3,r3,r6 stw r3,0x0000(r5) /* write word to Config Data */ sync /* * Set Memory Bank 3 to ROM memory type */ addi r3,0,MEMTYPE stw r3,0x0000(r4) /* write index word to Cfg Addr */ sync lwz r3,0x0(r5) /* read then modify */ sync rlwinm r3,r3,0,8,5 /* set MT_3='00' for ROM */ stw r3,0x0000(r5) /* write word to Config Data */ sync /* * Set Memory Bank 3 starting address to 0xFF800000 */ addi r3,0,MB3SA stw r3,0x0000(r4) /* write index word to Cfg Addr */ sync addis r3,0,0xFF80 /* set MB3SA='FF8' */ stw r3,0x0000(r5) /* write word to Config Data */ sync /* * Set Memory Bank 3 ending address to 0xFF800000 making this the * minimum 1MB region */ addi r3,0,MB3EA stw r3,0x0000(r4) /* write index word to Config Addr */ sync addis r3,0,0xFF80 /* set MB3EA='FF8' */ stw r3,0x0000(r5) /* write word to Config Data */ sync /* * Set Memory Bank 3 width to 8 bit. All attached devices are 8 bit.⌨️ 快捷键说明
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