rominit.s

VxWorks下 Spruce的BSP源代码

/* romInit.s - IBM CPC700 Spruce Board ROM initialization module */

/*******************************************************************************
   This source and object code has been made available to you by IBM on an
   AS-IS basis.

   IT IS PROVIDED WITHOUT WARRANTY OF ANY KIND, INCLUDING THE WARRANTIES OF
   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE OR OF
   NONINFRINGEMENT OF THIRD PARTY RIGHTS.  IN NO EVENT SHALL IBM OR ITS
   LICENSORS BE LIABLE FOR INCIDENTAL, CONSEQUENTIAL OR PUNITIVE DAMAGES.
   IBM'S OR ITS LICENSOR'S DAMAGES FOR ANY CAUSE OF ACTION, WHETHER IN
   CONTRACT OR IN TORT, AT LAW OR AT EQUITY, SHALL BE LIMITED TO A MAXIMUM
   OF $1,000 PER LICENSE.  Anyone receiving this source or object code is
   licensed under IBM copyrights to use it in any way he or she deems fit,
   including copying it, modifying it, compiling it, and redistributing it
   either with or without modifications.  No license under IBM patents or
   patent applications is to be implied by the copyright license.

   Any user of this software should understand that neither IBM nor its
   licensors will be responsible for any consequences resulting from the
   use of this software.

   Any person who transfers this object code or any derivative work must
   include the IBM copyright notice in the transferred software.

   COPYRIGHT   I B M   CORPORATION 1999
   LICENSED MATERIAL  -  PROGRAM PROPERTY OF  I B M

*******************************************************************************/

/* Copyright 1984-2002 Wind River Systems, Inc. */

/*
modification history
--------------------
01i,23jan03,jtp  SPR 84493 recognize 750FX PVR values 700xxxxx
01h,12sep02,pch  SPR 80542: recognize additional 750FX PVR value
01g,03apr02,pch  Update for T2.2; SPR 74348: Machine Check cleanup
01f,19dec01,kab  Update for diab
01e,22jun01,pch  Replace register name RPA with its value so file will
                 assemble for targets that don't have that register.
01d,27mar01,kab  Removed IBM support info per request
01c,03nov00,mcg  update for 750CX
01b,18apr00,ajm  updated to turn on icache and skip sdram init on
                 warm boot
01a,10feb99,mcg  written (from template/romInit.s, ver 01b)
*/

/*
DESCRIPTION
This module contains the entry code for VxWorks images that start
running from ROM, such as 'bootrom' and 'vxWorks_rom'.
The entry point, romInit(), is the first code executed on power-up.
It performs the minimal setup needed to call
the generic C routine romStart() with parameter BOOT_COLD.

RomInit() typically masks interrupts in the processor, sets the initial
stack pointer (to STACK_ADRS which is defined in configAll.h), and
readies system memory by configuring the DRAM controller if necessary.
Other hardware and device initialization is performed later in the
BSP's sysHwInit() routine.

A second entry point in romInit.s is called romInitWarm(). It is called
by sysToMonitor() in sysLib.c to perform a warm boot.
The warm-start entry point must be written to allow a parameter on
the stack to be passed to romStart().

WARNING:
This code must be Position Independent Code (PIC).  This means that it
should not contain any absolute address references.  If an absolute address
must be used, it must be relocated by the macro ROM_ADRS(x).  This macro
will convert the absolute reference to the appropriate address within
ROM space no matter how the boot code was linked. (For PPC, ROM_ADRS does
not work.  You must subtract _romInit and add ROM_TEXT_ADRS to each
absolute address). (NOTE: ROM_ADRS(x) macro does not work for current
PPC compiler).

This code should not call out to subroutines declared in other modules,
specifically sysLib.o, and sysALib.o.  If an outside module is absolutely
necessary, it can be linked into the system by adding the module
to the makefile variable BOOT_EXTRA.  If the same module is referenced by
other BSP code, then that module must be added to MACH_EXTRA as well.
Note that some C compilers can generate code with absolute addresses.
Such code should not be called from this module.  If absolute addresses
cannot be avoided, then only ROM resident code can be generated from this
module.  Compressed and uncompressed bootroms or VxWorks images will not
work if absolute addresses are not processed by the macro ROM_ADRS.

WARNING:
The most common mistake in BSP development is to attempt to do too much
in romInit.s.  This is not the main hardware initialization routine.
Only do enough device initialization to get memory functioning.  All other
device setup should be done in sysLib.c, as part of sysHwInit().

Unlike other RTOS systems, VxWorks does not use a single linear device
initialization phase.  It is common for inexperienced BSP writers to take
a BSP from another RTOS, extract the assembly language hardware setup
code and try to paste it into this file.  Because VxWorks provides 3
different memory configurations, compressed, uncompressed, and rom-resident,
this strategy will usually not work successfully.

WARNING:
The second most common mistake made by BSP writers is to assume that
hardware or CPU setup functions done by romInit.o do not need to be
repeated in sysALib.s or sysLib.c.  A vxWorks image needs only the following
from a boot program: The startType code, and the boot parameters string
in memory.  Each VxWorks image will completely reset the CPU and all
hardware upon startup.  The image should not rely on the boot program to
initialize any part of the system (it may assume that the memory controller
is initialized).

This means that all initialization done by romInit.s must be repeated in
either sysALib.s or sysLib.c.  The only exception here could be the
memory controller.  However, in most cases even that can be
reinitialized without harm.

Failure to follow this rule may require users to rebuild bootrom's for
minor changes in configuration.  It is WRS policy that bootroms and vxWorks
images should not be linked in this manner.
*/

#define _ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "asm.h"
#include "config.h"
#include "cpc700.h"
#include "regs.h"

/* defines */

/* Can't use ROM_ADRS macro with HIADJ and LO macro functions, for PPC */

        /* Exported internal functions */

        .data
        FUNC_EXPORT(_romInit)        /* start of system code */
        FUNC_EXPORT(romInit)         /* start of system code */
        FUNC_EXPORT(_romInitWarm)    /* start of system code */
        FUNC_EXPORT(romInitWarm)     /* start of system code */

        /* externals */

        FUNC_IMPORT(romStart)        /* system initialization routine */

	_WRS_TEXT_SEG_START

/******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
* romInit
*     (
*     int startType     /@ only used by 2nd entry point @/
*     )
*/
FUNC_LABEL(_romInit)
FUNC_BEGIN(romInit)

        /* This is the cold boot entry (ROM_TEXT_ADRS) */

        bl      cold

        /*
         * This warm boot entry point is defined as ROM_WARM_ADRS in config.h.
         * It is defined as an offset from ROM_TEXT_ADRS.  Please make sure
         * that the offset from _romInit to romInitWarm matches that specified
         * in config.h
         */

FUNC_LABEL(_romInitWarm)
FUNC_LABEL(romInitWarm)
        bl      warm

        /* copyright notice appears at beginning of ROM (in TEXT segment) */

        .ascii   "Copyright 1984-1999 Wind River Systems, Inc."
        .align 2

cold:
        li      r11, BOOT_COLD
        bl      start           /* skip over next instruction */

warm:
        or      r11, r3, r3     /* startType to r11 */

start:
        /* Zero-out registers */

        addis   r0,r0,0
        mtspr   SPRG0,r0
        mtspr   SPRG1,r0
        mtspr   SPRG2,r0
        mtspr   SPRG3,r0

        /* Turn off L1 data and instruction cache enable bits */

        mfspr   r3, HID0
        isync
        rlwinm  r4, r3, 0, 18, 15       /* r4 has ICE and DCE bits cleared */
        sync
        isync
        mtspr   HID0, r4                /* HID0 = r4 */
        isync

        /* initialize the stack pointer */

        lis     r1, HIADJ(STACK_ADRS)
        ori     r1, r1, LO(STACK_ADRS)

        /*
         * Set MPU/MSR to a known state. Turn on FP,
         * Interrupts are disabled.
         */

        andi.   r3, r3, 0
        ori     r3, r3, _PPC_MSR_FP
        sync
        mtmsr   r3
        isync

        /* Init the floating point control/status register */

        mtfsfi  7,0x0
        mtfsfi  6,0x0
        mtfsfi  5,0x0
        mtfsfi  4,0x0
        mtfsfi  3,0x0
        mtfsfi  2,0x0
        mtfsfi  1,0x0
        mtfsfi  0,0x0
        isync

        /*
         * Set MPU/MSR to a known state. Turn off FP.
         * Interrupts are disabled.
         */

        andi.   r3, r3, 0
        sync
        mtmsr   r3
        isync

        /* Init the Segment registers */

        andi.   r3, r3, 0
        isync
        mtsr    0,r3
        isync
        mtsr    1,r3
        isync
        mtsr    2,r3
        isync
        mtsr    3,r3
        isync
        mtsr    4,r3
        isync
        mtsr    5,r3
        isync
        mtsr    6,r3
        isync
        mtsr    7,r3
        isync
        mtsr    8,r3
        isync
        mtsr    9,r3
        isync
        mtsr    10,r3
        isync
        mtsr    11,r3
        isync
        mtsr    12,r3
        isync
        mtsr    13,r3
        isync
        mtsr    14,r3
        isync
        mtsr    15,r3
        isync


        /* Get cpu type */

        mfspr   r28, PVR
        rlwinm  r28, r28, 16, 16, 31

        /*
         * From the contents of the PVR register, determine
         * processor type and perform some processor
         * specific initialization
         */

        cmpli   0, 0, r28, CPU_FAMILY_603
        beq     cpuIs603
        cmpli   0, 0, r28, CPU_FAMILY_603E
        beq     cpuIs603
        cmpli   0, 0, r28, CPU_FAMILY_603EV
        beq     cpuIs603
        cmpli   0, 0, r28, CPU_FAMILY_7XX
        beq     cpuIs7xx
	rlwinm	r28, r28, 0, 16, 27		/* ignore 4 LS bits */
        cmpli   0, 0, r28, CPU_FAMILY_750FX	/* 0x700[0-f] */
        beq     cpuIs7xx

here:
        b       here                /* unsupported processor */

cpuIs603:
        /*
         * For 603, Clear the Real Page Address Reg.
	 * Use its number 982 rather than the name RPA so that
	 * this code can be built for targets which aren't 603.
         */
        addi    r4,r0,0x0000
        mtspr   982,r4

        /* And check the HID1 register to see if the 603 CPU running in
         * 1:1 or 3:2 (proc freq : bus freq) mode,
         */
        mfspr   r5,HID1
        rlwinm  r5,r5,4,28,31
        cmpi    cr0,0,r5,0x4
        blt     set_prifopt1
        cmpi    cr0,0,r5,0xC