spruce.h

VxWorks下 Spruce的BSP源代码

/* spruce.h - IBM Spruce eval board header */

/*******************************************************************************
   This source and object code has been made available to you by IBM on an
   AS-IS basis.

   IT IS PROVIDED WITHOUT WARRANTY OF ANY KIND, INCLUDING THE WARRANTIES OF
   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE OR OF
   NONINFRINGEMENT OF THIRD PARTY RIGHTS.  IN NO EVENT SHALL IBM OR ITS
   LICENSORS BE LIABLE FOR INCIDENTAL, CONSEQUENTIAL OR PUNITIVE DAMAGES.
   IBM'S OR ITS LICENSOR'S DAMAGES FOR ANY CAUSE OF ACTION, WHETHER IN
   CONTRACT OR IN TORT, AT LAW OR AT EQUITY, SHALL BE LIMITED TO A MAXIMUM
   OF $1,000 PER LICENSE.  Anyone receiving this source or object code is
   licensed under IBM copyrights to use it in any way he or she deems fit,
   including copying it, modifying it, compiling it, and redistributing it
   either with or without modifications.  No license under IBM patents or
   patent applications is to be implied by the copyright license.

   Any user of this software should understand that neither IBM nor its
   licensors will be responsible for any consequences resulting from the
   use of this software.

   Any person who transfers this object code or any derivative work must
   include the IBM copyright notice in the transferred software.

   COPYRIGHT   I B M   CORPORATION 1999
   LICENSED MATERIAL  -  PROGRAM PROPERTY OF  I B M"

*******************************************************************************/

/* Copyright 1984-2002 Wind River Systems, Inc. */

/*
modification history
--------------------
01i,23jan03,jtp  SPR 84493 recognize additional 750FX PVR values
01h,12sep02,pch  SPR 80542: recognize additional 750FX PVR value
		 SPR 81212: test entire L2 cache on 750FX
01g,22jun02,pch  add 750FX; report PVR if unsupported processor
01f,12jun02,kab  SPR 74987: cplusplus protection
01e,03apr02,pch  use generic pciConfigLib
01d,22jun01,pch  Adjust WRONG_CPU_MSG handling
01c,27mar01,kab  Removed IBM support info per request
01b,02nov00,mcg  updated for 750CX processor
01a,10feb99,mcg  written (from templateppc/template.h, ver 01b)
*/

/*
This file contains I/O addresses and related constants for the
IBM Spruce BSP.  Spruce contains a PowerPC 6xx or 7xx processor
daughter card (Cheetah) and the IBM CPC700 Embedded Chipset.
*/

#ifndef INCspruceh
#define INCspruceh

#ifdef __cplusplus
    extern "C" {
#endif

#define BUS             NONE            /* no off-board bus interface */
#define N_SIO_CHANNELS  2               /* Number of serial I/O channels */


/*
 * Minimum and maximum system clock rates
 */
#define SYS_CLK_RATE_MIN        3       /* minimum system clock rate */
#define SYS_CLK_RATE_MAX        5000    /* maximum system clock rate */

/*
 * The CPC700 has a 32 bit Time Base Counter register that on Spruce is
 * incremented at a frequency of 1/2 the CPU bus speed.  The TBC register
 * provides the reference time for all CPC700 capture and compare timers.
 * Since the CPU bus speed is typically 66MHz or 60MHz, the Time Base
 * Counter will increment at 33MHz or 30MHZ.  See auxiliary clock configuration
 * in config.h.
 */
#define CPC700_TIME_BASE_FREQ     (sysGetBusSpd() / 2)


/* create a single macro INCLUDE_MMU */

#if defined(INCLUDE_MMU_BASIC) || defined(INCLUDE_MMU_FULL)
#define INCLUDE_MMU
#endif

/* Only one can be selected, FULL overrides BASIC */

#ifdef INCLUDE_MMU_FULL
#   undef INCLUDE_MMU_BASIC
#endif

/*
 * PCI bus
 */
#ifdef INCLUDE_PCI
#define SPRUCE_NUM_PCI_SLOTS   4

# ifndef PCI_IN_BYTE
#  define PCI_IN_BYTE(x)         sysPciInByte (x)
# endif	/* PCI_IN_BYTE */
# ifndef PCI_IN_WORD
#  define PCI_IN_WORD(x)         sysPciInWord (x)
# endif	/* PCI_IN_WORD */
# ifndef PCI_IN_LONG
#  define PCI_IN_LONG(x)         sysPciInLong (x)
# endif	/* PCI_IN_LONG */
# ifndef PCI_OUT_BYTE
#  define PCI_OUT_BYTE(x,y)      sysPciOutByte (x,y)
# endif	/* PCI_OUT_BYTE */
# ifndef PCI_OUT_WORD
#  define PCI_OUT_WORD(x,y)      sysPciOutWord (x,y)
# endif	/* PCI_OUT_WORD */
# ifndef PCI_OUT_LONG
#  define PCI_OUT_LONG(x,y)      sysPciOutLong (x,y)
# endif	/* PCI_OUT_LONG */

/*
 * The Spruce board uses an Allied Telesyn PCI Ethernet adapter
 * (AT-2450T) for network attachment. This card contains the AMD
 * Am79C970 controller (PCnet-PCI II).
 *
 * PCI vendor and device information for the AMD Am79C970
 * and registers where the MAC address can be found are in
 * the AMD chip after it loads the contents of the serial
 * EPROM on the card
 */
#ifdef INCLUDE_NETWORK
#   define PCI_VENDOR_ID_AMD     0x1022
#   define PCI_DEVICE_ID_79C97X  0x2000

#   define APROM01               0           /* EEPROM registers */
#   define APROM23               2
#   define APROM45               4
#   define APROM_SIZE            16
#endif	/* INCLUDE_NETWORK */
#endif	/* INCLUDE_PCI */

/*
 * Dallas Semiconductor 8KB NVRAM with Real-Time Clock definitions
 * Reserving the first 1KB of the NVRAM for IBM Eval kit software use.
 */
#define NV_RAM_ADRS     0xFF800000
#define NV_RAM_INTRVL   1
#define NV_RAM_SIZE     (8*1024) - 8          /* 8KB - 8 bytes for the RTC    */
#undef  NV_BOOT_OFFSET
#define NV_BOOT_OFFSET  0x400                 /* Offset of 1KB                */

#define RTC_BASE_ADRS   0xFF801FF8            /* real-time clock base address */

/*
 * FPGA registers and bit definitions
 */
#define FPGA_REG_A           0xFF820000           /* Board status - read only */
#define INVALID_ADDR         0x01
#define UART_CLK_33          0x02
#define UART_CLK_EXT         0x04
#define SMI_PRESENT          0x08
#define IRQ0_PRESENT         0x10
#define SW_RATIO             0x20
#define FPGA_REG_B           0xFF820001           /* Board controls           */
#define SRESET               0x01
#define NMI_REQ_CTL          0x02
#define ECC_MODE_CTL         0x04
#define SMI_CTL              0x08
#define IRQ0_CTL             0x10
#define PCI_ARB_CTL          0x20
#define TEST_SYNC            0xFF820002           /* Test sync                */
#define FPGA_REG_C           0xFF820003      /* Patch area inputs - read only */
#define REG_C_SPARE_IN0      0x01
#define REG_C_SPARE_IN1      0x02
#define REG_C_SPARE_BI0      0x04
#define REG_C_SPARE_BI1      0x08
#define REG_C_SPARE_BI2      0x10
#define REG_C_SPARE_IN2      0x20
#define REG_C_SPARE_IN3      0x40
#define REG_C_SPARE_IN4      0x80
#define FPGA_REG_D           0xFF820004           /* Patch area outputs       */
#define REG_D_SPARE_OUT0     0x01
#define REG_D_SPARE_OUT1     0x02
#define REG_D_SPARE_BI0      0x04
#define REG_D_SPARE_BI1      0x08
#define REG_D_SPARE_BI2      0x10
#define REG_D_EN_SPARE_BI0   0x20
#define REG_D_EN_SPARE_BI1   0x40
#define REG_D_EN_SPARE_BI2   0x80

/*
 * Spruce External IRQ assignments, or how the CPC700 UIC external interrupt
 * pins are actually used on the Spruce board.
 */
#define INT_VEC_FPGA_REG_B           INT_VEC_EXT_IRQ_0
#define INT_VEC_MOUSE                INT_VEC_EXT_IRQ_1
#define INT_VEC_KEYBOARD             INT_VEC_EXT_IRQ_2
#define INT_VEC_PCI_SLOT3            INT_VEC_EXT_IRQ_3     /* J25 */
#define INT_VEC_PCI_SLOT2            INT_VEC_EXT_IRQ_4     /* J26 */
#define INT_VEC_PCI_SLOT1            INT_VEC_EXT_IRQ_5     /* J29 */
#define INT_VEC_PCI_SLOT0            INT_VEC_EXT_IRQ_6     /* J31 */
#define INT_VEC_PCI_PATCH_AREA0      INT_VEC_EXT_IRQ_7
#define INT_VEC_PCI_PATCH_AREA1      INT_VEC_EXT_IRQ_8
#define INT_VEC_PCI_PATCH_AREA2      INT_VEC_EXT_IRQ_9
#define INT_VEC_PCI_PATCH_AREA3      INT_VEC_EXT_IRQ_10
#define INT_VEC_PCI_PATCH_AREA4      INT_VEC_EXT_IRQ_11

#define INT_LVL_FPGA_REG_B           INT_LVL_EXT_IRQ_0
#define INT_LVL_MOUSE                INT_LVL_EXT_IRQ_1
#define INT_LVL_KEYBOARD             INT_LVL_EXT_IRQ_2
#define INT_LVL_PCI_SLOT3            INT_LVL_EXT_IRQ_3     /* J25 */
#define INT_LVL_PCI_SLOT2            INT_LVL_EXT_IRQ_4     /* J26 */
#define INT_LVL_PCI_SLOT1            INT_LVL_EXT_IRQ_5     /* J29 */
#define INT_LVL_PCI_SLOT0            INT_LVL_EXT_IRQ_6     /* J31 */
#define INT_LVL_PCI_PATCH_AREA0      INT_LVL_EXT_IRQ_7
#define INT_LVL_PCI_PATCH_AREA1      INT_LVL_EXT_IRQ_8
#define INT_LVL_PCI_PATCH_AREA2      INT_LVL_EXT_IRQ_9
#define INT_LVL_PCI_PATCH_AREA3      INT_LVL_EXT_IRQ_10
#define INT_LVL_PCI_PATCH_AREA4      INT_LVL_EXT_IRQ_11

/*
 * PowerPC 603, 603e, 603ev, 740, and 750 processor daughter cards are
 * supported in the Spruce board.
 */
#if CPU==PPC604
# define WRONG_CPU_MSG "A PPC604 VxWorks image cannot run on this processor ";
#endif

/*
 * Supported Processor Versions (found in the PVR register of the processor)
 */
#define CPU_TYPE              (vxPvrGet() & 0xffffff00)
#define CPU_TYPE_603          0x00030000     /* PPC 603   CPU */
#define CPU_TYPE_603E         0x00060000     /* PPC 603e  CPU */
#define CPU_TYPE_603EV        0x00070200     /* PPC 603ev CPU */
#define CPU_TYPE_740_750      0x00080200     /* PPC 740 or 750 Arthur CPU */
#define CPU_TYPE_740L_750L    0x00088000     /* PPC 740L or 750L Lonestar CPU */
#define CPU_TYPE_740L_750L_2  0x00088200     /* PPC 740L or 750L Lonestar CPU */
#define CPU_TYPE_740L_750L_3  0x00088300     /* PPC 740L or 750L Lonestar CPU */
#define CPU_TYPE_750CX        0x00082200     /* PPC 750CX */
/* 750FX can selectably report either 0008xxxx or 7000xxxx, also 700xxxxx */
#define CPU_TYPE_750FX        0x00080100     /* PPC 750FX */
#define CPU_TYPE_750FX_7K     0x70000100     /* PPC 750FX */

#define CPU_FAMILY_603        0x0003
#define CPU_FAMILY_603E       0x0006
#define CPU_FAMILY_603EV      0x0007
#define CPU_FAMILY_7XX        0x0008
#define CPU_FAMILY_750FX      0x7000		/* 0x7000 thru 0x700f */

/*
 * L2 Cache -
 *   750 and 750L : The L2 cache is implemented with SRAMs on the processor
 *                  card (aka Cheetah card). The L2 cache is 512KB in size.
 *                  The 750 and 750L are capable of up to 1MB of L2 cache.
 *   750CX        : the L2 cache is on-chip and is 256KB
 *   750FX        : the L2 cache is on-chip and is 512KB
 */

#define L2_CACHE_750_750L_SIZE   (512*1024)
#define L2_CACHE_750CX_SIZE      (256*1024)
#define L2_CACHE_750FX_SIZE      (512*1024)

/*
 * SDRAM Serial EEPROM presence-detect matrix offsets.
 * Values at these offsets are used to help configure the SDRAM controller
 * correctly for the properties of the DIMM.
 */
#define SDRAM_NUM_ROWS     3
#define SDRAM_NUM_COLS     4
#define SDRAM_NUM_BANKS    5
#define SDRAM_WIDTH        6
#define SDRAM_NUM_INTBANKS 17
#define SDRAM_MOD_DENSITY  31

/*
 * SPR addresses for HID1 register and 750 L2 cache control register.
 * These should eventually be found in target/h/arch/ppc/ppc750.h
 */
#define HID1 1009                         /* SPR address for the HID1 reg    */
#define L2CR 1017                         /* SPR address for the L2CR reg    */

#define _PPC_L2CR_ENABLE     0x80000000   /* L2 enable bit                 */
#define _PPC_L2CR_SIZE_512K  0x20000000   /* L2 size is 512KB              */
#define _PPC_L2CR_CLKDIV_21  0x08000000   /* core to L2 freq divider = 2:1 */
#define _PPC_L2CR_RAM_PB     0x01000000   /* L2 RAM pipelined burst        */
#define _PPC_L2CR_DATA_ONLY  0x00400000   /* L2 data-only, no instructions */
#define _PPC_L2CR_INVALIDATE 0x00200000   /* L2 Global Invalidate bit      */
#define _PPC_L2CR_TEST_SPRT  0x00040000   /* L2 Test Support               */
#define _PPC_L2CR_INPROGRESS 0x00000001   /* L2 Invalidate in-progress bit */

#ifdef __cplusplus
    }
#endif

#endif  /* INCspruceh */