config.h

VxWorks下 Spruce的BSP源代码

/* config.h - IBM Spruce board configuration header file */

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   licensors will be responsible for any consequences resulting from the
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   COPYRIGHT   I B M   CORPORATION 1999
   LICENSED MATERIAL  -  PROGRAM PROPERTY OF  I B M"

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/* Copyright 1984-2002 Wind River Systems, Inc. */

/*
modification history
--------------------
01f,12sep02,pch  SPR 80274: support 750FX additional BAT registers
01e,12jun02,kab  SPR 74987: cplusplus protection
01d,04apr02,pch  Revise for T2.2
01c,07nov00,mcg  update for 750CX, added L2 "data only" selection
01b,14sep99,mcg  updated for Tornado 2
01a,09feb99,mcg  Created from template
*/

/*
This file contains the configuration parameters for the IBM Spruce
evaluation board.
*/

#ifndef INCconfigh
#define INCconfigh

#ifdef __cplusplus
    extern "C" {
#endif

/* BSP version/revision identification, before configAll.h */

#define BSP_VER_1_2     1
#define BSP_VER_1_1     1
#define BSP_VERSION     "1.2"   /* A Tornado 2.0 BSP    */
#define BSP_REV         "/3"    /* 0 for first revision */

#include "configAll.h"          /* Set the VxWorks default configuration */

#define DEFAULT_BOOT_LINE \
    "lnPci(0,0)host:/vw/target/config/spruce/vxWorks h=90.0.0.3 " \
    "e=90.0.0.50 u=target"


/* Memory configuration */

/*
 * Boot ROM address space.
 * The Boot ROM is selectable with jumper J8 on the Spruce board.
 * The jumper selects either a 512KB flash (Am29F040) OR a 2MB flash (Am29F016)
 * If pins 1 and 2 are connected with jumper J8, define BOOT_FLASH_2MB below.
 * If pins 2 and 3 are connected with jumber J8, undef BOOT_FLASH_2MB below.
 */

#undef  BOOT_FLASH_2MB

#ifdef  BOOT_FLASH_2MB
#define BOOT_FLASH_ADRS       0xFFE00000
#define BOOT_FLASH_SIZE       0x00200000        /* 2MB */
#else
#define BOOT_FLASH_ADRS       0xFFF80000
#define BOOT_FLASH_SIZE       0x00080000        /* 512KB */
#endif


#define LOCAL_MEM_AUTOSIZE                      /* run-time memory sizing */
#define LOCAL_MEM_SIZE        0x01000000        /* 16MB memory default */
#define LOCAL_MEM_LOCAL_ADRS  0x00000000        /* fixed at zero */
#define USER_RESERVED_MEM     0                 /* see sysMemTop() */

/*
 * The constants ROM_TEXT_ADRS, ROM_SIZE, RAM_HIGH_ADRS, and RAM_LOW_ADRS
 * are defined in config.h and Makefile.
 * All definitions for these constants must be identical.
 */

#define ROM_BASE_ADRS         0xfff00000              /* base address of ROM  */
#define ROM_TEXT_ADRS         (ROM_BASE_ADRS+0x0100)  /* with PC & SP         */
#define ROM_WARM_ADRS         (ROM_TEXT_ADRS+0x0004)  /* warm reboot entry    */
#define ROM_SIZE              BOOT_FLASH_SIZE         /* 512KB or 2MB         */
#define RAM_LOW_ADRS          0x00200000              /* RAM addr for vxWorks */
#define RAM_HIGH_ADRS         0x00400000              /* RAM addr for bootrom */

/* Serial port configuration */

#define INCLUDE_SERIAL
#undef  NUM_TTY
#define NUM_TTY               N_SIO_CHANNELS

/* Timer configuration */

#undef  INCLUDE_TIMESTAMP

/*
 * The auxiliary clock uses compare timer 0 in the CPC700.  Different
 * mask register values produce different auxiliary clock periods.
 * A compare timer causes an interrupt each time the bits that are NOT zero
 * in its corresponding mask register match the CPC700 Time Base Counter.
 */

#define AUX_CLK_PERIOD_1        0x00080000
#define AUX_CLK_PERIOD_MASK_1   0xFFF80000

#define AUX_CLK_PERIOD_2        0x00010000
#define AUX_CLK_PERIOD_MASK_2   0xFFFF0000

/*
 * Using the two pairs of values above, the minumum and maximum
 * auxiliary clock rates in Hz are determined with the following formula:
 *
 *     CPC700_TIME_BASE_FREQ / AUX_CLK_PERIOD_n
 *
 *         where CPC700_TIME_BASE_FREQ = CPU bus frequency / 2   (see spruce.h)
 *
 * Therefore:
 *
 *     When the CPC700 time base counter freq is 33.33MHz :
 *         Minimum    PERIOD 1 ->  64  Hz
 *         Maximum    PERIOD 2 ->  508 Hz
 *
 *     When the CPC700 time base counter freq is 30MHz :
 *         Minimum    PERIOD 1 ->  57  Hz
 *         Maximum    PERIOD 2 ->  457 Hz
 *
 *
 * Adjust the min and max values depending on the TBC frequency which is
 * derived from the CPU bus frequency.
 * For example, a 100MHz 603e has a CPU to bus frequency ratio of 3:1
 * which means the bus clock is 66.66 MHz (CPC700 TBC frequency is 33.33MHz)
 * A 150MHz 603ev has a CPU to bus frequency of 5:2 which means the bus
 * clock is 60MHz (CPC700 TBC frequency is 30MHz).
 */
#define AUX_CLK_RATE_MIN  64
#define AUX_CLK_RATE_MAX  508


/*
 * Cache configuration
 *
 * Note that when MMU is enabled, cache modes are controlled by
 * the MMU table entries in sysPhysMemDesc[], not the cache mode
 * macros defined here.
 */

#define INCLUDE_CACHE_SUPPORT   /* cacheLib support */

#define USER_I_CACHE_ENABLE
#undef  USER_I_CACHE_MODE
#define USER_I_CACHE_MODE        CACHE_WRITETHROUGH
#define USER_D_CACHE_ENABLE
#undef  USER_D_CACHE_MODE
#define USER_D_CACHE_MODE        (CACHE_COPYBACK | CACHE_SNOOP_ENABLE)

/*
 * The IBM Spruce board has an L2 cache only if using the PowerPC 750, 750L,
 * or 750CX processor daughter cards.  The CPC700 itself does not have an
 * integrated L2 cache controller, but the PowerPC 750, 750L, and 750CX
 * processors do.  For the 750 and 750L processor daughter card, the SRAM for
 * the L2 tags and array is located on the processor card (external to the
 * processor), and allows for a 512KB L2 cache.  For the 750CX processor
 * daughter card, the L2 tags and array are contained within the 750CX and are
 * 256KB in size.
 *
 * If the USER_L2_CACHE_DATA_ONLY macro is defined, the L2 cache will cache
 * data accesses only, and not instruction accesses.
 */

/* L2 Cache configuration */

#define INCLUDE_CACHE_L2
#define USER_L2_CACHE_ENABLE
#undef  USER_L2_CACHE_DATA_ONLY


/* MMU configuration */

#define INCLUDE_MMU_BASIC       /* Basic MMU support */
#undef  INCLUDE_MMU_FULL        /* Full MMU support */

/*
 * Enable this setting to build in support for the additional BAT
 * registers in the 750FX processor.  The BSP will still run on other
 * processors.
 */
#define	EXTRA_BATS

/*
 * PCI configuration
 */

#define INCLUDE_PCI

#ifdef INCLUDE_PCI
/*
 * Processor local memory address to PCI memory address mapping.  If a region
 * is enabled, PMMx_LOCAL_ADRS must be between PCI_MEMORY_START and
 * PCI_MEMORY_END.  If PMMx_PCI_HIGH_ADRS is non-zero in an enabled region,
 * 64 bit dual cycle addresses will be generated on the PCI bus for this region.
 */
#    define PMM0_LOCAL_ADRS       PCI_MEMORY_START
#    define PMM0_PCI_LOW_ADRS     0x80000000
#    define PMM0_PCI_HIGH_ADRS    0x00000000
#    define PMM0_PCI_MASK_ATTRIB  (PMM_MASK_512MB | PMM_ENABLE)

#    define PMM1_LOCAL_ADRS       PMM_UNUSED
#    define PMM1_PCI_LOW_ADRS     PMM_UNUSED
#    define PMM1_PCI_HIGH_ADRS    PMM_UNUSED
#    define PMM1_PCI_MASK_ATTRIB  PMM_UNUSED

#    define PMM2_LOCAL_ADRS       PMM_UNUSED
#    define PMM2_PCI_LOW_ADRS     PMM_UNUSED
#    define PMM2_PCI_HIGH_ADRS    PMM_UNUSED
#    define PMM2_PCI_MASK_ATTRIB  PMM_UNUSED

/*
 * PCI memory address to processor local memory address mapping.  If a region
 * is enabled, PTMx_LOCAL_ADRS must be within the two Local memory / peripheral
 * regions (0x00000000-0x7FFFFFFF, or 0xFF80000-0xFFFFFFFF)
 */
#    define PTM1_LOCAL_ADRS       LOCAL_MEM_LOCAL_ADRS
#    define PTM1_SIZE_ATTRIB      PTM_SIZE_2GB | PTM_ENABLE

#    define PTM2_LOCAL_ADRS       PTM_UNUSED
#    define PTM2_SIZE_ATTRIB      PTM_UNUSED

#endif /* INCLUDE_PCI */

/* Real Time Clock configuration */

#define INCLUDE_RTC


/* Network Configuration */

/* remove unused network drivers */

#undef  INCLUDE_EI
#undef  INCLUDE_EX
#undef  INCLUDE_ENP
#undef  INCLUDE_LN
#undef  INCLUDE_SM_NET
#undef  INCLUDE_SM_SEQ_ADDR

#define INCLUDE_END             /* Enhanced Network Driver (see configNet.h) */
#define INCLUDE_NETWORK

#include "spruce.h"             /* Verify user options, specify i/o addr etc */

#ifdef __cplusplus
    }
#endif

#endif /* INCconfigh */

#if defined(PRJ_BUILD)
#include "prjParams.h"
#endif