target.nr

VxWorks下 Spruce的BSP源代码

status and controller register associated with the interrupt.
All interrupts are configured at the same hardware priority.

.TS
tab(|);
lB lB
lfR lfR
l lw .
Device|Interrupt Number
Memory controller Errors|0
PCI Write region|2
UART 0|3
UART 1|4
IIC0|5
IIC1|6
Compare Timer 0|7
Compare Timer 1|8
Compare Timer 2|9
Compare Timer 3|10
Compare Timer 4|11
Capture Timer 0|12
Capture Timer 1|13
Capture Timer 2|14
Capture Timer 3|15
Capture Timer 4|16
FPGA reg B|20
Mouse|21
Keyboard|22
PCI SLOT3|23
PCI SLOT2|24
PCI SLOT1|25
PCI SLOT0|26
Patch area 0|27
Patch area 1|28
Patch area 2|29
Patch area 3|30
Patch area 4|31
.TE

.SS "Serial Configuration"
The two 16550 serial ports integrated in the IBM CPC700 present only two pins
each (transmit and receive).  The serial connector at location J6 is used as
the serial console (9600 bps).

.SS "Network Configuration"
An Allied Telesyn AT-2450T PCI Ethernet adapter is currently supplied with
the Spruce board.  This card has the AMD Am79C970A (PCnet-PCI II) controller
on it and an EEPROM that contains the MAC address of the card.  The Spruce
BSP obtains this MAC address from the EEPROM and provides it to the
initialization portion of the device driver. 

.SS "VME Access"
Spruce does not support VME.

.SS "PCI Access"
PCI configuration space is accessed using a pair of registers in the CPC700.
The addresses of these two registers, PCICFGADR and PCICFGDATA, are defined in
the CPC700.h header file.  Two functions exist (pciConfigIn and pciConfigOut) in
pciconfigLib.c that provide easy access to PCI configuration registers of
various sizes (1 byte, 2 byte, and 4 byte).

The BSP user can change the local memory to PCI address mapping or PCI to
local memory address mapping by changing the PMM and PTM configuration
respectively.  These parameters can be found in config.h.

.SS "Boot Devices"
Ethernet
Serial
JTAG debugger (like RISCWatch)

.SS "Boot Methods"
The following protocols can be used to load and boot a VxWorks image
with the Spruce BSP:

.IP
ftp
.IP
bootp
.IP
tftp
.LP

.SS "ROM Considerations"
The ROM consists of a single 8 bit Am29F040 (512 MB) flash memory.
This part can be programmed in most ROM programmers.  This part
can also be programmed while on the Spruce board, but code for this
is not provided.

.SH "SPECIAL CONSIDERATIONS"
    This BSP does not include BSP specific .man files.
    ROM-resident VxWorks images are too large to fit in the 512KB boot ROM.
    The Makefile is delivered with CPU=PPC604, which is appropriate for any
    604 or 750 processor.  If using a PowerPC 603 processor daughter card,
    change the Makefile to specify CPU=PPC603.
    Use the following parameters in spruce.T1 if running the BSP Verification
    Test Suite:

        T1_MODEL="IBM Spruce 603e"
                  or
        T1_MODEL="IBM Spruce 603ev"
                  or
        T1_MODEL="IBM Spruce 740/750"        # depending on the processor card
        T1_LOCAL_ERR_ADRS=0xffa00000
        T1_OFFBOARD_ERR_ADRS=0xffa00000
        T1_BUS_ERR_MSG="machine check"
        T1_DIV_ZERO_MSG="The value of a is"  # divide by zero does not cause
                                             # an exception in the PowerPC
                                             # architecture



.SS "Delivered Objects"
The following images are delivered with the Spruce BSP:

.IP
bootrom.hex
.IP
vxWorks
.IP
vxWorks.st
.LP

.SS "Make Targets"
VxWorks images vxWorks.res_rom_res_low, vxWorks_.res_rom_nosym_res_low,
and vxWorks_rom are too large to fit in the 512KB boot ROM.  These images
will not build.

.SS "Special Routines"
Not Applicable.

.SS "Known Problems"
The following are known problems with the Spruce BSP.

   1. Since sysTimestampDisable() has no effect in the timestamp driver in
      /drv/timer/ppcDecrementer.c, the test in the BSP VTS (timestamp.tcl)
      that stops the time stamp timer fails.  This is true for all PowerPC
      6xx/7xx BSPs that use the system clock driver and and timestamp driver
      in /drv/timer/ppcDecrementer.c
   2. The off-board error address test in the BSP VTS (error1.tcl) fails.
      The BSP configures the CPC700 to inform the processor via machine check
      when an address is accessed outside what is configured in the memory
      controller, but it can not report a second invalid access until the
      first one is cleared in the CPC700 ERRDET1 register.  The CPC700
      successfully detects and causes a machine check exception when the
      local error address test is run, but since the VxWorks default machine
      check handler does not clear the status bit in the ERRDET1 register,
      the subsequent off-board error access is not reported to the processor.

.SH "BOARD LAYOUT"
The diagram below shows jumpers relevant to VxWorks configuration.

.bS
                 IBM Spruce
________________________________          ________________          ________
|                               ----------                ----------       |
|  P  P  P  P                   J20 UART 1                J6  UART 0       |
|  C  C  C  C                                   _                          |
|  I  I  I  I                                  | |                         |
|                     _                        |S|                         |
|  S  S  S  S        | |                       |D|                         |
|  L  L  L  L        |P|  L - Jumper J16       |R|                         |
|  O  O  O  O        |R|                       |A|                         |
|  T  T  T  T        |O|                       |M|                         |
|                    |C|                       | |                         |
|  4  3  2  1        |E|                       |D|   ___                   |
|                    |S|                       |I|  | U |                  |
|                    |S|                       |M|  | 2 | D - Jumper J8    |
|                    |O|                       |M|  |___|                  |
|                    |R|                       |_|                         |
|                    | |                              U2 - boot ROM        |
|                    |C|                                                   |
|                    |A|                                                   |
|                    |R|                                                   |
|  X - JUMPER J1     |D|                                                   |
|                    |_|                                                   |
|__________________________________________________________________________|
.bE
    Key:
    X  vertical jumper installed
    :  vertical jumper absent
    -  horizontal jumper installed
    "  horizontal jumper absent
    0  switch off
    1  switch on
    U  three-pin vertical jumper, upper jumper installed
    D  three-pin vertical jumper, lower jumper installed
    L  three-pin horizontal jumper, left jumper installed
    R  three-pin horizontal jumper, right jumper installed

.SH "SEE ALSO"
.tG "Getting Started,"
.pG "Configuration,"
.pG "Architecture Appendix"

.SH "BIBLIOGRAPHY"
The following documents are available on the IBM PowerPC Embedded Processors,
Cores, and Tools product documentation CDROM, or on the World Wide Web at http://www.chips.ibm.com/products/powerpc/tools/ or http://www.chips.ibm.com/products/powerpc/chips/

.iB "IBM PowerPC 6xx/7xx CPC700 Reference Design Kit User's Manual"
.iB "IBM PowerPC 6xx/7xx CPC700 Reference Board Manual"
.iB "IBM PowerPC CPC700 Memory Controller and PCI Bridge Data Sheet"
.iB "CPC700 User's Manual"
.iB "PowerPC 740 and 750 Embedded Microprocessor Datasheet"
.iB "PowerPC 740 and 750 Embedded Microprocessor Hardware Specification"
.iB "PowerPC 740 and 750 RISC Microprocessor User's Manual"
.iB "PowerPC 750CX Supplement to the PowerPC 750 RISC Microprocessor User Manual"
.iB "PowerPC 603e and EM603e Embedded Hardware Specification"
.iB "PowerPC 603e RISC Microprocessor Technical Summary"
.iB "PowerPC 603e and EM603e RISC Microprocessor Family User's Manual"