target.nr

VxWorks下 Spruce的BSP源代码

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.\" spruce/target.nr - IBM Spruce target specific documentation
.\"
.\" Copyright 1984-2003 Wind River Systems, Inc.
.\" Copyright 1999      IBM Corporation
.\"
.\" modification history
.\" --------------------
.\" 01f,07mar03,pch  editorial revisions
.\" 01e,05mar03,pch  Add "Power Considerations"
.\" 01d,27aug01,dgp  change manual pages to reference entries per SPR 23698
.\" 01c,27mar01,pew  Fix table formatting.
.\" 01b,08nov00,mcg  update for 750CX
.\" 01a,01may99,mcg  derived from template
.\"
.TH Spruce T "IBM PowerPC Spruce" "Rev: 01 May 99" "TORNADO REFERENCE: VXWORKS"

.SH "NAME"
.aX "IBM PowerPC 6xx/7xx CPC700 Reference Board (a.k.a. Spruce)"

.SH "INTRODUCTION"
This reference entry provides board-specific information necessary to run
VxWorks with the Spruce BSP. Before using a board with VxWorks,
verify that the board runs in the factory configuration by using
vendor-supplied ROMs and jumper settings and checking the RS-232
connection.

.SS "Boot ROMs"
The boot ROM for the Spruce BSP is an AMD Am29F040 Flash Memory part.
This part is 512K bytes in size and resides at the very top of the address
space. Install the VxWorks boot ROM in socket U16 and make sure that jumper J8
is connecting pins 2 and 3.  This jumper setting selects the flash part in
socket U16 as the boot ROM.

The NVRAM in the Dallas Semiconductor DS1643P preserves VxWorks boot
parameters whenever the system is powered off.

To load VxWorks, and for more information, follow the instructions in the
.I "Tornado User's Guide: Getting Started."

.SS "Power Considerations"
When equipped with a 750CX processor module, the Spruce board may not
draw enough power to properly load an ATX power supply, resulting in
unexpected resets.  Some versions of the Spruce system are supplied with
a case-mounted 2.5-ohm, 50-watt load resistor, which can be connected
across the 5V supply to correct this problem.  The load resistor may
not be needed when using other processor modules, which consume more
power, or if the ATX supply is also powering other devices such as disk
drives or multiple PCI cards.

.SS "Jumpers"

.TS E
expand;
lB lB lB
lfR lfR lfR
l l lw(3i) .
.ne 5
Jumper	Function	Description
_
J8	 ROM Selection	T{
Connect pins 2 and 3 to select the socketed AMD Am29F040 Flash.
Connect pins 1 and 2 to select the unsocketed AMD Am29F016 Flash.
T}
J16	 SDRAM Mode Selection	T{
Connect pins 1 and 2 to select normal SDRAM mode (default).
Connect pins 2 and 3 (and replace the SDRAM DIMM with an ECC SDRAM DIMM) to
select ECC SDRAM mode.
T}
J16	 Arbiter Selection	T{
Connect pins 1 and 2 to use the PCI arbiter within the IBM CPC700.
Connect pins 2 and 3 to use the external PCI arbiter in the FPGA at U49.
T}
.TE
.PP
For details of jumper configuration, see the board diagram at the end
of this entry.  Also see the board's hardware manual for other jumpers
not directly related to VxWorks operation.

.SH "FEATURES"

.SS "Supported Features"
The following features of the IBM Spruce board are supported in the
Spruce BSP:

    Processor daughter cards for PowerPC 603e, 603ev, 740, 750, and 750CX.
    IBM CPC700 embedded peripheral chip
    Integrated features of the IBM CPC700 supported are:
        PCI bridge
        internal PCI arbiter
        SDRAM controller for normal or ECC SDRAM
        SRAM/ROM/peripheral controller
        2 UARTs
        1 I2C port (dedicated to read serial EEPROMs on SDRAM DIMMS)
        Universal Interrupt Controller
        general purpose timers (used by auxiliary clock driver)
    Dallas Semiconductor DS1643P; both NVRAM and real-time clock
    Four 33MHz, 5V PCI slots.
    AMD PCnet(TM)-PCI II ethernet via a PCI card supplied with the Spruce board.
    External PCI arbiter (in an FPGA)

SDRAM options:

    For SDRAM, the Spruce board has a single 168 pin DIMM socket.
    A 16M SDRAM DIMM (non-ECC) is included with the Spruce board
    which can be replaced if more memory or ECC memory is desired.

    The following 64 bit memory sizes are supported:
       16M  (single sided 2M x 64)
       32M  (double sided 4M x 64)
       64M  (single sided 8M x 64)
       128M (double sided 16M x 64)

    For ECC support, the following 72 bit memory sizes are supported:
       16M  (single sided 2M x 72)
       32M  (double sided 4M x 72)
       64M  (single sided 8M x 72)
       128M (double sided 16M x 72)

    SDRAM DIMMs use I2C compatible serial presence detect EEPROMs.
    One of the I2C ports of the CPC700 is dedicated to reading this
    EEPROM which supplies the SDRAM configuration routine with
    information required to properly initialize the SDRAM controller.

.SS "Unsupported Features"
The following features of the IBM Spruce board are not supported in the
Spruce BSP:

    Intel S82C42PC Keyboard/Mouse Controller
    The 2nd I2C port on the IBM CPC700
    AMD 29F016 Flash for boot ROM (can be supported with minor BSP modfications)
    Processor data bus parity (not verified)

.SS "Feature Interactions"
    The CPC700 internal PCI arbiter and processor data bus parity are mutually
    exclusive features because they share the same pins on the CPC700.  If
    processor data bus parity is desired, an external PCI arbiter must be used.

.SH "HARDWARE DETAILS"
This section documents the details of the device drivers and board
hardware elements.

.SS "Devices"
The chip drivers included are:

.TS
expand tab(|);
l lw(4i)
l lw(4i) .
byteNvRam.c|byte-oriented generic non-volatile RAM library
nullVme.c|no VME support library
ppcDecTimer.c|system clock and timestamp driver using PPC decrementer
CPC700Intr.c|CPC700 Univeral Interrupt controller driver
sysSerial.c|prepares serial driver evbNs16550sio
sysNet.c|prepares PCI Ethernet driver if_lnPci
sysCache.c|PowerPC 750 L2 cache library
pciConfigLib.c|CPC700 PCI configuration library
auxClock.c|Auxiliary clock driver that uses CPC700 compare timer
d1642RTC.c|real-time clock driver for Dallas DS1642
.TE

.SS "Memory Maps"

.TS
expand tab(|);
lB lB 
lfR lfR
l lw(4i) .
Local Bus|Address Map
SDRAM|0x00000000  -  0x7FFFFFFF   (max 128M bytes)
PCI Memory*|0x80000000  -  0xF7FFFFFF   (1.92G bytes)
PCI I/O|0xF8000000  -  0xF800FFFF   (64K bytes)
PCI I/O|0xF8800000  -  0xFBFFFFFF   (56M bytes)
PCI Configuration|0xFEC00000  -  0xFEC00007   (8 bytes)
PCI Local Configuration|0xFF400000  -  0xFF40003F   (64 bytes)
CPC700 Processor Interface|0xFF500000  -  0xFF500007   (8 bytes)
CPC700 Memory Controller|0xFF500008  -  0xFF50000F   (8 bytes)
CPC700 Interrupt Controller|0xFF500880  -  0xFF5008A3   (36 bytes)
CPC700 UART0|0xFF600300  -  0xFF600307   (8 bytes)
CPC700 UART1|0xFF600400  -  0xFF600407   (8 bytes)
CPC700 I2C0|0xFF620000  -  0xFF620010   (17 bytes)
CPC700 I2C1|0xFF630000  -  0xFF630010   (17 bytes)
CPC700 Timers|0xFF650000  -  0xFF6500FF   (256 bytes)
Dallas 1643 NVRAM/RTC|0xFF800000  -  0xFF801FFF   (8K bytes)
FPGA registers|0xFF820000  -  0xFF820004   (5 bytes)
Boot ROM (Flash)|0xFFF00000  -  0xFFFFFFFF   (512K bytes)
.TE
    * Local memory address to PCI memory address mapping is variable and is
      controlled by the 3 PMM (PCI Master Map) register sets in the CPC700.
      The default configuration maps one 512 MB region of local memory
      starting at address 0x80000000 to PCI address space starting at
      0x80000000.  See the IBM CPC700 User's Manual for more details.


PCI Bus Address Map

    PCI memory address to local memory address mapping is variable and is
    controlled by the 2 PTM (PCI Target Map) register sets in the CPC700.
    The default configuration maps one 2 GB region of PCI memory address
    space starting at address 0x00000000 to local address space starting at
    0x00000000.  See the IBM CPC700 User's Manual for more details.

.SS "Shared Memory"
Shared memory is not supported.

.SS "Interrupts"
The Universal Interrupt Controller (UIC) integrated into the IBM CPC700
monitors the following external interrupt sources:
The number associated with the interrupt is the bit number in the UIC