target.nr

VxWorks下 Mcpn750的BSP源代码

.SS "Compact Flash Configuration"
Compact Flash is supported on the MCPN750 as IDE controller 0, device 0 & 1.  To
configure the compact flash, perform the following:
.IP "1)"
In config.h, replace "#undef INCLUDE_ATA" with "#define INCLUDE_ATA".
.IP "2)"
Set the definitions of ATA_DEV0_STATE and ATA_DEV1_STATE to DEV_PRESENT or DEV_NOT_PRESENT as required.
.IP "3)"
Rebuild the kernel.  After booting, the compact flash device can
be configured with the following command:

.CS
        usrAtaConfig(0,0,"/ata0") /* Dev 0 */
        usrAtaConfig(0,1,"/ata1") /* Dev 1 */
.CE

.SS "Universal Serial Bus Configuration"
Two USB ports are supported on the MCPN750.  They are located on the optional
TMCPN710 transition module as J10 and J12.  The USB controller is inside the
PCI Peripheral Bus Controller (PBC) on the MCPN750 and is HCI v1.1 compatible.

The \f2USB Developer Kit\f1 for Tornado is available as an optional product.
It includes a USB stack for VxWorks, as well as drivers for various types
of USB peripherals.  Detailed information can be obtained from the
\f2USB Developer Kit\f1 documentation.

To enable PCI auto configuration of the USB device, the file sysBusPci.c
needs to be modified.  In sysPciAutoConfigInclude(), the \f3case PCI_ID_USB\f1
in \f3switch(devVend)\f1 should be changed to return OK instead of ERROR.
After this change, rebuild and flash a new bootrom by following the
instructions in the "ROM Considerations" section.  After verifying the new
bootrom is functioning properly, proceed to the \f2USB Developer Kit\f1
documentation.

.SS "Processor Data Bus Parity Configuration"
Processor data bus parity checking is supported on the MCPN750 and is enabled by
default.
.HP 6
NOTE: Do not read the CPU Control Register ($FEF88300) while processor
data parity checking is enabled. Reading this register with processor data
parity checking enabled may result in a parity error.
.P
To disable processor data bus parity checking, perform the following:
.IP "1)"
In config.h, replace "#define INCLUDE_DPE" with "#undef INCLUDE_DPE".
.IP "2)"
Rebuild the kernel.

.SS "Vital Product Data"
Support is available for retrieving and displaying Vital Product Data (VPD) from
serial EEPROM devices located on the processor board and transition module (if
installed.) This data is presented for informational purposes only.

Two VPD Show routines are available as part of this BSP. To access them, perform
the following:
.IP "1)"
In config.h, add "#define INCLUDE_SHOW_ROUTINES".
.IP "2)"
Rebuild the kernel.
.IP "3)"
Reboot the system.
.IP "4)"
At the command line, type "vpdBrdShow" or "vpdTmShow" to display the processor
board or transition module VPD information.

.HP 6
NOTE: Reading the serial EEPROMs is performed at system boot time and increases
system boot time by 500-600 mSecs.
.P
If VPD information is not required, it
can be eliminated by making the following changes:
.ne 2
.sp .5
.IP "1)"
In config.h: Change #define INCLUDE_VPD to #undef INCLUDE_VPD.
.IP "2)"
Rebuild the kernel.

.SS "Boot Devices"
The supported boot device is:

    \f3dc\f1 - Ethernet (10baseT or 100baseTX or AUI)

Motorola's PPC1-Bug can be used to download and run VxWorks.
Consult the user's manuals for details.

.SS "Flashing the Boot ROM Using Motorola PPC1-Bug:" 1

At the PPC1-Bug prompt, set up the network transfer from a TFTP host using 
`niot'.  Important: You must have a TFTP server running on your host's
subnet for the `niop' command to succeed.  Using `niot', the Client IP Address,
Server IP Address, and Gateway IP Address must be set up for the user's
specific environment:

.CS
   PPC1-Bug>niot
   Controller LUN =00?
   Device LUN     =00?
   Node Control Memory Address =00FA0000?
   Client IP Address      =123.123.10.100? 123.321.12.123
   Server IP Address      =123.123.18.105? 123.321.21.100
   Subnet IP Address Mask =255.255.255.0?
   Broadcast IP Address   =255.255.255.255?
   Gateway IP Address     =123.123.10.254? 123.321.12.254
   Boot File Name ("NULL" for None)     =? .

   Update Non-Volatile RAM (Y/N)? y
   PPC1-Bug>
.CE

The file is transferred from the TFTP host to the target board using
the `niop' command.  The file name must be set to the location
of the binary file on the TFTP host.  The binary file must be stored
in the directory identified for TFTP accesses, but the file name is
a relative path and does not include the \f3/tftpboot\f1 directory name:

.CS
   PPC1-Bug>niop
   Controller LUN =00?
   Device LUN     =00?
   Get/Put        =G?
   File Name      =? bootrom.bin
   Memory Address =00004000?
   Length         =00000000?
   Byte Offset    =00000000?

   PPC1-Bug>
.CE

After the file is loaded onto the target, the `pflash' command is used
to put it into soldered FLASH parts.

.CS
   PPC1-Bug>pflash 4000:FFF00 ff000100
.CE

When the command is finished, power down the board and switch the ROM
jumper to select soldered FLASH.  Then power the board back up.

.SH "SPECIAL CONSIDERATIONS"
This section describes miscellaneous information concerning this BSP and its
use.

.SS "Delivered Objects"
The delivered objects are: `bootrom', `bootrom.hex', `vxWorks', 
`vxWorks.sym', and `vxWorks.st'.

.SS "Make Targets"
The make targets are listed as the names of object-format files.  Append `.hex'
to each to derive a hex-format file name.

.ne 9
.nf
`bootrom'
`bootrom_uncmp'
`bootrom_res_high'
`vxWorks' (with `vxWorks.sym')
`vxWorks.st'
`vxWorks_rom'
`vxWorks.st_rom'
`vxWorks.res_rom_res_low' (builds but does not execute)
`vxWorks.res_rom_nosym_res_low' (builds but does not execute)
.fi

Note, "bootrom_res", "vxWorks.res_rom", and "vxWorks.res_rom_nosym" are
also make targets but are not part of the PowerPC supported set.  These
particular targets will not build in the PowerPC environment.

.SS "Special Routines"
For these boards, the value of the CPU clock speed is read from the CPU 
configuration register using the macro MEMORY_BUS_SPEED which is defined
in mcpx750.h.  For example:

.CS
   clkFreqMhz = MEMORY_BUS_SPEED;
.CE

.SS "Known Problems"

.IP "Spurious transactions on ISA devices"
It has been discovered that the VIA PCI-to-ISA bridge device has
a subtractive decoder which cannot be disabled. Therefore, when a PCI
access is performed to a non-existent PCI I/O or Memory address on the
local PCI bus, the VIA PCI-to-ISA bridge will respond and forward the
transaction onto the ISA bus using the lower 24 bits of the PCI address
as the ISA address. The operation can result in spurious transactions
if the resulting ISA address maps to a valid ISA device. If the ISA
device does not exist, the PCI-to-ISA bridge returns 0xffffffff if the
transaction is a read and discards the data on a write. This behavior
prevents the generation of the Master Abort used to detect a faulty local
PCI access and essentially nullifies the results of a probe directed at
a local PCI I/O or Memory address. If the PCI transaction is claimed
by the Dec2155x and forwarded to the cPCI bus, the PCI-to-ISA
subtractive decoder does not respond and the Dec2155x will provide the
proper response (Target Abort) when an invalid cPCI I/O or Memory
address is presented. In this case, the results of the probe are valid.
The probe result is also valid if the access references an address
that produces an MMU fault regardless of the target address space
(local or cPCI I/O or Memory or local DRAM).

.IP "Device dc fail to start"
Some earlier verions of the MCPN750 boards were shipped with an incorrectly
programmed dec21143 SROM. As a result, booting with the END driver will fail
with the message "Failed to start device dc." The SROM was mis-programmed with
an extra byte inserted at offset 0x20 with a value of 0x03. The rest of the
SROM data was shifted down. A mis-programmed SROM appears as follows:
.CS
PPC1-Bug>srom
...
$1E (&030) 0008?
$20 (&032) 0301? <---- 0x03 in the upper halfword is the extra byte
$22 (&034) 9303?
...
.CE
The following instructions capture how to use PPC1-Bug to remove the extra
byte from the SROM. \f3WARNING:\f1 Special care must be taken in the
following steps, or further corruption of the SROM may result:
.CS
PPC1-Bug>srom

Device Address =$00007000 (N/Y)? y
Reading SROM into Local Buffer.....
$00 (&000) 5710?
$02 (&002) 5634?
$04 (&004) 0000?
$06 (&006) 0000?
$08 (&008) 0000?
$0A (&010) 0000?
$0C (&012) 0000?
$0E (&014) 0000?
$10 (&016) 1300?
$12 (&018) 0301?
$14 (&020) 0800?
$16 (&022) 3E28?
$18 (&024) 3DBF?
$1A (&026) 0E1E?
$1C (&028) 0000?
$1E (&030) 0008?
$20 (&032) 0301? 0193
$22 (&034) 9303? 0308
$24 (&036) 0800? 0003
$26 (&038) 0301? 0108
$28 (&040) 0800? 0000
$2A (&042) 0001? 0100
$2C (&044) 0000? 0078
$2E (&046) 78E0? E001
$30 (&048) 0100? 0050
$32 (&050) 5000? 0018
$34 (&052) 1800? 0000
$36 (&054) 0000? .
...

Update SROM (Y/N)? y

Calculate CRC (Y/N)? y
Writing SROM from Local Buffer.....
Verifying SROM with Local Buffer...
PPC1-Bug>
.CE

.SS "Pseudo-PReP Memory Model"
The following table describes the modified PowerPC Reference Platform (PReP)
address map. Tornado-compatible mapping deviates only slightly from the model.

.TS E
expand;
lf3 lf3 lf3
lw16 lw15 lw(1.8i) .
.ne 6
.sp .5
Start (CPU addr)	Size	Access to
_
0x0	T{
LOCAL_MEM_SIZE (16MB min)
T}	DRAM
LOCAL_MEM_SIZE	T{
(0x80000000 - LOCAL_MEM_SIZE)
T}	[Not used]
0x80000000	64K	PCI I/O space (16-bit)
0x80010000	8M-64K	[Not Used]	
0x80800000	8M	T{
Direct Map PCI Cfg. Space
T}
0x81000000	T{
1G-16M (0x3F000000)
T}	PCI I/O space (32-bit)
0xC0000000	T{
1G-48M (0x3D000000)
T}	PCI MEM space
0xFD000000	T{
504M (0x1F800000)
T}	Reserved
0xFEF80000	64K	Falcon Registers
0xFEF90000	384K	Reserved
0xFEFF0000	64K	Raven Registers
0xFF000000	8M	ROM/FLASH Bank A
0xFF800000	1M	ROM/FLASH Bank B
0xFF900000	6M	Reserved
0xFFF00000	1M	ROM/FLASH Bank A or Bank B
.TE

.SH "BOARD LAYOUT"
The diagram below shows flash EEPROM locations and jumpers relevant to VxWorks
configuration:

Serial port 1 (COM1) and the Ethernet port appear both on the MCPN750 and 
the TMCPN710 transition module.  The USB ports, COM3 and COM4 headers and
connectors for IDE CompactFLASH appear only on the TMCPN710 transition
module.

.ne 4i

.bS
____________________________________________________________________________
|                          Needs TMCPN710-001(002)                         |
|                          Transition Module                               |
____________________________________________________________________________
|                                                                          |
|  =========== =========== =========== ===========                         |
|                                                                          |
|  =========== =========== =========== ===========                         |
|         PMC slot                PMC slot                                 |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                                          |
| D (J7)                                                                   |
|                                                                          |
|      +-----+ +-----+                                                     |
|      |XU1  | |XU2  |                                                     |
|      |     | |     |                                                     |
|      +-----+ +-----+                                                     |
|          PPC1Bug                                                         |
|                                                                          |
|______.......................___.......................____----_____----__|
         PCI Mezzanine Card        PCI Mezzanine Card      10/100    Com1 
              Cutout                    Cutout             base T  
.bE
    Key: 
    U  three-pin vertical jumper, upper jumper installed
    D  three-pin vertical jumper, lower jumper installed

.SH "SEE ALSO"
.tG "Getting Started,"
.pG "Configuration"

.SH "BIBLIOGRAPHY"
.iB "MCPN750 CompactPCI Single Board Computer Installation and Use,"
.iB "TMCPN710 Transition Module Installation and Use,"
.iB "Motorola MPC750 RISC Microprocessor User's Manual,"
.iB "Motorola PowerPC Microprocessor Family: The Programming Environments,"
.iB "VT82C586B PCI Peripheral Bus Controller,"
.iB "DECchip 21143 PCI Fast Ethernet LAN Controller Hardware Reference Manual,"
.iB "Peripheral Component Interconnect (PCI) Local Bus Specification, Rev 2.1,"
.iB "PCI to PCI Bridge Architecture Specification 2.0,"
.iB "PICMG 2.0 D2.14 CompactPCI Specification,"
.iB "Digital Semiconductor 2155x PCI-to-PCI Bridge for Embedded Applications Hardware Reference Manual,"
.iB "IEEE Standard 1284 Bidirectional Parallel Port Interface Specification,"
.iB "IEEE P1386.1 Draft 2.0 - PCI Mezzanine Card Specification (PMC),"
.iB "IEEE P1386 Draft 2.0 - Common Mezzanine Card Specification (CMC),"
.iB "SGS-Thompson MK48T59/559 CMOS 8K x 8 TIMEKEEPER SRAM Data Sheet."