target.nr

VxWorks下 Mcpn750的BSP源代码

        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.200.200.2
        target name (tn)     : beta
.CE

.ne 6
.IP "6)"
MCPN750 master, MCPN750 anchor, sequential addressing:
.CS

   MCP750:

        #define SM_OFF_BOARD TRUE
        #undef  SYS_SM_SYSTEM_MEM_POLL
        /* #undef  INCLUDE_SM_SEQ_ADDR */

        boot device          : sm
        processor number     : 1
        host name            : sunray
        inet on ethernet (e) :
        inet on backplane (b):
        host inet (h)        : 124.170.16.143
        gateway inet (g)     :
        target name (tn)     : gamma

   MCPN750-1:

        #define SM_OFF_BOARD FALSE
        #undef  SYS_SM_SYSTEM_MEM_POLL
        /* #undef  INCLUDE_SM_SEQ_ADDR */

        boot device          : dc
        processor number     : 0
        host name            : sunray
        inet on ethernet (e) : 124.170.16.109:ffffff00
        inet on backplane (b): 124.200.200.1:ffffff00
        host inet (h)        : 124.170.16.143
        gateway inet (g)     : 124.170.16.233
        target name (tn)     : alpha

   MCPN750-2:

        #define SM_OFF_BOARD TRUE
        #undef  SYS_SM_SYSTEM_MEM_POLL
        /* #undef  INCLUDE_SM_SEQ_ADDR */

        boot device          : sm
        processor number     : 2
        host name            : sunray
        inet on ethernet (e) :
        inet on backplane (b):
        host inet (h)        : 124.170.16.143
        gateway inet (g)     :
        flags (f)            : 0x0
        target name (tn)     : beta
.CE

.SS "Unsupported Features"
The following board features are not supported:

.TS E
expand;
lf3 lf3
lw13 lw(3.7i) .
.ne 6
.sp .5
Feature	Description
_
RTC	T{
MK48T59/559; only NVRAM portion is used
T}
Peripherals	T{
SROM (I2C interface).
T}
ISA Interface	T{
ISA RTC.
T}
PCI Interface	T{
64-bit data; Prefetchable memory is not distinguished from nonprefetchable.
T}
Compact PCI	T{
Compact PCI device autoconfiguration and compact PCI bus interrupt handling.
T}
Hot Swap	T{
No software support for hot swap.
T}
Registers	T{
No support for Board Status and Board Last Reset registers.
T}
Timers	T{
Watchdog timers.
T}
.TE

.SS "Feature Interactions"
.IP "MPIC Spurious Interrupts"

A race condition can exist between PCI write posting and interrupt
processing which can cause an MPIC spurious interrupt.  The problem occurs
when a device's interrupt service routine writes to clear the interrupt
source and then returns to the interrupted code. When the PCI bus is very
busy, the write takes a while to get onto the bus and reach the
interrupting device. During this time, the device's interrupt will remain
asserted. If the PowerPC reenables external interrupts before the PCI
write has reached the interrupting device, the processor will see the
interrupt still asserted and re-enter the MPIC interrupt routines.

When the MPIC handler reads the vector, the MPIC reports a spurious
interrupt because the PCI write has generally completed by then and the
device's interrupt has now been cleared.

.IP "Spurious Interrupt Workaround"

Modify the driver to perform a read from the PCI device (after writing to
the device to clear the interrupt) to ensure that 
the write has fully propagated.  sysPciOutWordConfirm() will do this
automatically. Note that sysPciOutWordConfirm() reads from the address
written which may cause an undesirable side-effect depending on the design
of the hardware. If it does, just add a read from any safe location on the
device. The primary goal is force the write out of the posting queues before
proceeding.

.LP

.SH "HARDWARE DETAILS"
This section details device drivers and board hardware elements.

.SS "Devices"
The device drivers and libraries included with this BSP:

.TS C
center;
rw(1.oi) lw(3.7i) .
i8250Sio:	T{
Intel 8250 UART driver (serial ports 1 and 2).
T}
ppcDecTimer:	T{
PowerPC decrementer timer driver (system clock).
T}
ravenAuxClk:	T{
Motorola Raven timer driver for auxiliary clock.
T}
ravenMpic:	T{
Motorola Raven MPIC interrupt controller driver.
T}
ravenPci:	T{
Motorola Raven PCI bus bridge chip driver.
T}
pciAutoConfigLib:	T{
PCI autoconfiguration library.
T}
pciConfigLib:	T{
PCI configuration library.
T}
pciConfigShow:	T{
Show routines of PCI bus library.
T}
dec21x40End:	T{
10baseT/100baseTX DEC 21x4x Ethernet driver.
T}
byteNvRam:	T{
byte-oriented generic non-volatile RAM driver.
T}
ns8730xSuperIo:	T{
National Semiconductor 8730x Super IO driver.
T}
ataDrv:	T{
ATA/IDE (LOCAL and PCMCIA) disk device driver.
T}
isaDma:	T{
DMA controller device (I8237) utilities/support driver.
T}
fdcDrv:	T{
driver for PS2 floppy device controller(FDC)
T}
dec2155xCpci.c:	T{
DEC 2155x Non-Transparent PCI-to-PCI Bridge support.
T}
vpd:	T{
Vital Product Data Support.
T}
hawkI2c:	T{
Falcon/Hawk I2C support.
T}
.TE

.SS "Memory Maps"
On-board RAM for these boards always appears at address 0x0 locally.

Dynamic memory sizing is supported.  By default, LOCAL_MEM_AUTOSIZE is
defined so memory is auto-sized at hardware initialization time.
If auto-sizing is not selected, LOCAL_MEM_SIZE must be set to the actual size
of DRAM memory available on the board to ensure all memory is available.
The default fixed RAM size is set to 16MB (see LOCAL_MEM_SIZE in config.h).

.SS "Interrupts"
The system interrupt vector table has 256 entries.  Vectors for the various
devices on the buses are assigned hierarchically as follows:

.TS C
center;
lf3 lf3
l lw(2.6i) .
.ne 6
.sp .5
Vector#	Assigned to
_
00 - 0f	ISA IRQ numbers 0 - 15
10 - 1f	All MPIC interrupts
20 - 23	Raven timers
24 - 27	Raven interprocessor dispatch
   28  	Raven detected internal errors
29 - 5f	[User defined]
60 - 72	Dec2155x interrupts
73 - ff	[User defined]
.TE

The specific ISA vector number assignments are:

.TS C
center;
lf3 lf3
l lw(2.6i) .
.ne 6
.sp .5
Vector#	Assigned to
_
   02	[Cascade interrupt from PIC2]
   03	COM2 and COM4
   04	COM1 and COM3
.TE

Vector numbers not in the table are not used by this BSP.

The standard ISA Intel 8259 Programmable Interrupt Controllers (PICs) assert
their interrupts through the Raven MPIC as an external interrupt.  The external
interrupt vector numbers (MPIC vectors) are:

.TS C
center;
lf3 lf3
l lw(2.6i) .
.ne 6
.sp .5
Vector#	Assigned to
_
   10	PBC (8259)
   11	Falcon-ECC error
   12	PCI Ethernet
   13	Watchdog Timer Level 1
   14	Dec2155x
   15	CompactPCI Bus1 INTA#
   16	CompactPCI Bus1 INTB#
   17	CompactPCI Bus1 INTC#
   18	CompactPCI Bus1 INTD#
   19	PMC1 INTA#/PMC2 INTB#
   1a	PMC1 INTB#/PMC2 INTC#
   1b	PMC1 INTC#/PMC2 INTD#
   1c	PMC1 INTD#/PMC2 INTA#
.TE

Vector numbers not in the table are not used by this BSP.

The Raven Multi-Processor Interrupt Controller (MPIC) sets system interrupt
priorities and serves as controller of all external interrupts.  Each
of its 16 interrupt control registers, designated IRQ0 through IRQ15, can be
programmed with a relative priority from 15, the highest, to 0, the lowest.  A
priority of zero effectively disables the interrupt.  All but one of the 16
control registers has been hardwired to a particular interrupt source.  The IRQ
number and priority assignments are as follows:

.TS E
expand;
lf3 lf3 lf3
l l lw(2.6i) .
.ne 6
.sp .5
Raven MPIC IRQ	Priority	IRQ Source
_
IRQ0	8	PBC (8259)
IRQ1	0	Falcon ECC Error
IRQ2	14	Ethernet
IRQ3	0	Watchdog Timer Level 1
IRQ4	10	Dec2155x
IRQ5	0	CompactPCI Bus 1 INTA#
IRQ6	0	CompactPCI Bus 1 INTB#
IRQ7	0 	CompactPCI Bus 1 INTC#
IRQ8	0	CompactPCI Bus 1 INTD#
IRQ9	3	PMC1 INTA#/PMC2 INTB#
IRQ10	3	PMC1 INTB#/PMC2 INTC#
IRQ11	3	PMC1 INTC#/PMC2 INTD#
IRQ12	3	PMC1 INTD#/PMC2 INTA#
.TE

For further details, refer to the appropriate board's reference guide.

There are only four PCI bus interrupts: A, B, C, and D.  They are shared among
all PCI bus devices and do not have levels.  PCI bus interrupts are wired
directly to the MPIC and, therefore, have preassigned system vector numbers
and interrupt levels.  The MCPN750 default configuration disables these
interrupt sources at the MPIC by programming the MPIC relative priority as
zero for these interrupt sources (see "config.h").  In normal situations, 
the board plugged into the "CPU" or "system" slot (a board such as the 
MCP750) will field these interrupts.  Enabling these interrupts sources
on the MCPN750 is not recommended (see earlier section titled "Compact
PCI Backpanel Interrupts").  Nevertheless, if it is desired to enable
these interrupts for the MCPN750, "config.h" must be modified to program 
the interrupt level for these sources with a value between 1 and 15.  
The user then enables one or more PCI interrupts and connects vectored 
ISRs to the system by following these steps:

.IP "1)"
Identify the PCI interrupt letter(s) as required by the application.
Based on this, identify the associated system interrupt vector from
the following chart taken from the external (MPIC) interrupt table:

.TS C
center;
lf3 lf3
l lw(2.6i) .
.ne 6
.sp .5
Vector#	Assigned to
_
   19	PMC1 INTA#/PMC2 INTB#
   1a	PMC1 INTB#/PMC2 INTC#
   1b	PMC1 INTC#/PMC2 INTD#
   1c	PMC1 INTD#/PMC2 INTA#
.TE

For example, PMC slot 2, INTC# corresponds to vector #1a.  The interrupt
level (used in the call to intEnable()) is numerically equal to the 
interrupt vector number.

.IP "2)"
In the application code, perform intConnect() for
each vector and its associated ISR.
.IP "3)"
Perform IntEnable() for each identified system 
interrupt level.
.IP "4)"
When the application has finished, perform
IntDisable() for each identified level.

.SS "Serial Configuration"
The MCPN750 has four serial ports.  All are ISA bus devices (16550C 
compatible).  The console port is labelled COM1.  The other ports are
COM2, COM3, and COM4.  

By default, all serial ports are configured as asynchronous, 9600 baud, with
1 start bit, 8 data bits, 1 stop bit, no parity, and no hardware 
handshake.  Hardware handshake using RTS/CTS is a supported option on all ports.

The TMCPN710 transition module has two RJ-45 connectors for COM1 and COM2;
these are permanently configured as DTE.  COM3 and COM4 are routed 
to on-board headers J11 and J14.  For details, consult 
\f2TMCPN710 Transition Module Installation and Use\f1.

.SS "Network Configuration"
All boards have one Ethernet port which is 10baseT and 100baseTX
compatible.  

The MCPN750 uses an RJ45 (twisted pair)
jack and can be used with either 10baseT or 100baseTX.  The Ethernet driver
automatically senses and configures the port as 10baseT or 100baseTX.  The
Ethernet driver is compatible with DEC21040, DEC21140, and DEC21143 devices.

The Media Access Control (Ethernet) address for each port is obtained from a
serial ROM contained in the DEC21140 chip.  If the address is not found in
serial ROM, the driver attempts to read it from NVRAM at offset 0x202c.