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VxWorks下 Mcpn750的BSP源代码

.TS C
center;
lf3 s
r lw(3.2i) .
.ne 6
.sp .5
Upstream I/O or Memory 0 BAR:
Size:	T{
4MB
T}
Direction:	T{
Out-Bound (MCPN750 to cPCI)
T}
cPCI Adrs:	T{
CPCI_MSTR_MEM_BUS (0x80000000 by convention)
T}
Local PCI Adrs:	T{
Dynamic (assigned by MCPN750)
T}
Local CPU Adrs:	T{
Dynamic (based on local PCI adrs)
T}
Use:	T{
R/W access to host DRAM
T}
.TE

.TS C
center;
lf3 s
r lw(3.2i) .
.ne 6
.sp .5
Upstream Memory 1 BAR:
Size:	T{
32MB
T}
Direction:	T{
Out-Bound (MCPN750 to cPCI)
T}
cPCI Adrs:	T{
Base cPCI address of the host's dynamic PCI configuration area (0x02000000 for
the default MCP750 BSP)
T}
Local PCI Adrs:	T{
Dynamic (assigned by MCPN750)
T}
Local CPU Adrs:	T{
Dynamic (based on local PCI adrs)
T}
Use:	T{
R/W access to cPCI devices
T}
.TE

The remaining Dec2155x Base Address Registers are not used by the BSP and
are available for use by the application.

.SS "Dec2155x Address Translation:
Due to the dynamic nature of PCI address allocation, the locations of the
upstream Dec2155x windows move as devices are added to the MCPN750 PCI
bus. Since these windows map the cPCI space into the local MCPN750 PCI
and CPU address spaces, their positions determine where the cPCI
resources appear when viewed by the MCPN750 CPU and any MCPN750 resident
PCI devices. Likewise, the downstream windows move as cPCI devices are
added and removed. The downstream windows are used to map the on-board
PCI and DRAM resources into the cPCI address space for access by the host
and other cPCI devices.

To assist with address translation, two translation routines are
provided by this BSP:

.TS C
center;
rw20 lw(3.2i) .
sysLocalToBusAdrs()	T{
Translates a local CPU address to an equivalent cPCI or local PCI memory or
I/O address.
T}

sysBusToLocalAdrs()	T{
Translates a cPCI or local PCI memory or I/O space address to a local CPU
equivalent address.
T}
.TE

.HP 6
NOTE: The translations performed by sysLocalToBusAdrs() and 
sysBusToLocalAdrs() are not symmetrical if one of the endpoints is the Compact
PCI bus. sysLocalToBusAdrs() translates by locating a downstream window which
makes the local CPU address visible in the cPCI address space.
sysBusToLocalAdrs() performs a similar operation by locating an upstream window
which makes the cPCI address visible in the local CPU address space. Since the
two sets of windows map different areas of the local address space,
the translation is not reversible.

.SS "Accessing Dec2155x CSR Registers"
Due to dynamic PCI address allocation, the PCI address assigned to the
Dec2155x CSR area cannot be known until runtime. To determine the
assigned address, it is necessary to read the Secondary CSR memory
BAR (or the Secondary CSR I/O BAR if I/O space is to be used).

The following code fragment derives the CPU address of the Scratchpad 0
register using its PCI memory space address:

.CS
    UINT32 bar;

    /* get the contents of the secondary CSR memory BAR
       (see note below) */

    if (pciConfigInLong (0, DEC2155X_PCI_DEV_NUMBER, 0,
                         DEC2155X_CFG_SEC_CSR_MEM_BAR,
                         &bar) != OK)
        {
        return (ERROR);
        }

    /* calculate the local PCI address of the scratchpad 0
       register */

    bar += DEC2155X_CSR_SCRATCHPAD0;

    /* convert the result to the CPU equivalent address */

    if (sysBusToLocalAdrs (PCI_SPACE_MEM_PRI, (char *)bar,
                         (char **)&bar) != OK)
        {
        return (ERROR);
        }

    return (bar);
.CE

.HP 6
NOTE: Using the constant DEC2155X_PCI_DEV_NUMBER ensures that the
on-board Dec2155x is read. If a search of the local PCI bus had
been performed using the Dec2155x device ID, the returned Bus,
Device and Function numbers may have corresponded to a Dec2155x
part found on an installed PMC card.

.P
Once the local CPU address is known, the cPCI address can be derived by
adding the following code fragment before returning the result:

    if (sysLocalToBusAdrs (PCI_BACKPANEL_MEMORY_SPACE,
                           (char *)bar,
                           (char **)&bar) != OK)
        return (ERROR);
    else
        return (bar);
.CE

.SS "Internal Dec2155x Interrupt Sources"
At start-up, all Dec2155x interrupt sources are masked and cleared.
Before unmasking an interrupt, an application ISR service routine must be
attached to the appropriate Dec2155x interrupt vector using intConnect().
Multiple ISR service routines can be connected to each vector if required
by the application. Once the handler is attached, the interrupt can be
enabled and disabled by calling sysDec2155xIntEnable() or
sysDec2155xIntDisable() as required. Interrupt vector definitions for the
Dec2155x internal interrupt sources are defined in mcpx750.h.

Unique interrupt vectors are provided for each of the 16 bits in the
Dec2155x Secondary IRQ register. Bit 0 (LSB) corresponds to
DEC2155X_DOORBELL0_INT_VEC with the remaining bits mapped in sequence.
These doorbell interrupts can be used for host-to-MCPN750 or
MCPN750-to-MCPN750 event notification. The Dec2155x interrupt handler
clears these interrupts which simplifies the application ISR.

Individual interrupt vectors are also provided for Dec2155x Hot Swap
Power State and I2O in-bound list events. The Dec2155x interrupt handler
also clears these interrupts.

The 64 Upstream Memory 2 BAR Page Crossing interrupts are all presented
on a single interrupt vector and the application ISR is responsible for
clearing the bits serviced. Calls to sysDec2155xIntEnable() and
sysDec2155xIntDisable() enable or disable all 64 interrupts.

The Dec2155x interrupt handler provides a default service routine for all
unclaimed interrupt vectors, including the Upstream Memory 2 BAR Page
Crossing interrupt. The default routine reports the event and clears the
interrupt source.

.SS "Compact PCI Backpanel Interrupts"
The Dec2155x can generate cPCI backpanel interrupts using any of the bits
in the Primary IRQ register if they have been un-masked by the host. The
following code fragment generates a compact PCI backpanel interrupt by
setting bit 15 (MSB) of the Primary IRQ register:

    if (sysBusIntGen (DEC2155X_DOORBELL15_INT_LVL,
                      DEC2155X_DOORBELL15_INT_VEC) != OK)
        return (ERROR);

Note that the cPCI bus does not provide an interrupt vector to the host.
The vector number passed to sysBusIntGen() simply identifies which bit in
the register to set. It is the host's responsibility to locate the
interrupt source and clear the interrupt.

In-bound cPCI backpanel interrupts are routed directed to the MCPN750
Raven MPIC and can be enabled, disabled and handled by calling
sysIntEnable(), sysIntDisable() and intConnect() with the MPIC vector
number of the desired backpanel interrupt line.  By default, cPCI
backpanel interrupts are disabled for the MCPN750 in config.h.  It is
recommended that these interrupts be left disabled to prevent interaction
problems with the MCP750 and cPCI system operation.

.HP 6
NOTE: Great care must be exercised when cPCI backpanel interrupts are
being generated and received simultaneously. If the packpanel
interrupt line driven by the MCPN750 is also enabled for receiving
interrupts, the MCPN750 will be interrupted by its own backpanel
interrupt. This scenario causes complications because the backpanel
interrupts are configured as level sensitive and difficulties are
encountered in determining the party responsible for clearing the
interrupt source. In general, backpanel interrupt generation is
useful for signaling an event to the host, but in-bound packpanel
interrupts have limited usefulness.

.SS "Altering the Default Dec2155x Configuration:
Altering the Dec2155x configuration requires the careful consideration of
several items:

.IP
Dec2155x window sizes and alignment.
.IP
Dec2155x translation values.
.IP
The size and alignment of the host's dynamic PCI configuration area.
.IP
The size and alignment of the MCPN750's dynamic PCI configuration area.

.P
The Dec2155x window parameters are controlled by #defines in config.h. 
There are three defines associated with each window:

.TS C
center;
rw11 lw(4.0i) .
\&..._SIZE	T{
determines the size of the window in bytes and must be an
integral power of two. The minimum size for a PCI I/O
space window is 64 bytes. The minimum size for a PCI
memory space window is 4KB. To disable a window, set the
size to 0. Note that the Dec2155x will not allow the
Primary CSR and Downstream Memory 0 BAR to 0 to be
disabled. If the size of this window is set to zero, the
Dec2155x will default to a 4KB window.
T}

\f3NOTE:\f1	T{
If a window value is not a power of 2, or is below the minimum size, sysLib.c
will not compile.
T}
.TE

.TS C
center;
rw11 lw(4.0i) .
\&..._TYPE	T{
determines the type of the window and any placement
restrictions. For proper operation, the window must be
configured for placement anywhere in the 32-bit PCI
address space.
T}
.TE

.TS C
center;
rw11 lw(4.0i) .
\&..._TRANS	T{
determines the base address of the window on the target
PCI bus. It is important to remember that this is a local
PCI address (downstream window) or a cPCI address
(upstream window). The translation value chosen must be
an even multiple if the window size.
T}

\f3NOTE:\f1	T{
If the translation value is not a multiple of the window
size, sysLib.c will not build.
T}
.TE

The default window sizes can be reduced without altering the sizes of the
dynamic PCI configuration area. However, if the required values are
significantly reduced from the default values, reducing the size of the
dynamic PCI configuration area reduces the size of the MMU page tables at
the ratio of 128:1 (a 128KB reduction saves 1KB of MMU table space).

The size of the PCI memory space used for dynamic PCI configuration is
controlled by PCI_MSTR_MEMIO_LOCAL in config.h and the area's base address
is controlled by PCI_MSTR_MEMIO_BUS in mcpx750.h. By default, the companion
MCP750 BSP allocates a 32MB area aligned to a 32MB boundary for dynamic
PCI configuration. To access peer MCPN750 DRAM areas, an upstream window
must be opened which matches the size of the host's dynamic PCI
configuration area. For translation to work correctly, the host's
dynamic PCI configuration area must be aligned to a multiple of the
area's size and the corresponding Dec2155x upstream translation register
must contain the area's base cPCI address (not CPU address). Since this
BSP supports peer-to-peer access between MCPN750 DRAM areas, the default
dynamic PCI configuration area for the MCPN750 is 64MB aligned to a 32MB
boundary which satisfies these requirements.

In addition to the peer access window, sufficient space must also be
available for mapping the host DRAM upstream window and any space
required by MCPN750-resident PCI devices. A margin must also be allowed
for areas that are unusable due to window alignment requirements.

If the application does not require peer-to-peer MCPN750 DRAM access, the
large 32MB window used to contain the host's dynamic PCI configuration
area can be eliminated with a corresponding decrease in the required
MCPN750 dynamic PCI configuration area. If peer-to-peer doorbell
interrupts are still required, the doorbell interrupt registers of peer
MCPN750s may be accessed through an I/O window which has much smaller
CPU address space requirements. This would require re-configuring the
default BSP to access host DRAM through Upstream Memory 1 BAR and using
the Upstream I/O or Memory 0 BAR to access the peer MCPN750 doorbell
interrupt registers.

.SS "Shared Memory Support"

The MPCN750 supports shared memory backplane communication with
the MCP750 or CPV5000 as the Compact PCI host node.  The Wind River
documentation provides a great deal of information regarding shared
memory concepts.  The section below provides tutorial style information
regarding the setup of a shared memory system involving the MCPN750 and
either a MCP750 or a CPV5000.

Setting up a working shared memory system involves proper setting of
certain "config.h" parameters and proper setting of boot parameters
via the "c" command from the boot prompt.  There are three components
involved in shared memory communication which must be configured
properly to create a working system:

.IP "Anchor:"
This is an area of memory which must be accessible to all nodes
participating in shared memory backplane communication.  The anchor
points to the actual shared memory buffer pool which must be located
in the same memory space as the anchor itself.  The associated
"config.h" parameter is SM_ANCHOR_ADRS.  In certain configurations,
nonzero nodes will "poll" for the location of the anchor.  "config.h"
defines which comes into play for polling are SM_OFF_BOARD and
SYS_SM_SYSTEM_MEM_POLL.

.IP "Master node:"
This node is always designated as node zero.  It is the node which
sets up the anchor and shared memory pool.  Once the anchor and shared
memory pool is set up, the master node acts as a peer with the other
nodes.  The node number (0 in this case) is one of the boot parameters
which can be set up with the "c" command from the bootline prompt.

.IP "Sequential addressing:"
This is is governed by a "config.h" parameter, INCLUDE_SM_SEQ_ADDR and is
used when sequential IP addresses are assigned to the participating
nodes.  Node zero is assigned the lowest IP address, followed by nodes
1, 2 etc. which are assigned the subsequent and sequential IP addresses.
The advantage of sequential addressing is that fewer boot parameters
must be specified to configure the system.
.LP

The following restrictions apply to shared memory configurations.

.IP "1)"
Node zero must not boot over the shared memory interface.  Only
nonzero nodes are allowed to boot over the shared memory "sm"
interface.

.IP "2)"
The location of the anchor must be statically determinable by the
master node (node 0).  That is, the location of the anchor must