target.nr

VxWorks下 Mcpn750的BSP源代码

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.\" PowerPlus/target.nr - Motorola MCPN750 target-specific documentation
.\"
.\" Copyright 1984-1999 Wind River Systems, Inc.
.\" Copyright 1996,1997,1998,1999 Motorola, Inc., All Rights Reserved
.\"
.\" modification history
.\" --------------------
.\" 01v,04dec01,mil  Changed USB ports to supported and added USB information.
.\" 01u,09oct01,mil  Added dec SROM fix in known problems (SPR 28677).
.\"                  Also fixed refgen errors on missing \\te.
.\" 01t,27aug01,dgp  change manual page to reference entry per SPR 23698
.\" 01s,13may99,srr  Changed documentation of PCI AutoConfiguration using
.\"                  PCI_MSTR_MEM_LOCAL to PCI_MSTR_MEMIO_LOCAL.
.\" 01r,15apr99,srr  Changed to WRS address space naming convention.
.\" 01q,09Apr99,srr  Add CPV5000 as supported host node for shared memory.
.\" 01p,08feb99,scb  Writeup on MPCI spurious interrupts.
.\" 01o,08feb99,scb  Clarification in "Make Targets" section.
.\" 01n,28jan99,scb  Writeup on SENS support.
.\" 01m,01dec98,scb  One-line tweek about SM_ANCHOR_OFFSET value.
.\" 01l,23nov98,scb  Reentered info about unified sysBusToLocalAdrs() and 
.\"                  sysLocalToBusAdrs() and PCI address space designations 
.\"                  in pci.h (inadvertently dropped).
.\" 01k,23nov98,scb  Emphasized caveat associated with PCI backpanel interrupts.
.\" 01j,23nov98,scb  Fix minor documentation error in building of "boot.bin".
.\" 01i,19nov98,scb  Added "PCI autoconfiguration roll call" information.
.\" 01h,19nov98,scb  Cleaned out old MCP750 related information.
.\" 01g,17nov98,scb  Added section: "Booting the MCPN750".
.\" 01f,16nov98,scb  Added Shared Memory Support information.
.\" 01e,05nov98,rhv  Added Dec2155x Information.
.\" 01d,21sep98,rhv  Added VPD information.
.\" 01c,08sep98,rhv  Added warning about VIA PCI-to-ISA bridge causing
.\"                  interference with PCI Bus probing under Known Problems
.\"                  section.
.\" 01b,28aug98,rhv  Added Processor Data Bus Parity configuration instructions.
.\" 01a,26aug98,srr  created from mcp750 target.nr (revision 01t).
.\"
.\"
.TH "MCPN750" T "Motorola PowerPlus" "Rev: 13 May 99" "VXWORKS REFERENCE MANUAL"

.SH "NAME"
.aX "Motorola MCPN750"

.SH "INTRODUCTION"
This reference entry provides board-specific information necessary to run
VxWorks.  Before using a board with VxWorks, verify that the board runs in the
factory configuration by using vendor-supplied ROMs and jumper settings and
checking the RS-232 connection.

The Motorola CompactPCI series of boards includes the following families: 
MCP750 and MCPN750.  This BSP encompasses MCPN750 only.

The MCPN750 single-board computer is based on the PowerPC MPC750 (Arthur)
microprocessors.  The series part numbers are of the form:

    MCPN750-nnnn

    where
        nnnn = Processor speed and ECC DRAM size (DRAM contained on-board)
            1222 = 266 MHz w/16MB
            1232 = 266 MHz w/32MB
            1332 = 366 MHz w/32MB
            1342 = 366 MHz w/64MB
            1352 = 366 MHz w/128MB
            1362 = 366 MHz w/256MB

The MCPN750 transition module designation is TMCPN710.  The transition
module contains two RJ45 connectors
providing access to the asynchronous serial ports permanently configured as 
EIA DTE, and two HD-26 connectors providing access to two serial ports (COM3 
and COM4).
For more information refer to the Motorola manual 
\f2"TMCPN710 Transition Module Installation and Use"\f1.


The BAT registers are not supported in the current cache management strategy;
therefore, they can best be used for non-cacheable, data-only address regions.

.SS "Boot ROMS"
The MCPN750 boards have two sets of flash EEPROM (FLASH).  One set of two AMD
Am29F040 FLASH is socketed (sockets XU1 and XU2) and contains Motorola's
PPC1-Bug.  The other set of E28f800 FLASH is soldered in.  The VxWorks boot
kernel resides in the soldered FLASH.  See \f2Hardware Details: ROM
Considerations\f1 for information about loading and writing the boot kernel
image to the soldered FLASH.

These boards have non-volatile RAM; thus, boot parameters are preserved
whenever the system is powered off.

To load VxWorks, and for more information, follow the instructions in the
\f2Tornado User's Guide: Getting Started.\f1

.SS "Jumpers"
The following jumpers are relevant to VxWorks configuration: 

.TS E
expand;
cf3 s s
lf3 lf3 lf3
l l lw(2.6i) .
.ne 6
MCPN750
.sp .5
Jumper	Function	Description
_
J7	ROM controller	T{
Install the jumper across pins 2 and 3 to select the socketed FLASH.
Install the jumper across pins 1 and 2 to select the soldered FLASH
(factory configuration).
T}
.TE

For details of jumper configuration, see the board diagram at the end of
this entry and in the hardware manual.

Note that ROM controller jumpers should be set to select socketed FLASH until
VxWorks boot code is written to soldered FLASH, after which the jumpers should
be restored to the factory configuration of soldered FLASH.

.SH "FEATURES"
The following subsections list all supported and unsupported features, as well
as any feature interaction.

.SS "Supported Features"
The following features of the MCPN750 are supported:

.TS E
expand;
lf3 lf3
lw13 lw(3.7i) .
.ne 6
.sp .5
Feature	Description
_
Processors	T{
MPC750; 66MHz bus clock
T}
L2 Cache	T{
1MB in-line cache, write-through only.
T}
FLASH	T{
4MB soldered (64-bit wide), 1MB socketed 
(16-bit wide).  Soldered used for VxWorks boot image.
T}
DRAM	T{
16, 32, 64, 128MB, two-way interleaved; auto-sized or fixed
T}
NVRAM	T{
8KB (MK48T59/559)
8KB
T}
Peripherals	T{
Four 16550C asynchronous serial ports COM1, COM2, COM3, and COM4;
AUI or 10baseT/100baseTX Ethernet interface;
Primary ATA/EIDE port and Compact Flash;
USB ports 1 and 2
T}
ISA Interface	T{
full 64KB memory and I/O space
T}
PCI Interface	T{
32-bit address, 32-bit data; complies with \f2PCI Local Bus Specification\f1,
Revision 2.1
T}
Miscellaneous	T{
RESET switch
T}
.TE

.SS "Booting the MCPN750"

When running with an MCP750 in the same chassis, a reset performed on
the MCP750 will automatically reset all MCPN750s in the same chassis.
Also, it generally makes no sense to reset (using the reset button) a
single MCPN750 in a chassis without resetting the MCP750 as well.  The
MCP750 PCI autoconfiguration (see below) only enumerates and
initializes the PCI bus during MCP750 initialization.  Part of this
PCI bus initialization involves the MCP750's programming of the
MCPN750's Dec2155x downstream BARs.  Thus a single MCPN750 which is
reset via the reset button press without rebooting the the MCP750 will
not be visible to the MCP750 and will be unable to partake in
interrupt handshaking or shared memory support.  Note that performing
a ctrl-x type reboot on the MCPN750 (as opposed to a reset button
press) will not destroy the programming in the downstream BAR and the
MCPN750 will still be visible to the MCP750 and will be able to
partake in interrupt handshaking etc.

.SS "PCI Autoconfiguration"

The board support package for the MCPN750 handles automatic
detection and configuration of compact PCI devices.  In
particular, it performs the following:

.IP "1)"
Probes the host PCI bridge for all devices on the host
PCI bus (bus zero).  Note that among the devices on bus
zero might be PCI-PCI bridges.  These bridges are probed
as well and recursive probing occurs until all devices
and bridges are found. 

.IP "2)"
Memory is assigned to each device and sub-bridge found.
For devices, each Base Address Register (BAR) is queried.
Memory or I/O space (or both) is allocated for each BAR
which has been implemented.

.IP "3)"
Complete initialization of the devices is performed,
including cache Line size, command register, latency timer,
interrupt line and base address registers (0 through 5).
PCI-PCI bridges are initialized with the correct primary
bus, secondary bus and subordinate bus designation.  In
short, the entire bridge/device "tree" rooted at the host
pci bridge is completely configured and ready for driver
access.

.SS "PCI Autoconfiguration Roll Call"

A new feature to the PCI autoconfiguration is "roll call".  If you
expect to find a certain number of specific devices identified by
device/vendor ID during PCI autoconfiguration you can enter the
information into a roll call list.  For example assume that you
know that the autoconfiguration process should find 4 different
devices with device/vendor ID of 0x00461011 (this would be the
Dec2155x device).  You want PCI autoconfiguration to "wait" until
it finds at least this many but you don't want it to wait more
than 20 seconds.  If 20 seconds have elapsed and 4 different
Dec2155x chips have not appeared in the bus enumeration process,
you would like the PCI autoconfiguration process to proceed
anyway.

You would construct the "roll call" list in "config.h" as shown
below:

#define ROLL_CALL_MAX_DURATION 20  

#define PCI_ROLL_CALL_LIST_ENTRIES \
{ 4, 0x00461011 },


The parameter ROLL_CALL_MAX_DURATION specifies that no more than 20
seconds should elapse before proceeding on with the
autoconfiguration, even though less than 4 Dec2155x devices have
been found.

You can see the entry { 4, 0x00461011 } which says that you expect
to find at least 4 devices whose device/vendor ID is 0x00461011.
Note that "mcpx750.h" contains defines for some device/vendor IDs,
such a define could be used here instead of a hard-coded
device/vendor ID.

Also note that this list can be extended so more than one device/
vendor ID is identified with possibly a different count.

If the list is empty (except for the termination entry) then there
is no roll call waiting performed, regardless of the setting of
ROLL_CALL_MAX_DURATION (seconds).

The roll call feature can be useful for devices which are slow to
appear on the cPCI bus.  For example, MCPN750 CPU boards (which
contain the Dec2155x nontransparent PCI bridge) will not be
visible to an MCP750 master which is enumerating the bus until the
MCPN750 clears the "primary access lock-out" bit in the Dec2155x chip
control 0 register.  If the MCP750's bus enumeration occurs
before the MCPN750 software unlocks the Dec2155x, then the MCP750
will not know the MCPN750 is present and will not configure it.
The roll call feature allows for bus enumeration polling until the
specified devices actually appear.  Note that roll call may not
always be required for the example just presented.  Some system
configurations and timings may work without using the roll call
feature.  

.SS "Dec2155x PCI-to-PCI Non-Transparent Bridge Support"
This BSP contains support for the Dec2155x non-transparent PCI-to-PCI
bridge. This device provides read/write access to and from the Compact
PCI bus (cPCI).

The following support is provided:
.IP
Up to 4 user configurable downstream cPCI to local PCI windows.
.IP
Up to 2 user configurable upstream local PCI to cPCI windows.
.IP
Support for in-bound "doorbell" interrupts.
.IP
Support for cPCI backpanel interrupts.
.IP
cPCI to local CPU address translation.
.IP
Local CPU to cPCI address translation.
.IP
Build-time validation of Dec2155x configuration parameters.

.SS "Dec2155x Support Limitations"
The PReP standard does not support 64-bit PCI addressing. Therefore, this
BSP does not provide support for 64-bit addressing through the Dec2155x.

There is a limitation when the cPCI to local PCI or cPCI to local CPU
address translation routines are presented with a cPCI address which maps
into a downstream window on the local board. The translation will succeed
and return an address, but when that address is accessed, the Dec2155x
will attempt to access one of its own downstream windows. The transfer
will fail because PCI devices cannot access themselves on the cPCI bus.
Depending on how error detection is configured, the result will be
invalid data or a PCI Master Abort.

Interrupt vectors are provided for the interrupts associated with
Dec2155x Hot Swap Power State transitions, Intelligent I/O (I2O), and the
Upstream Memory 2 Base Address Register but no other support for these
features is provided.

During system startup, the Dec2155x must be configured and unlocked
before the host enumerates the cPCI bus. To meet this timing requirement,
the Dec2155x is configured by the vxWorks boot ROM image. If changes to
the Dec2155x configuration are made, new boot ROMs are required in
addition to a new kernel. For proper operation, the Dec2155x
configuration in the Boot ROMs must match the configuration used by the
kernel.

The Dec2155x places certain limitations on window sizes and translation
values. This BSP adheres to those limitations and provides
build-time parameter checking to help avoid misconfigurations.
Modifications to the default Dec2155x configuration provided in this BSP
must be made with care to avoid invalid configurations. Information on
the default Dec2155x configuration provided by this BSP is presented in
the next section and modification guidelines appear later in this file.

.SS "Dec2155x Default Configuration"
The default Dec2155x configuration supports a host processor (MCP750) and
up to 7 MCPN750s. The following interoperability is supported:

.IP
Host access to MCPN750 CSR and the low 4MB of MCPN750 DRAM.
.IP
MCPN750 access to the low 4MB of host DRAM.
.IP
MCPN750 access to peer MCPN750 CSR and low 4MB of peer MCPN750 DRAM.

.P
The BSP provides these features using the following Dec2155x
configuration:

.TS C
center;
lf3 s
r lw(3.2i) .
.ne 6
.sp .5
Primary CSR and Downstream Memory 0 BAR:
Size:	T{
4MB
T}
Direction:	T{
In-Bound (cPCI to MCPN750)
T}
cPCI Adrs:	T{
Dynamic (assigned by host)
T}
Local PCI Adrs:	T{
PCI_SLV_MEM_BUS (0x80000000 by convention)
T}
Local CPU Adrs:	T{
PCI_SLV_MEM_LOCAL (0x00000000 by convention)
T}
Use:	T{
R/W access to CSR (low 4KB) and MCPN750 DRAM (above 4KB)
T}
.TE