dec2155xcpci.c

VxWorks下 Mcpn750的BSP源代码

#endif

#ifndef DEC2155X_CFG_WR_LONG
#   define DEC2155X_CFG_WR_LONG(offset, result) \
           pciConfigOutLong (0, DEC2155X_PCI_DEV_NUMBER, 0, (offset), \
                             (UINT32)(result))
#endif

#ifndef DEC2155X_CFG_WR_WORD  
#   define DEC2155X_CFG_WR_WORD(offset, result) \
           pciConfigOutWord (0, DEC2155X_PCI_DEV_NUMBER, 0, (offset), \
                             (UINT16)(result))
#endif

#ifndef DEC2155X_CFG_WR_BYTE
#   define DEC2155X_CFG_WR_BYTE(offset, result) \
           pciConfigOutByte (0, DEC2155X_PCI_DEV_NUMBER, 0, (offset), \
                             (UINT8)(result))
#endif

#ifndef DEC2155X_CFG_INSERT_LONG
#   define DEC2155X_CFG_INSERT_LONG(offset, mask, data) \
           pciConfigModifyLong (0, DEC2155X_PCI_DEV_NUMBER, 0, (offset), \
                                (mask), (data))
#endif
#ifndef DEC2155X_CFG_INSERT_WORD
#   define DEC2155X_CFG_INSERT_WORD(offset, mask, data) \
           pciConfigModifyWord (0, DEC2155X_PCI_DEV_NUMBER, 0, (offset), \
                                (mask), (data))
#endif
#ifndef DEC2155X_CFG_INSERT_BYTE
#   define DEC2155X_CFG_INSERT_BYTE(offset, mask, data) \
           pciConfigModifyByte (0, DEC2155X_PCI_DEV_NUMBER, 0, (offset), \
	                        (mask), (data))
#endif
#ifndef DEC2155X_PCI_INSERT_LONG
#   define DEC2155X_PCI_INSERT_LONG(offset, mask, data) \
           PCI_INSERT_LONG(DEC2155X_CSR_ADRS(offset), (mask), (data))
#endif

#ifndef DEC2155X_PCI_INSERT_WORD
#   define DEC2155X_PCI_INSERT_WORD(offset, mask, data) \
           PCI_INSERT_WORD(DEC2155X_CSR_ADRS(offset), (mask), (data))
#endif

#ifndef DEC2155X_PCI_INSERT_BYTE
#   define DEC2155X_PCI_INSERT_BYTE(offset, mask, data) \
           PCI_INSERT_BYTE(DEC2155X_CSR_ADRS(offset), (mask), (data))
#endif

/*******************************************************************************
*
* sysDec2155xInit - initialize registers of the Dec2155x (Drawbridge) chip
*
* This routine initializes registers of the DEC 2155x PCI-to-PCI bridge and maps
* access to the Compact PCI bus.
*
* RETURNS: OK on success, else ERROR (Dec2155x not in correct state).
*/

STATUS sysDec2155xInit (void)
    {
    UINT16 priLockOut;
    UINT16 mstrEn;

    /* configure the primary and secondary SERR disables */

    DEC2155X_CFG_INSERT_BYTE(DEC2155X_CFG_PRI_SERR_DISABLES,
                             (UINT8)~DEC2155X_SERR_RSV_MSK,
                             DEC2155X_PRI_SERR_VAL);
    DEC2155X_CFG_INSERT_BYTE(DEC2155X_CFG_SEC_SERR_DISABLES,
                             (UINT8)~DEC2155X_SERR_RSV_MSK,
                             DEC2155X_SEC_SERR_VAL);

    /* configure downstream translation base registers */

    DEC2155X_CFG_INSERT_LONG(DEC2155X_CFG_DS_MEM0_TB,
                             ~DEC2155X_MEM_TB_RSV_MSK,
                             DEC2155X_CSR_AND_DS_MEM0_TRANS);

    DEC2155X_CFG_INSERT_LONG(DEC2155X_CFG_DS_IO_OR_MEM1_TB,
                             ~DEC2155X_IO_OR_MEM_TB_RSV_MSK,
                             DEC2155X_DS_IO_OR_MEM1_TRANS);

    DEC2155X_CFG_INSERT_LONG(DEC2155X_CFG_DS_MEM2_TB,
                             ~DEC2155X_MEM_TB_RSV_MSK,
                             DEC2155X_DS_MEM2_TRANS);

    DEC2155X_CFG_INSERT_LONG(DEC2155X_CFG_DS_MEM3_TB,
                             ~DEC2155X_MEM_TB_RSV_MSK,
                             DEC2155X_DS_MEM3_TRANS);

    /* configure upstream translation base values */

    DEC2155X_CFG_INSERT_LONG(DEC2155X_CFG_US_IO_OR_MEM0_TB,
                             ~DEC2155X_IO_OR_MEM_TB_RSV_MSK,
                             DEC2155X_US_IO_OR_MEM0_TRANS);

    DEC2155X_CFG_INSERT_LONG(DEC2155X_CFG_US_MEM1_TB,
                             ~DEC2155X_MEM_TB_RSV_MSK,
                             DEC2155X_US_MEM1_TRANS);

    /* configure the dec2155x backpanel PCI interrupt routing */

    sysOutByte (DEC2155X_HW_INT_ROUTING_ADRS, DEC2155X_CPCI_HW_INT_ROUTING_VAL);

    /* get current state of Primary Lock-out and Master Enable bits */

    DEC2155X_CFG_RD_WORD(DEC2155X_CFG_CHP_CTRL0, &priLockOut);
    priLockOut &= DEC2155X_CC0_PRI_ACCESS_LKOUT;

    DEC2155X_CFG_RD_WORD(PCI_CFG_COMMAND, &mstrEn);
    mstrEn &= PCI_CMD_MASTER_ENABLE;

    /* verify ROM boot phase */

    if (!mstrEn)
        {

        /* in ROM boot phase, OK to continue */

#ifdef DEC2155X_SETUP_FROM_SROM

       /*
        * primary lock-out bit should not be set if ROM contents are OK.
        * if primary lock-out bit is set, indicate error.
        */

       if (priLockOut)
           sysDec2155xInitFail = TRUE;

#else /* !DEC2155X_SETUP_FROM_SROM */
       
       /*
        * primary lock-out bit should be set if ROM contents are OK.
        * if primary lock-out bit is not set, indicate error.
        */

       if (!priLockOut)

           sysDec2155xInitFail = TRUE;

       else
            {

            /* configure primary class register */

            DEC2155X_CFG_WR_BYTE((PCI_CFG_PROGRAMMING_IF +
                                 DEC2155X_PRI_FROM_SEC_OFFSET),
                                 DEC2155X_PRI_PRG_IF_VAL);
            DEC2155X_CFG_WR_BYTE((PCI_CFG_SUBCLASS +
                                 DEC2155X_PRI_FROM_SEC_OFFSET),
                                 DEC2155X_PRI_SUBCLASS_VAL);
            DEC2155X_CFG_WR_BYTE((PCI_CFG_CLASS +
                                 DEC2155X_PRI_FROM_SEC_OFFSET),
                                 DEC2155X_PRI_CLASS_VAL);

            /* configure bist register (shared) */

            DEC2155X_CFG_INSERT_BYTE(PCI_CFG_BIST, ~DEC2155X_BIST_RSV,
                                     DEC2155X_BIST_VAL);
            
            /* configure the downstream windows */

            DEC2155X_CFG_INSERT_LONG(DEC2155X_CFG_DS_MEM0_SETUP,
                                     ~DEC2155X_MEM_SETUP_RSV_MSK,
                                     DEC2155X_CSR_AND_DS_MEM0_SETUP);

            DEC2155X_CFG_INSERT_LONG(DEC2155X_CFG_DS_IO_OR_MEM1_SETUP,
                                     ~DEC2155X_IO_OR_MEM_SETUP_RSV_MSK,
                                     DEC2155X_DS_IO_OR_MEM1_SETUP);

            DEC2155X_CFG_INSERT_LONG(DEC2155X_CFG_DS_MEM2_SETUP,
                                     ~DEC2155X_MEM_SETUP_RSV_MSK,
                                     DEC2155X_DS_MEM2_SETUP);

            DEC2155X_CFG_INSERT_LONG(DEC2155X_CFG_DS_MEM3_SETUP,
                                     ~DEC2155X_MEM_SETUP_RSV_MSK,
                                     DEC2155X_DS_MEM3_SETUP);

            DEC2155X_CFG_INSERT_LONG(DEC2155X_CFG_UPR32_BITS_DS_MEM3_SU,
                                     ~DEC2155X_MEM_SETUP_RSV_MSK,
                                     DEC2155X_UPR32_DS_MEM3_SETUP);

            /* configure subsystem and vendor id (shared) */

            DEC2155X_CFG_WR_WORD(PCI_CFG_SUB_VENDER_ID,
                                 DEC2155X_SUB_VNDR_ID_VAL);
            DEC2155X_CFG_WR_WORD(PCI_CFG_SUB_SYSTEM_ID,
                                 DEC2155X_SUB_SYS_ID_VAL);

            /* configure the primary max latency and minimum grant registers */

            DEC2155X_CFG_WR_BYTE(PCI_CFG_MAX_LATENCY + 
                                 DEC2155X_PRI_FROM_SEC_OFFSET,
                                 DEC2155X_MAX_LAT_VAL);

            DEC2155X_CFG_WR_BYTE(PCI_CFG_MIN_GRANT +
                                 DEC2155X_PRI_FROM_SEC_OFFSET,
                                 DEC2155X_MIN_GNT_VAL);

            /* configure chip ctrl 0 without altering primary lock-out */

            DEC2155X_CFG_INSERT_WORD(DEC2155X_CFG_CHP_CTRL0,
                                     ~DEC2155X_CC0_PRI_ACCESS_LKOUT,
                                     DEC2155X_CHP_CTRL0_VAL);

            /* configure chip control 1 */

            DEC2155X_CFG_WR_WORD(DEC2155X_CFG_CHP_CTRL1,
                                 DEC2155X_CHP_CTRL1_VAL);

            /*
             * set secondary master access enable so we're ready when the host
             * sets the I/O and/or Memory access enables on the primary side
             */

            DEC2155X_CFG_INSERT_WORD(PCI_CFG_COMMAND, PCI_CMD_MASTER_ENABLE,
                                     PCI_CMD_MASTER_ENABLE);

            /* allow host access from the primary side */

            DEC2155X_CFG_INSERT_WORD(DEC2155X_CFG_CHP_CTRL0,
                                     DEC2155X_CC0_PRI_ACCESS_LKOUT,
                                     DEC2155X_CHP_CTRL0_VAL);

            /* configure secondary class register */

            DEC2155X_CFG_WR_BYTE(PCI_CFG_PROGRAMMING_IF,
                                  DEC2155X_SEC_PRG_IF_VAL);
            DEC2155X_CFG_WR_BYTE(PCI_CFG_SUBCLASS,
                                 DEC2155X_SEC_SUBCLASS_VAL);
            DEC2155X_CFG_WR_BYTE(PCI_CFG_CLASS,
                                 DEC2155X_SEC_CLASS_VAL);

            /* configure upstream windows */

            DEC2155X_CFG_INSERT_LONG(DEC2155X_CFG_US_IO_OR_MEM0_SETUP,
                                     ~DEC2155X_IO_OR_MEM_SETUP_RSV_MSK,
                                     DEC2155X_US_IO_OR_MEM0_SETUP);

            DEC2155X_CFG_INSERT_LONG(DEC2155X_CFG_US_MEM1_SETUP,
                                     ~DEC2155X_MEM_SETUP_RSV_MSK,
                                     DEC2155X_US_MEM1_SETUP);

            /* configure secondary max latency and minimum grant */

            DEC2155X_CFG_WR_BYTE(PCI_CFG_MAX_LATENCY, DEC2155X_MAX_LAT_VAL);
            DEC2155X_CFG_WR_BYTE(PCI_CFG_MIN_GRANT, DEC2155X_MIN_GNT_VAL);

            }

#endif /* DEC2155X_SETUP_FROM_SROM */
        }

    /* return status based on error flag */

    if (sysDec2155xInitFail)
        return (ERROR);
    else
        return (OK);

    }

/*******************************************************************************
*
* sysDec2155xInit2 - perform phase 2 Dec2155x initialization
*
* This routine performs the initialization that must be performed after PCI
* auto-configuration.
*
* RETURNS: N/A
*/

void sysDec2155xInit2 (void)
    {
    UINT8  intLine;

    /* read the Dec2155x CSR Memory BAR, convert to CPU view and save */

    DEC2155X_CFG_RD_LONG(DEC2155X_CFG_SEC_CSR_MEM_BAR, &sysDec2155xCsrAdrs);

    sysDec2155xCsrAdrs = (sysDec2155xCsrAdrs & PCI_MEMBASE_MASK) + 
                          PCI_MSTR_MEMIO_LOCAL;

    /* disable and clear all in-bound doorbell interrupts. */

    sysPciOutWord (DEC2155X_CSR_ADRS(DEC2155X_CSR_SEC_SET_IRQ_MSK),
                   (UINT16)(0xffff));
    sysPciOutWord (DEC2155X_CSR_ADRS(DEC2155X_CSR_SEC_CLR_IRQ),
                   (UINT16)(0xffff));

    /* disable and clear power state interrupt. */

    sysPciOutWord (DEC2155X_CSR_ADRS(DEC2155X_CSR_CHP_SET_IRQ_MSK),
                   DEC2155X_CHPCSR_PM_D0);
    sysPciOutWord (DEC2155X_CSR_ADRS(DEC2155X_CSR_CHP_STS_CSR),
                   DEC2155X_CHPCSR_PM_D0);

    /* disable I2O in-bound list empty interrupt. */

    DEC2155X_PCI_INSERT_LONG(DEC2155X_CSR_I2O_IBND_PST_LST_MSK,
                             DEC2155X_I2O_PST_LST_MSK,
                             DEC2155X_I2O_PST_LST_MSK);

    /* disable and clear Upstream memory 2 page crossing interrupts. */

    sysPciOutLong (DEC2155X_CSR_ADRS(DEC2155X_CSR_US_PG_BND_IRQ_MSK0),
                   (UINT32)(0xffffffff));
    sysPciOutLong (DEC2155X_CSR_ADRS(DEC2155X_CSR_US_PG_BND_IRQ_MSK1),
                   (UINT32)(0xffffffff));
    sysPciOutLong (DEC2155X_CSR_ADRS(DEC2155X_CSR_US_PG_BND_IRQ0),
                   (UINT32)(0xffffffff));
    sysPciOutLong (DEC2155X_CSR_ADRS(DEC2155X_CSR_US_PG_BND_IRQ1),
                   (UINT32)(0xffffffff));

    /* connect the Dec2155X interrupt handler to the proper MPIC interrupt */

    DEC2155X_CFG_RD_BYTE(PCI_CFG_DEV_INT_LINE, &intLine);

    intLine += EXT_INTERRUPT_BASE;

    intConnect (INUM_TO_IVEC((UINT32)intLine), sysDec2155xIntr, 0);

    intEnable (intLine);

    }

/*******************************************************************************
*
* sysIntDisable - disable a bus interrupt level (vector)
*
* This routine disables reception of a specified Compact PCI interrupt level.
*
* Since Compact PCI interrupts are routed directly to the interrupt controller,
* this function simply passes the caller's parameter through to the standard
* intDisable function (which will eventually end up at the interrupt
* controller's intDisable function).
*
* RETURNS: The results of intDisable.
*
* SEE ALSO: sysIntEnable()
*/

STATUS sysIntDisable
    (
    int intLevel        /* interrupt level (vector) */
    )
    {
    return (intDisable (intLevel) );
    }

/*******************************************************************************
*
* sysIntEnable - enable a Compact PCI bus interrupt level (vector)
*
* This routine enables reception of a specified Compact PCI interrupt level.
*
* Since Compact PCI interrupts are routed directly to the interrupt controller,
* this function simply passes the caller's parameter through to the standard
* intEnable function (which will eventually end up at the interrupt controller's
* intEnable function).
*
* RETURNS: The results of intEnable.
*
* SEE ALSO: sysIntDisable()
*/

STATUS sysIntEnable
    (
    int intLevel        /* interrupt level (vector) */
    )
    {
    return (intEnable (intLevel) );
    }

/*******************************************************************************
*
* sysBusIntAck - acknowledge a bus interrupt
*
* This routine acknowledges a specified Compact PCI bus interrupt level.
*
* NOTE: This routine is included for BSP compliance only.  Since Compact
* PCI bus interrupts are routed directly to the interrupt controller, interrupts
* are re-enabled in the interrupt controller's handler and this routine is a
* no-op.
*
* RETURNS: NULL.
*
* SEE ALSO: sysBusIntGen()
*/

int sysBusIntAck
    (
    int intLevel        /* interrupt level to acknowledge */
    )
    {
    return (0);
    }

/*******************************************************************************
*
* sysBusIntGen - generate a bus interrupt
*
* This routine generates a Compact PCI backpanel interrupt by setting one of
* the 16 bits in the 2155x Primary Set IRQ register. The bit is set regardless
* of the current state of the bit and whether the interrupt has been enabled by
* the host processor. Because the Compact PCI bus does not have interrupt
* levels or vectors, the caller's interrupt level parameter is ignored and the
* caller's vector number is used to select the bit to set in the Primary Set IRQ
* Register. The symbol DEC2155X_DOORBELL0_INT_VEC corresponds to bit 0 (LSB)
* and the remaining bits are mapped in sequence.
*
* RETURNS: OK, or ERROR if <vector> is out of range.
*
* SEE ALSO: sysBusIntAck()
*/

STATUS sysBusIntGen
    (
    int level,          /* interrupt level to generate (not used) */
    int vector          /* interrupt vector for interrupt */
    )
    {
    int bit;

    /* make sure the interrupt vector is valid */

    if ( (vector > DEC2155X_DOORBELL15_INT_VEC) ||
         (vector < DEC2155X_DOORBELL0_INT_VEC) )
        return (ERROR);