syslib.c

VxWorkS下 MV2604的BSP源代码

    return (state);

    }


/*******************************************************************************
*
* sysVmeRmwTas - test and set a location across the VMEbus utilizing RMW
*
* This routine performs a test-and-set (TAS) instruction on the specified
* address.  To prevent deadlocks, interrupts are disabled and the VMEbus is
* locked during the test-and-set operation.
*
* NOTE: Although the address passed-in to sysBusTas() is defined as
*	"char *", vxTas() operates on the address as a "void *".
*	For PowerPC, this implies that the location tested-and-set is
*	actually a 32-bit entity.
* 
* RETURNS: TRUE if the value had not been set but is now
*          FALSE if the VMEbus cannot be locked or the value was already set.
*
* SEE ALSO: vxTas()
*/

LOCAL BOOL sysVmeRmwTas
    (
    char * adrs          /* address to be tested and set */
    )
    {
    BOOL state = FALSE;  /* semaphore state */
    int  lockKey;        /* interrupt lock key */

    /* A board with the UNIVERSE_II can generate a VMEbus RMW */

    /*
     * Lock interrupts so that setting up SCG and issuing RMW
     * are atomic
     */

    lockKey = intLock ();

    /* Enable RMW cycle */

    sysBusRmwEnable(VME_SCG_COMPARE_MASK,
		    VME_SCG_COMPARE_TO_SET,
		    VME_SCG_SWAP_TO_SET,
		    (char *)adrs);

    /* perform RMW to try and set TAS location */

    state = *((UINT *)adrs);
    EIEIO_SYNC;

    /* Disable RMW cycle */

    sysBusRmwDisable();

    /* unlock the interrupt */

    intUnlock (lockKey);

    /* return TAS test result */

    if (state)
        {
	return (FALSE);
	}
    else
        {
        return (TRUE);
        }
    }


/******************************************************************************
*
* sysLanIntEnable - enable the LAN interrupt
*
* This routine enables interrupts at a specified level for the on-board LAN
* chip.  LAN interrupts are controlled by the ISA Bridge Control (IBC)
* chip.  The LANCE chip on this board is on the Peripheral Component
* Interconnect (PCI) bus.  The PCI interrupts should be routed through the
* IBC to the processor.  The LANCE chip asserts PCI IRQ0 which is routed
* to the IBC.  The IBC must be programmed to generate an ISA IRQ10.
*
* RETURNS: OK, or ERROR if network support not included.
*
* SEE ALSO: sysLanIntDisable()
*/

STATUS sysLanIntEnable
    (
    int intLevel 		/* interrupt level to enable */
    )
    {
#ifdef INCLUDE_NETWORK
    intEnable (intLevel);
    return (OK);
#else
    return (ERROR);
#endif /* INCLUDE_NETWORK */
    }


/******************************************************************************
*
* sysLanIntDisable - disable the LAN interrupt
*
* This routine disables interrupts for the on-board LAN chip. 
*
* RETURNS: OK, or ERROR if network support not included.
*
* SEE ALSO: sysLanIntEnable()
*/

STATUS sysLanIntDisable
    (
    int intLevel 		/* interrupt level to enable */
    )
    {
#ifdef INCLUDE_NETWORK
    /* 
     *  disable the ISA IRQ10 for MV2600
     */

    intDisable (intLevel);

    return (OK);
#else
    return (ERROR);
#endif /* INCLUDE_NETWORK */
    }


/******************************************************************************
*
* sysSpuriousIntHandler - spurious interrupt handler
*
* This is the entry point for spurious interrupts.
*
* NOTE: This routine has no effect.
*
* This routine catches all spurious interrupts.  It does nothing at all.
*
* RETURNS: N/A.
*
* RETURNS: N/A
*
* NOMANUAL
*/

void sysSpuriousIntHandler (void)
    {
    }


/******************************************************************************
*
* sysNvRead - read one byte from NVRAM
*
* This routine reads a single byte from a specified offset in NVRAM.
*
* RETURNS: The byte from the specified NVRAM offset.
*/

UCHAR sysNvRead
    (
    ULONG	offset	/* NVRAM offset to read the byte from */
    )
    {
    sysOutByte (NV_RAM_LSB_REG, LSB(offset));
    sysOutByte (NV_RAM_MSB_REG, MSB(offset));
    return sysInByte (NV_RAM_DAT_REG);
    }


/******************************************************************************
*
* sysNvWrite - write one byte to NVRAM
*
* This routine writes a single byte to a specified offset in NVRAM.  The
* MVME2600 uses a 48T18 device w/fast write times, no wait.
*
* RETURNS: N/A
*/

void sysNvWrite
    (
    ULONG	offset,	/* NVRAM offset to write the byte to */
    UCHAR	data	/* datum byte */
    )
    {
    sysOutByte (NV_RAM_LSB_REG, LSB(offset));
    sysOutByte (NV_RAM_MSB_REG, MSB(offset));
    sysOutByte (NV_RAM_DAT_REG, data);
    }


/*******************************************************************************
*
* sysCpuCheck - confirm the CPU type
*
* This routine validates the cpu type.  If the wrong cpu type is discovered
* a message is printed using the serial channel in polled mode.
*
* RETURNS: N/A.
*/

void sysCpuCheck (void)
    {
    int msgSize;
    int msgIx;
    SIO_CHAN * pSioChan;        /* serial I/O channel */

    /* Check for a valid CPU type;  If one is found, just return */

#if	(CPU == PPC603)

    if	((CPU_TYPE == CPU_TYPE_603) || (CPU_TYPE == CPU_TYPE_603E) ||
         (CPU_TYPE == CPU_TYPE_603P))
	{
	return;
	}

#else	/* (CPU == PPC604) */

    if	((CPU_TYPE == CPU_TYPE_604) || (CPU_TYPE == CPU_TYPE_604E) ||
	 (CPU_TYPE == CPU_TYPE_604R) || (CPU_TYPE == CPU_TYPE_750))
	{
	return;
	}

#endif	/* (CPU == PPC604) */

    /* Invalid CPU type; print error message and terminate */

    msgSize = strlen (wrongCpuMsg);

    sysSerialHwInit ();

    pSioChan = sysSerialChanGet (0);

    sioIoctl (pSioChan, SIO_MODE_SET, (void *) SIO_MODE_POLL);

    for (msgIx = 0; msgIx < msgSize; msgIx++)
    	{
    	while (sioPollOutput (pSioChan, wrongCpuMsg[msgIx]) == EAGAIN);
    	}

    sysToMonitor (BOOT_NO_AUTOBOOT);
    }


/******************************************************************************
*
* sysRavenErrClr - Clear error conditions in Raven
*
* This routine clears any existing errors in the Motorola Raven PCI Host Bridge
* Controller.
*
* RETURNS: N/A
*/

void sysRavenErrClr (void)
    {
    /* Clear MPC Error Status register */

    sysOutByte ((RAVEN_BASE_ADRS + RAVEN_MPC_MERST), RAVEN_MPC_MERST_CLR);

    /* get and clear Raven PCI status reg */

    pciConfigOutWord (ravPciBusNo, ravPciDevNo, ravPciFuncNo, PCI_CFG_STATUS,
                      RAVEN_PCI_CFG_STATUS_DPAR | RAVEN_PCI_CFG_STATUS_SIGTA |
                      RAVEN_PCI_CFG_STATUS_RCVTA | RAVEN_PCI_CFG_STATUS_RCVMA |
                      RAVEN_PCI_CFG_STATUS_SIGSE | RAVEN_PCI_CFG_STATUS_RCVPE);
    }


/******************************************************************************
*
* sysPciExtRavenInit - initialize the extended portion of the Raven PCI header
*
* This routine initializes the extended portion of the PCI header for the 
* Motorola Raven ISA Bridge Controller (IBC).
*
* RETURNS: OK, or ERROR if...
*
* SEE ALSO: sysPciExtIbcInit()
*/

STATUS sysPciExtRavenInit
    (
    int busNo,          /* bus number */
    int deviceNo,       /* device number */
    int funcNo          /* function number */
    )
    {
    /*
     * Init Raven's MPIC control register access addresses in I/O and
     * memory spaces:
     *
     * IOSPACE  - 0x00000000  [no access]
     * MEMSPACE - 0x3C000000  [MPIC_PCI_BASE_ADRS]
     */

    pciConfigOutLong (busNo, deviceNo, funcNo, PCI_CFG_BASE_ADDRESS_0,
                      0x00000000);
    pciConfigOutLong (busNo, deviceNo, funcNo, PCI_CFG_BASE_ADDRESS_1,
                      MPIC_PCI_BASE_ADRS);
 
    /*
     *  Init Raven's Slave decoders (range/offset/attributes)
     *
     *  These decoders map addresses on the PCI bus to the CPU for
     *  access to local DRAM.
     *
     *  Because hardware can read past real memory, it is necessary to disable
     *  Read Ahead for the last 64k of physical memory (DRAM).
     */

    pciConfigOutLong (busNo, deviceNo, funcNo, PCI_CFG_RAVEN_PSADD0,
                      PCI2CPU_ADDR0_RANGE);
    pciConfigOutWord (busNo, deviceNo, funcNo, PCI_CFG_RAVEN_PSOFF0,
                      PCI2CPU_OFFSET0);
    pciConfigOutByte (busNo, deviceNo, funcNo, PCI_CFG_RAVEN_PSATT0,
                      PCI2CPU_ATT0);

    pciConfigOutLong (busNo, deviceNo, funcNo, PCI_CFG_RAVEN_PSADD1,
                      PCI2CPU_ADDR1_RANGE);
    pciConfigOutWord (busNo, deviceNo, funcNo, PCI_CFG_RAVEN_PSOFF1,
                      PCI2CPU_OFFSET1);
    pciConfigOutByte (busNo, deviceNo, funcNo, PCI_CFG_RAVEN_PSATT1,
                      PCI2CPU_ATT1);

    pciConfigOutLong (busNo, deviceNo, funcNo, PCI_CFG_RAVEN_PSADD2,
                      PCI2CPU_ADDR2_RANGE);
    pciConfigOutWord (busNo, deviceNo, funcNo, PCI_CFG_RAVEN_PSOFF2,
                      PCI2CPU_OFFSET2);
    pciConfigOutByte (busNo, deviceNo, funcNo, PCI_CFG_RAVEN_PSATT2,
                      PCI2CPU_ATT2);

    pciConfigOutLong (busNo, deviceNo, funcNo, PCI_CFG_RAVEN_PSADD3,
                      PCI2CPU_ADDR3_RANGE);
    pciConfigOutWord (busNo, deviceNo, funcNo, PCI_CFG_RAVEN_PSOFF3,
                      PCI2CPU_OFFSET3);
    pciConfigOutByte (busNo, deviceNo, funcNo, PCI_CFG_RAVEN_PSATT3,
                      PCI2CPU_ATT3);
 
    /*
     *  Enable Raven's PCI master capability and MEM space
     *  (i.e., enable PCI space decoders).
     */
    pciConfigOutWord (busNo, deviceNo, funcNo, PCI_CFG_COMMAND, 0x0006);

    return (OK);
    }


#ifdef INCLUDE_PMC_SPAN
/******************************************************************************
*
* sysPmcSpanConfig - configure the PMC Span (DEC21150 PCI-to-PCI Bridge)
*
* This routine configures the DEC21150 PCI-to-PCI Bridge on the PMC Span.
*
* RETURNS: OK or ERROR if pciConfigLib has not been initialized.
*/

STATUS sysPmcSpanConfig
    (
    int         pciBusNo,       /* PCI bus number */
    int         pciDevNo,       /* PCI device number */
    int         pciFuncNo,      /* PCI function number */
    PMC_SPAN *  pmcSpan         /* pointer to PMC Span config array */
    )
    {
    STATUS      result = OK;
    FAST        i;

    /* Write all parameters in pcmSpan in the order given */

    for (i = 0; i < NUM_PMC_SPAN_PARMS && result == OK; ++i)
        {
        switch (pmcSpan[i].parmSize)
            {
            case 1:
                result = pciConfigOutByte (pciBusNo, pciDevNo, pciFuncNo,
                                           pmcSpan[i].parmOffset,
                                           pmcSpan[i].parmValue);
                break;

            case 2:
                result = pciConfigOutWord (pciBusNo, pciDevNo, pciFuncNo,
                                           pmcSpan[i].parmOffset,
                                           pmcSpan[i].parmValue);
                break;

            case 4:
                result = pciConfigOutLong (pciBusNo, pciDevNo, pciFuncNo,
                                           pmcSpan[i].parmOffset,
                                           pmcSpan[i].parmValue);
                break;
            }
        }

    return (result);
    }
#endif /* INCLUDE_PMC_SPAN */


/******************************************************************************
*
* sysGetBusSpd - get the speed of the 60x processor bus
*
* This routine returns the speed (in MHz) of the 60x system bus.
*
* RETURNS: The bus speed (inMHz).
*/

int sysGetBusSpd (void)
    {
    int busSpd;
    int speed;

    busSpd = (( *MV2600_CCR ) & MV2600_CCR_CLK_MSK );

    switch (busSpd)
        {
        case MV2600_CCR_CPU_CLK_66:
            speed = 67;
	    break;
	case MV2600_CCR_CPU_CLK_60:
	    speed = 60;
	    break;
	case MV2600_CCR_CPU_CLK_50:
	    speed = 50;
	    break;
	default:
	    speed = 67;
        }
    return (speed);
    }


/******************************************************************************
*
* sysDec21x40EnetAddrGet - retrive ethernet address.
*
* This routine returns a six-byte ethernet address for a given ethernet unit.
* The dec21x40End driver uses this routine to obtain the ethernet address if
* indicated by a user-flag in DEC_LOAD_STRING in configNet.h; or if the
* reading the ethernet address ROM is unsuccessful.
*
* RETURNS: ERROR, always since this board always has a valid standard ethernet
* address ROM.
*/

STATUS sysDec21