syslib.c

VxWorkS下 MV2604的BSP源代码

/* sysLib.c - Motorola MVME2600 board series system-dependent library */

/* Copyright 1984-2002 Wind River Systems, Inc. */
/* Copyright 1996,1997,1998 Motorola, Inc. All Rights Reserved */

/*
modification history
--------------------
02t,17jul02,kab  SPR 73642: sysBusTas* cleanup
02s,30apr02,sbs  fixing compiler warnings
02r,26mar02,dtr  Removing compiler warnings.
02q,30nov01,gls  fixed sysBatDesc definition (SPR #20321)
02p,06nov01,dat  Fix to sysBusTasClear, SPR 30848
02o,11oct99,dmw  Added error message if VME_A32_MSTR_LOCAL is less than
                 the total DRAM size.
02n,18aug99,dmw  Added support for mv2300SC.
02m,24feb99,sbs  corrected mod history (SPR #21146).
02l,09feb99,mas  Removed erroneous Guard bit on Flash memory region (SPR 24893)
02k,03dec98,mas  added GUARDED attributes to non-local memory areas mapped in
		 sysPhysMemDesc[]. (SPR 23674)
02j,13oct98,dat  SPR 20654, added ravenAuxClk for mv2300
02i,24aug98,mdp  Fixed support for ECC
02h,07aug98,tb   Added VMEbus DMA support
02g,07aug98,tb   Fixed support for SM_OFF_BOARD
02f,25jun98,mas  all variables except sysPhysMemSize are now conditionally
		 compiled in sysPhysMemTop() (SPR 21271).
02e,28apr98,mas  removed variable sysVmeEnable (SPR 21043).
02d,16apr98,dat  moved sysHid1Get to sysALib.o
02c,15apr98,db   added support for floppy disk driver.
02b,14apr98,ms_  merged Motorola mv2700 support
02a,11feb98,tb   Added TAS support which uses VMEbus RMW
01z,17dec97,tb   Added Universe II support
01y,19aug97,scb  Add MPC750 (Arthur) support.
01x,05nov97,mas  removed intConnect and counter for sysUnivVERRIntr; added
		 EIEIO_SYNC in sysMemProbeBus(); fixed sysVmeProbe(); changed
		 P2P_PREF_MEM_SIZE to P2P_NONPREF_MEM_SIZE (SPR 9654, 9717).
01w,31oct97,mas  added intConnect and counter for sysUnivVERRIntr (SPR 9438).
01v,25jul97,srr  added 604r (Mach 5) support (SPR 8911).
	    mas
01u,24jul97,mas  added support for dynamic memory sizing (SPR 8824).
01t,14jul97,mas  added support for probing all buses w/sysBusProbe() (SPR 8022).
01s,11jul97,tb   fixed Secondary SCSI bug (MR 78).
01r,11jun97,mas  merged w/SENS version of BSP.
01q,05jun97,mas  added support for serial ports 3 & 4 (Z85230 ESCC). (SPR 8566)
01p,02jun97,map  removed sysDec21x40MediaSelect().
01o,29may97,dat  remove sysGetDramSpd to romInit.s. Add reset to MPIC before
		 initializing it.  Modified sysModel for MV3600.
		 (MCG MR #67, 73) SPRs 8289, 8560.
01n,12may97,dat  fixed mangen bugs
01m,09may97,mas  added extended VME support (SPR 8410).
		 now clears BRDFAIL LED after sysHwInit() (SPR 8432).
01l,29apr97,dat  removed old pci.h now using pciIomapLib.h
01k,25apr97,map  added support for dec21x40End driver.
01j,24apr97,mas  added support for MPIC (SPR 8170).
01i,11apr97,dat  using local version of pciIomapLib.c - temporarily.
01h,10apr97,mas  added support for pciIomapLib and PMC Span board (SPR 8226).
01g,01apr97,dat  new VME configuration macros SPR 8271
01f,24mar97,mas  made Lance and Scsi init/control code conditional (SPR 8141).
01e,10jan97,dat  added sysBusClearTas setup, fixed WD_TIMER setup.
            mas  fixed 64K VME problem (from motorola).
01d,02jan97,wlf  doc: cleanup.
01c,02jan97,dat  removed refs to mv1600, fixed mod history
01b,17dec96,mas  removed raven.h, universe.h and ncr810.h includes; added
		 include of pci.h (SPR 7525).
01a,01sep96,mot  written. (from ver 01t of mv1600 bsp)
*/

/*
DESCRIPTION
This library provides board-specific routines.  The chip drivers included are:

    i8250Sio.c - Intel 8250 UART driver 
    z8530Sio.c - Zilog 8530 ESCC driver
    ppcDecTimer.c - PowerPC decrementer timer library (system clock)
    ppcZ8536Timer.c - Zilog Z8536 timer library (auxiliary clock)
    byteNvRam.c - byte-oriented generic non-volatile RAM library
    pciConfigLib.c - PCI configuration library
    universe.c - Tundra Universe chip VME-to-PCI interface library
    ncr810Lib - NCR 53C810 or NCR 53C825 SCSI controller library
    fdcDrv.c - driver for PS2 floppy device controller(FDC)
    isaDma.c - I8237 ISA DMA transfer interface library

    sl82565IntrCtl.c - interrupt controller driver
         or
    ravenMpic.c - raven Mpic / W83C553 PIB/IBC Interrupt Controller

INCLUDE FILES: sysLib.h

SEE ALSO:
.pG "Configuration"
*/

/* includes */

#include "vxWorks.h"
#include "vme.h"
#include "memLib.h"
#include "cacheLib.h"
#include "sysLib.h"
#include "config.h"
#include "string.h"
#include "intLib.h"
#include "esf.h"
#include "excLib.h"
#include "logLib.h"
#include "taskLib.h"
#include "vxLib.h"
#include "tyLib.h"
#include "arch/ppc/archPpc.h"
#include "arch/ppc/mmu603Lib.h"
#include "arch/ppc/vxPpcLib.h"
#include "arch/ppc/excPpcLib.h"
#include "private/vmLibP.h"
#include "drv/pci/pciConfigLib.h"


/* defines */

#define ZERO	0


/* globals */

/*
 * sysBatDesc[] is used to initialize the block address translation (BAT)
 * registers within the PowerPC 603/604 MMU.  BAT hits take precedence
 * over Page Table Entry (PTE) hits and are faster.  Overlap of memory
 * coverage by BATs and PTEs is permitted in cases where either the IBATs
 * or the DBATs do not provide the necessary mapping (PTEs apply to both
 * instruction AND data space, without distinction).
 *
 * The primary means of memory control for VxWorks is the MMU PTE support
 * provided by vmLib and cacheLib.  Use of BAT registers will conflict
 * with vmLib support.  User's may use BAT registers for i/o mapping and
 * other purposes but are cautioned that conflicts with cacheing and mapping
 * through vmLib may arise.  Be aware that memory spaces mapped through a BAT
 * are not mapped by a PTE and any vmLib() or cacheLib() operations on such
 * areas will not be effective, nor will they report any error conditions.
 *
 * Note: BAT registers CANNOT be disabled - they are always active.
 * For example, setting them all to zero will yield four identical data
 * and instruction memory spaces starting at local address zero, each 128KB
 * in size, and each set as write-back and cache-enabled.  Hence, the BAT regs
 * MUST be configured carefully.
 *
 * With this in mind, it is recommended that the BAT registers be used
 * to map LARGE memory areas external to the processor if possible.
 * If not possible, map sections of high RAM and/or PROM space where
 * fine grained control of memory access is not needed.  This has the
 * beneficial effects of reducing PTE table size (8 bytes per 4k page)
 * and increasing the speed of access to the largest possible memory space.
 * Use the PTE table only for memory which needs fine grained (4KB pages)
 * control or which is too small to be mapped by the BAT regs.
 *
 * The BAT configuration for 4xx/6xx-based PPC boards is as follows:
 * All BATs point to PROM/FLASH memory so that end customer may configure
 * them as required.
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 */

UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT)] =
    {
    /* I BAT 0 */
    ((ROM_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT),

    /* I BAT 1 */

    0, 0,

    /* I BAT 2 */

    0, 0,

    /* I BAT 3 */

    0, 0,

    /* D BAT 0 */
    ((ROM_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT),

    /* D BAT 1 */

    0, 0,

    /* D BAT 2 */

    0, 0,

    /* D BAT 3 */

    0, 0

    };

/*
 * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array
 * used by the MMU to translate addresses with single page (4k) granularity.
 * PTE memory space should not, in general, overlap BAT memory space but
 * may be allowed if only Data or Instruction access is mapped via BAT.
 *
 * Address translations for local RAM, memory mapped PCI bus, memory mapped
 * VME A16 space and local PROM/FLASH are set here.
 *
 * PTEs are held, strangely enough, in a Page Table.  Page Table sizes are
 * integer powers of two based on amount of memory to be mapped and a
 * minimum size of 64 kbytes.  The MINIMUM recommended Page Table sizes
 * for 32-bit PowerPCs are:
 *
 * Total mapped memory		Page Table size
 * -------------------		---------------
 *        8 Meg			     64 K
 *       16 Meg			    128 K
 *       32 Meg			    256 K
 *       64 Meg			    512 K
 *      128 Meg			      1 Meg
 * 	.				.
 * 	.				.
 * 	.				.
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 *
 * *** EXTENDED_VME configuration ***
 *
 * The user can use TLBs, and/or BATs, to map VME A32 space to the processor.
 * The default is to use TLBs (MMU).  Change the table entry below to use
 * a different method. (See "MODIFY A32 VME WINDOW HERE")
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
    {
    {
    /* Vector Table and Interrupt Stack */

    (void *) LOCAL_MEM_LOCAL_ADRS,
    (void *) LOCAL_MEM_LOCAL_ADRS,
    RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },

    {
    /* Local DRAM */

    (void *) RAM_LOW_ADRS,
    (void *) RAM_LOW_ADRS,
    LOCAL_MEM_SIZE -  RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE
    },

    {
    /* PCI address spaces */

    (void *) CPU_PCI_ISA_IO_ADRS,
    (void *) CPU_PCI_ISA_IO_ADRS,
    CPU_PCI_ISA_IO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

    {
    (void *) CPU_PCI_IO_ADRS,
    (void *) CPU_PCI_IO_ADRS,
    CPU_PCI_IO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

#ifndef INCLUDE_MPIC
    {
    (void *) CPU_PCI_IACK_ADRS,
    (void *) CPU_PCI_IACK_ADRS,
    CPU_PCI_IACK_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },
#endif /* INCLUDE_MPIC */

    {
    (void *) CPU_PCI_MEM_ADRS,
    (void *) CPU_PCI_MEM_ADRS,
    CPU_PCI_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

    {
    (void *) CPU_PCI_ISA_MEM_ADRS,
    (void *) CPU_PCI_ISA_MEM_ADRS,
    CPU_PCI_ISA_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },


    {
    /* MODIFY A32 VME WINDOW HERE */
    (void *) VME_A32_MSTR_LOCAL,
    (void *) VME_A32_MSTR_LOCAL,
    VME_A32_MSTR_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

    {
    (void *) VME_A24_MSTR_LOCAL,
    (void *) VME_A24_MSTR_LOCAL,
    VME_A24_MSTR_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

    {
    (void *) VME_A16_MSTR_LOCAL,
    (void *) VME_A16_MSTR_LOCAL,
    VME_A16_MSTR_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

    {
    /* Off-board VME LM/SIG/Semaphore Regs */

    (void *) CPU_VME_WINDOW_REG_BASE,
    (void *) CPU_VME_WINDOW_REG_BASE,
    VME_A32_REG_SPACE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

    {
    /* MPIC Regs */

    (void *) MPIC_BASE_ADRS,
    (void *) MPIC_BASE_ADRS,
    MPIC_REG_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

    {
    (void *) FALCON_BASE_ADRS,
    (void *) FALCON_BASE_ADRS,
    FALCON_REG_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

    {
    (void *) RAVEN_BASE_ADRS,
    (void *) RAVEN_BASE_ADRS,
    RAVEN_REG_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

    {
    (void *) FLASH_BASE_ADRS,
    (void *) FLASH_BASE_ADRS,
    FLASH_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    }
    };

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);

int    sysBus      = VME_BUS;		/* system bus type */
int    sysCpu      = CPU;		/* system CPU type (MC680x0) */
char * sysBootLine = BOOT_LINE_ADRS;	/* address of boot line */
char * sysExcMsg   = EXC_MSG_ADRS;	/* catastrophic message area */
int    sysProcNum;			/* processor number of this CPU */
int    sysFlags;			/* boot flags */
char   sysBootHost [BOOT_FIELD_LEN];	/* name of host from which we booted */
char   sysBootFile [BOOT_FIELD_LEN];	/* name of file from which we booted */
UINT   sysVectorIRQ0  = INT_VEC_IRQ0;	/* vector for IRQ0 */
static int   ravPciBusNo;               /* Raven Config Space BDF address */
static int   ravPciDevNo;
static int   ravPciFuncNo;
int    pciToVmeDev;			/* PCI to VME Bridge Device */

/* last 5 nibbles are board specific, initialized in sysHwInit */

unsigned char lnEnetAddr [6] = { 0x08, 0x00, 0x3e, 0x00, 0x00, 0x00 };
unsigned char clearWd [1]  = { 0x00 };

#ifdef INCLUDE_PMC_SPAN
/*
 * PMC Span (DEC21150 PCI-to-PCI Bridge) Configuration Parameter Array
 *
 * This array MUST contain the parameters in the order which they will
 * be set.
 */

PMC_SPAN sysPmcSpanParm [] =
{
  {PCI_CFG_COMMAND, 2,   P2P_PMC_DISABLE},
  {PCI_CFG_STATUS,  2,   P2P_CLR_STATUS >> 16},
  {PCI_CFG_BRIDGE_CONTROL, 2, P2P_SEC_BUS_RESET},
  {PCI_CFG_CACHE_LINE_SIZE, 2, P2P_CACHE_LINE_SIZE | P2P_PRIM_LATENCY},
  {PCI_CFG_PRIMARY_BUS,     1, PCI_PRIMARY_BUS},
  {PCI_CFG_SECONDARY_BUS,   1, PCI_SECONDARY_BUS},
  {PCI_CFG_SUBORDINATE_BUS, 1, PCI_SUBORD_BUS},
  {PCI_CFG_SEC_STATUS, 2,   P2P_CLR_STATUS >> 16},
  {PCI_CFG_IO_BASE, 2,   ((P2P_IO_BASE & 0x0000F000) >> 8) |
                         ((P2P_IO_BASE + P2P_IO_SIZE - 1) & 0x0000F000)},
  {PCI_CFG_MEM_BASE, 2,  ((P2P_NONPREF_MEM_BASE & 0xFFF00000) >> 16)},
  {PCI_CFG_MEM_LIMIT, 2, ((P2P_NONPREF_MEM_BASE + P2P_NONPREF_MEM_SIZE - 1) & \
                          0xFFF00000) >> 16},
  {PCI_CFG_PRE_MEM_BASE, 2, ((P2P_PREF_MEM_BASE & 0xFFF00000) >> 16)},
  {PCI_CFG_PRE_MEM_LIMIT, 2, ((P2P_PREF_MEM_BASE + P2P_PREF_MEM_SIZE - 1) & \
                              0xFFF00000) >> 16},
  {PCI_CFG_PRE_MEM_BASE_U,  4, P2P_PREF_HI32_BASE},  /* only < 4GB space */
  {PCI_CFG_PRE_MEM_LIMIT_U, 4, P2P_PREF_HI32_BASE},
  {PCI_CFG_IO_BASE_U,  2, ((P2P_IO_BASE & 0xFFFF0000) >> 16)},
  {PCI_CFG_IO_LIMIT_U, 2, ((P2P_IO_BASE + P2P_IO_SIZE - 1) & 0xFFFF0000) >> 16},
  {PCI_CFG_BRIDGE_CONTROL, 2, 0},
  {PCI_CFG_DEC21150_SEC_CLK,   2, P2P_CLK_ENABLE},
  {PCI_CFG_DEC21150_SERR_STAT, 1, (P2P_CLR_STATUS >> 16) & 0xFF},
  {PCI_CFG_STATUS,  2,  P2P_CLR_STATUS >> 16},
  {PCI_CFG_COMMAND, 2,  P2P_PMC_ENABLE}
};

#define NUM_PMC_SPAN_PARMS      (sizeof(sysPmcSpanParm) / sizeof(PMC_SPAN))
#endif /* INCLUDE_PMC_SPAN */

/* locals */

LOCAL char sysModelStr[80];