mv2600.h

VxWorkS下 MV2604的BSP源代码

 *
 * Note: the PCI bus is inherently little endian. 
 */

#define PCI_CFG_RAVEN_PSADD0	0x80
#define PCI_CFG_RAVEN_PSATT0	0x84
#define PCI_CFG_RAVEN_PSOFF0	0x86
#define PCI_CFG_RAVEN_PSADD1	0x88
#define PCI_CFG_RAVEN_PSATT1	0x8c
#define PCI_CFG_RAVEN_PSOFF1	0x8e
#define PCI_CFG_RAVEN_PSADD2	0x90
#define PCI_CFG_RAVEN_PSATT2	0x94
#define PCI_CFG_RAVEN_PSOFF2	0x96
#define PCI_CFG_RAVEN_PSADD3	0x98
#define PCI_CFG_RAVEN_PSATT3	0x9c
#define PCI_CFG_RAVEN_PSOFF3	0x9e

/* Raven MPC registers */

#define RAVEN_MPC_VENID		0x00
#define RAVEN_MPC_DEVID		0x02
#define RAVEN_MPC_REVID		0x05
#define RAVEN_MPC_GCSR		0x08
#define RAVEN_MPC_FEAT		0x0a
#define RAVEN_MPC_MARB		0x0e
#define RAVEN_MPC_PADJ		0x13
#define RAVEN_MPC_MEREN		0x22
#define RAVEN_MPC_MERST		0x27
#define RAVEN_MPC_MERAD		0x28
#define RAVEN_MPC_MERAT		0x2e
#define RAVEN_MPC_PIACK		0x30
#define RAVEN_MPC_MSADD0	0x40
#define RAVEN_MPC_MSOFF0	0x44
#define RAVEN_MPC_MSATT0	0x47
#define RAVEN_MPC_MSADD1	0x48
#define RAVEN_MPC_MSOFF1	0x4c
#define RAVEN_MPC_MSATT1	0x4f
#define RAVEN_MPC_MSADD2	0x50
#define RAVEN_MPC_MSOFF2	0x54
#define RAVEN_MPC_MSATT2	0x57
#define RAVEN_MPC_MSADD3	0x58
#define RAVEN_MPC_MSOFF3	0x5c
#define RAVEN_MPC_MSATT3	0x5f
#define RAVEN_MPC_WDT1CNTL      0x60
#define RAVEN_MPC_WDT2CNTL      0x68
#define RAVEN_MPC_GPREG0_U	0x70
#define RAVEN_MPC_GPREG0_L	0x74
#define RAVEN_MPC_GPREG1_U	0x78
#define RAVEN_MPC_GPREG1_L	0x7c

/*
 * Raven register bit masks
 *
 * Bits marked with 'C' indicate conditions which can be cleared by
 * writing a 1 to the bits.
 */

/* Raven MPC Error Enable (MEREN) register bit masks */

#define RAVEN_MPC_MEREN_RTAI	0x0001	/* PCI mstr Recvd Target Abort Int */
#define RAVEN_MPC_MEREN_SMAI	0x0002	/* PCI mstr Signld Target Abort Int */
#define RAVEN_MPC_MEREN_SERRI	0x0004	/* PCI System Error Int */
#define RAVEN_MPC_MEREN_PERRI	0x0008	/* PCI Parity Error Int */
#define RAVEN_MPC_MEREN_MATOI	0x0020	/* MPC Address Bus Time-out Int */
#define RAVEN_MPC_MEREN_RTAM	0x0100	/* RTAI machine check enable */
#define RAVEN_MPC_MEREN_SMAM	0x0200	/* SMAI machine check enable */
#define RAVEN_MPC_MEREN_SERRM	0x0400	/* SERRI machine check enable */
#define RAVEN_MPC_MEREN_PERRM	0x0800	/* PERRI machine check enable */
#define RAVEN_MPC_MEREN_MATOM	0x2000	/* MATOI machine check enable */
#define RAVEN_MPC_MEREN_DFLT	0x4000	/* Default MPC Master ID select */
#define RAVEN_MPC_MEREN_VALID	0x6F2F	/* Mask for valid MEREN bits */

/* Raven MPC Error Status (MERST) register bit masks */

#define RAVEN_MPC_MERST_RTA	0x01	/* C PCI mstr Recvd Target Abort */
#define RAVEN_MPC_MERST_SMA	0x02	/* C PCI mstr Signld Target Abort */
#define RAVEN_MPC_MERST_SERR	0x04	/* C PCI System Error */
#define RAVEN_MPC_MERST_PERR	0x08	/* C PCI Parity Error */
#define RAVEN_MPC_MERST_MATO	0x20	/* C MPC Address Bus Time-out */
#define RAVEN_MPC_MERST_OVF	0x80	/* C Error Status Overflow */
#define RAVEN_MPC_MERST_VALID	0xAF	/*   Mask for valid MERST bits */
#define RAVEN_MPC_MERST_CLR	0xAF	/*   Clears all errors */

/* Raven PCI Configuration Status register bit masks */

#define RAVEN_PCI_CFG_STATUS_FAST    0x0010  /*   Fast back-to-back capable */
#define RAVEN_PCI_CFG_STATUS_DPAR    0x0100  /* C Data prity error detected */
#define RAVEN_PCI_CFG_STATUS_SELTIM0 0x0200  /*   Device select timing bit 0 */
#define RAVEN_PCI_CFG_STATUS_SELTIM1 0x0400  /*   Device select timing bit 1 */
#define RAVEN_PCI_CFG_STATUS_SIGTA   0x0800  /* C Signalled Target Abort */
#define RAVEN_PCI_CFG_STATUS_RCVTA   0x1000  /* C Received Target Abort */
#define RAVEN_PCI_CFG_STATUS_RCVMA   0x2000  /* C Received Master Abort */
#define RAVEN_PCI_CFG_STATUS_SIGSE   0x4000  /* C Signalled System Error */
#define RAVEN_PCI_CFG_STATUS_RCVPE   0x8000  /* C Detected Parity Error */
#define RAVEN_PCI_CFG_STATUS_VALID   0xFF10  /*   Valid status bits */
#define RAVEN_PCI_CFG_STATUS_CLR     0xF900  /*   Clears all conditions */

/*
 * PMC Span DEC21150 PCI-to-PCI Bridge device-specific registers
 *
 * These registers are in Configuration Space and are extensions to a
 * standard type 1 PCI header.
 */

#define PCI_CFG_DEC21150_CHIP_CTRL 0x40
#define PCI_CFG_DEC21150_DIAG_CTRL 0x41
#define PCI_CFG_DEC21150_ARB_CTRL  0x42
#define PCI_CFG_DEC21150_EVNT_DSBL 0x64
#define PCI_CFG_DEC21150_GPIO_DOUT 0x65
#define PCI_CFG_DEC21150_GPIO_CTRL 0x66
#define PCI_CFG_DEC21150_GPIO_DIN  0x67
#define PCI_CFG_DEC21150_SEC_CLK   0x68     /* secondary clock controll reg */
#define PCI_CFG_DEC21150_SERR_STAT 0x6A

/* programmable interrupt controller (PIC) */

#define	PIC_REG_ADDR_INTERVAL	1	/* address diff of adjacent regs. */

/* programmable interrupt timers */

#define PIT_BASE_ADR		SL82565_TMR1_CNT0	/* timeraddrs */
#define PIT_REG_ADDR_INTERVAL	1
#define PIT_CLOCK		1193180

/* serial ports (COM1 - COM4) */

#ifdef INCLUDE_I8250_SIO
#  define COM1_BASE_ADR		pc87303_COM1	/* serial port 1 */
#  define COM2_BASE_ADR		pc87303_COM2	/* serial port 2 */
#  define UART_REG_ADDR_INTERVAL  1       	/* addr diff of adjacent regs */
#  define N_UART_CHANNELS 	2		/* No. serial I/O channels */
#endif /* INCLUDE_I8250_SIO */

#ifdef INCLUDE_Z85230_SIO
#  define BAUD_CLK_FREQ		10000000        /* 10 MHz "P Clock" (fixed) */
#  define REG_8530_WRITE(reg,val) sysOutByte((UINT32)(reg), (UINT8)(val))
#  define REG_8530_READ(reg,pVal) *(UINT8 *)pVal = sysInByte((UINT32)reg)
#  define DATA_REG_8530_DIRECT
/* #  define Z8530_RESET_DELAY_COUNT 2000 */
#define Z8530_RESET_DELAY \
        { \
        int i; \
        for (i = 0; i < Z8530_RESET_DELAY_COUNT; i++) \
                ; /* do nothing */ \
        }
#endif /* INCLUDE_Z85230_SIO */

/* total number of serial ports */

#if defined(INCLUDE_I8250_SIO) && defined(INCLUDE_Z85230_SIO)
#  define N_SIO_CHANNELS	4		/* No. serial I/O channels */
#elif defined(INCLUDE_I8250_SIO)
#  define N_SIO_CHANNELS	2		/* No. serial I/O channels */
#elif defined(INCLUDE_Z85230_SIO)
#  define N_SIO_CHANNELS	2		/* No. serial I/O channels */
#else
#  define N_SIO_CHANNELS	0		/* No. serial I/O channels */
#endif

/* non-volatile (battery-backed) ram defines
 *
 * the top 16 bytes are used for the RTC registers
 */

#define	BBRAM_ADRS		0		/* base address */
#define	BBRAM_SIZE		0x1ff0		/* 8k NVRAM Total Size */

/* factory ethernet address */

#define	BB_ENET			((char *)(BBRAM_ADRS + 0x1f2c))

/* MK48TXX register settings */

/* flag register */

#define MK48T_FLAGS		((char *)(BBRAM_ADRS + 0x1ff0))

/* alarm clock registers, 4 1byte locations */

#define ALARM_CLOCK		((char *)(BBRAM_ADRS + 0x1ff2))

/* interrupt register */

#define MK48T_INTR		((char *)(BBRAM_ADRS + 0x1ff6))

/* watchdog timer register */

#define WD_TIMER		((char *)(BBRAM_ADRS + 0x1ff7))

/* MK48TXX bb time of day clk, 8 1byte locations */

#define	TOD_CLOCK 		((char *)(BBRAM_ADRS + 0x1ff8))

#define NV_RAM_IO_MAPPED	/* nvram is io mapped in ISA space */
#define NV_RAM_READ(x)		sysNvRead (x)
#define NV_RAM_WRITE(x,y)	sysNvWrite (x,y)
#define NV_RAM_LSB_REG		m48TXX_LSB_REG
#define NV_RAM_MSB_REG		m48TXX_MSB_REG
#define NV_RAM_DAT_REG		m48TXX_DAT_REG

/* ncr810/ncr825 delay loop count */

#define NCR810_DELAY_MULT       10


/*
 * UNIVERSE REGISTER SETUP FOR CPU <-> VME MAPPING (via PCI)
 *
 * ALL VAL_LSIx and VAL_VSIx values MUST be multiples of 64KB !!!
 * Except VAL_LSI0 and VAL_VSI0, which must be multiples of 4KB !
 */

/*
 * VME MASTER WINDOW FOR LM/SEM (MAILBOX) REGISTERS
 *
 * Universe PCI slave (VME master) window 0
 * 
 * Map access to A32 VMEbus (VME LM/SEM Regs) (64K)
 */

#define VME_A32_REG_SIZE	0x00001000	/* individual reg space */
#define	VME_A32_REG_SPACE	0x00010000	/* total reg space */

#ifndef EXTENDED_VME
/*
 * Map access to A32 VMEbus (LM/SEM Regs) - 64K  MAP FOR STANDARD vxWorks
 * This maps: MPU RANGE:     0xf0000000 - 0xf000ffff  
 *        to: PCI RANGE:     0x30000000 - 0x3000ffff
 *        to: VME RANGE:     0x40000000 - 0x4000ffff
 */
#  define CPU_VME_WINDOW_REG_BASE	0xf0000000
#  define VME_A32_REG_BASE		0x40000000
#  define VAL_LSI0_BS_VALUE	(CPU_VME_WINDOW_REG_BASE - CPU_PCI_ISA_MEM_ADRS)
#else
/*
 * Map access to A32 VMEbus (LM/SEM Regs) - 64K  MAP FOR EXTENDED VME vxWorks
 * This maps: MPU RANGE:     0xfb000000 - 0xfb00ffff
 *        to: PCI RANGE:     0xfb000000 - 0xfb00ffff
 *        to: VME RANGE:     0xfb000000 - 0xfb00ffff
 */
#  define CPU_VME_WINDOW_REG_BASE	0xfb000000
#  define VME_A32_REG_BASE	0xfb000000
#  define VAL_LSI0_BS_VALUE	(CPU_VME_WINDOW_REG_BASE)
#endif
#define VAL_LSI0_BS		(VAL_LSI0_BS_VALUE)
#define VAL_LSI0_BD		(VAL_LSI0_BS + VME_A32_REG_SPACE)
#define VAL_LSI0_TO		(VME_A32_REG_BASE - VAL_LSI0_BS)
#define VAL_LSI0_CTL		( LSI_CTL_EN     | LSI_CTL_WP  |\
                                  LSI_CTL_D64    | LSI_CTL_A32 |\
                                  LSI_CTL_DATA   | LSI_CTL_USR |\
                                  LSI_CTL_SINGLE | LSI_CTL_PCI_MEM )

/*
 * Semaphore Test-and-Set Register as seen from a slave.
 * Only used with a special version of sysBusTas() (not included)
 * and when mv2300, mv2600 or mv3600 boards are the ONLY boards
 * used in the configuration.
 */

#define OFFBRD_VME_SEM_REG1     (CPU_VME_WINDOW_REG_BASE + \
                                 (CPU_VME_SEM_REG1 - CPU_VME_HW_REGS_BASE)) 

/*
 * VME MASTER WINDOW FOR A24 SPACE
 *
 * Universe PCI slave (VME master) window 2
 */

#ifndef EXTENDED_VME
/*
 * Map access to A24 VMEbus - 16M       MAP FOR STANDARD vxWorks
 * This maps: MPU RANGE:     0xe0000000 - 0xe0ffffff
 *        to: PCI RANGE:     0x20000000 - 0x20ffffff
 *        to: VME RANGE:     0xff000000 - 0xffffffff
 */
#  define VME_A24_MSTR_LOCAL	0xe0000000
#  define VAL_LSI2_BS_VALUE    (VME_A24_MSTR_LOCAL - CPU_PCI_ISA_MEM_ADRS)
#else
/*
 * Map access to A24 VMEbus - 16M       MAP FOR EXTENDED VME vxWorks
 * This maps: MPU RANGE:     0xfa000000 - 0xfaffffff
 *        to: PCI RANGE:     0xfa000000 - 0xfaffffff
 *        to: VME RANGE:     0xff000000 - 0xffffffff
 */
#  define VME_A24_MSTR_LOCAL	0xfa000000
#  define VAL_LSI2_BS_VALUE	(VME_A24_MSTR_LOCAL)
#endif
#  if  (VME_A24_MSTR_SIZE > 0x01000000)
#  error Maximum VME_A24_MSTR_SIZE cannot exceed 16 MB
#  endif
#define VAL_LSI2_BS	(VAL_LSI2_BS_VALUE)
#define VAL_LSI2_BD	(VAL_LSI2_BS + VME_A24_MSTR_SIZE)
#define VAL_LSI2_TO	(0xff000000 + VME_A24_MSTR_BUS - VAL_LSI2_BS)
#define VAL_LSI2_CTL	( LSI_CTL_EN     | LSI_CTL_WP  |\
                          LSI_CTL_D64    | LSI_CTL_A24 |\
                          LSI_CTL_DATA   | LSI_CTL_USR |\
                          LSI_CTL_SINGLE | LSI_CTL_PCI_MEM )

/*
 * VME MASTER WINDOW FOR A32 SPACE
 *
 * Universe PCI slave (VME master) window 1
 */

#ifndef EXTENDED_VME
/*                      
 * Map access to A32 VMEbus - 128M      MAP FOR STANDARD vxWorks
 * This maps: MPU RANGE: 0xd8000000       - 0xdfffffff  
 *        to: PCI RANGE: 0x18000000       - 0x1fffffff
 *        to: VME RANGE: VME_A32_MSTR_BUS - VME_A32_MSTR_BUS + VME_A32_MSTR_SIZE
 */
#  define VAL_LSI1_BS_VALUE	(VME_A32_MSTR_LOCAL - CPU_PCI_ISA_MEM_ADRS)
#  if  (VME_A32_MSTR_SIZE > 0x08000000)
#  error VME_A32_MSTR_SIZE cannot exceed 128 MB
#  endif
#else
/*
 * Map access to A32 VMEbus - (up to ~3.7GB)  MAP FOR EXTENDED VME vxWorks
 * This maps: MPU RANGE: VME_A32_MSTR_LOCAL  - VME_A32_MSTR_LOCAL +
 *                                             VME_A32_MSTR_SIZE
 *        to: PCI RANGE: VME_A32_MSTR_LOCAL  - VME_A32_MSTR_LOCAL +
 *                                             VME_A32_MSTR_SIZE
 *        to: VME RANGE: VME_A32_MSTR_BUS    - VME_A32_MSTR_BUS +
 *                                             VME_A32_MSTR_SIZE
 *
 * NOTE:
 *  - VME_A32_MSTR_LOCAL + VME_A32_MSTR_SIZE must not exceed
 *    VME_A24_MSTR_LOCAL (no overlap of A32 and A24 address spaces)
 *  - for local memory sizes greater than 256 MB, set VME_A32_MSTR_LOCAL equal
 *    to the memory size.
 */
#  define VAL_LSI1_BS_VALUE	(VME_A32_MSTR_LOCAL)
#  if  ((VME_A32_MSTR_LOCAL + VME_A32_MSTR_SIZE) > VME_A24_MSTR_LOCAL)
#  error VME A32 space extends into VME A24 space
#  endif
#endif
#  if  ((VME_A32_MSTR_BUS + VME_A32_MSTR_SIZE) > VME_A32_REG_BASE) && \
       (VME_A32_MSTR_BUS < (VME_A32_REG_BASE + VME_A32_REG_SPACE))
#  warning VME A32 space overlaps VME LM/SEM (MAILBOX) REG space
#  endif

#define VAL_LSI1_BS	(VAL_LSI1_BS_VALUE)
#define VAL_LSI1_BD	(VAL_LSI1_BS + VME_A32_MSTR_SIZE)
#define VAL_LSI1_TO	(VME_A32_MSTR_BUS - VAL_LSI1_BS)   /*  LSI_CTL_WP  | */
#define VAL_LSI1_CTL	( LSI_CTL_EN     | LSI_CTL_WP  |\
                          LSI_CTL_D64    | LSI_CTL_A32 |\
                          LSI_CTL_DATA   | LSI_CTL_USR |\
                          LSI_CTL_SINGLE | LSI_CTL_PCI_MEM )

/*
 * VME MASTER WINDOW FOR A16 SPACE
 *
 * Universe PCI slave (VME master) window 3
 */

#ifndef EXTENDED_VME
/*
 * Map access to A16 VMEbus - 64K       MAP FOR STANDARD vxWorks
 * This maps: MPU RANGE:     0xefff0000 - 0xefffffff  
 *        to: PCI RANGE:     0x2fff0000 - 0x2fffffff
 *        to: VME RANGE:     0xffff0000 - 0xffffffff
 */
#define VME_A16_MSTR_LOCAL	0xefff0000
#define VAL_LSI3_BS_VALUE	(VME_A16_MSTR_LOCAL - CPU_PCI_ISA_MEM_ADRS)
#else
/*
 * Map access to A16 VMEbus - 64K       MAP FOR EXTENDED VME vxWorks
 * This maps: MPU RANGE:     0xfbff0000 - 0xfbffffff
 *        to: PCI RANGE:     0xfbff0000 - 0xfbffffff
 *        to: VME RANGE:     0xfbff0000 - 0xfbffffff
 */
#  define VME_A16_MSTR_LOCAL	0xfbff0000
#  define VAL_LSI3_BS_VALUE	(VME_A16_MSTR_LOCAL)
#endif
#  if  (VME_A16_MSTR_SIZE > 0x00010000)
#  error Maximum VME_A16_MSTR_SIZE cannot exceed 64 KB
#  endif
#define	VME_A16_MSTR_BUS	0x00000000	/* must be 0 */
#define VAL_LSI3_BS		(VAL_LSI3_BS_VALUE)
#define VAL_LSI3_BD		(VAL_LSI3_BS + VME_A16_MSTR_SIZE)
#define VAL_LSI3_TO		(0xffff0000 + VME_A16_MSTR_BUS - VAL_LSI3_BS)
#define VAL_LSI3_CTL		( LSI_CTL_EN     | LSI_CTL_WP  |\
                                  LSI_CTL_D64    | LSI_CTL_A16 |\
                                  LSI_CTL_DATA   | LSI_CTL_USR |\
                                  LSI_CTL_SINGLE | LSI_CTL_PCI_MEM )

/*
 * VME MASTER MEMORY WINDOW LIMITS
 *
 * These values are strictly defined by the base memory addresses and window
 * sizes of the spaces defined above.  These values must be correct for the
 * sysBusProbe() memory range checks of the VME bus to work properly.