mv2600.h

VxWorkS下 MV2604的BSP源代码

#define CNFG_VGA_ADRS		0x80007800 /* Graphics Device */
#define CNFG_PMC1_ADRS		0x80008000 /* PMC Slot1 */
#define CNFG_SCSI2_ADRS		0x80008800 /* Secondary SCSI */
#define CNFG_LN2_ADRS		0x80009000 /* Secondary Ethernet */
#define CNFG_PMC2_ADRS		0x80009800 /* PMC Slot 2 or PCIX */
     
/* Number of PCI devices */

#define NUM_PCI_DEVS		4

/* PCI Device/Vendor IDs */

#define PCI_ID_RAVEN            0x48011057      /* Id for RAVEN ASIC */
#define PCI_ID_IBC              0x056510ad      /* Id for W83C553 PIB */
#define PCI_ID_UNIVERSE         0x000010e3      /* Id for Universe VME chip */
#define PCI_ID_LN_DEC21140      0x00091011      /* Id DEC chip 21140 */
#define PCI_ID_LN_DEC21143      0x00191011      /* Id DEC chip 21143 */
#define PCI_ID_SCSI             0x00031000      /* Id for SYM53C825/75 Chips */
#define PCI_ID_SEC_SCSI         0x000f1000      /* Id for SYM53C810A Chip */
#define PCI_ID_NCR810           0x00011000      /* Id for SYM53C810A Chip */
#define PCI_ID_NCR860           0x00061000      /* Id for SYM53C860 Chip */
#define PCI_ID_NCR825           0x00031000      /* Id for SYM53C825/75 Chips*/
#define PCI_ID_NCR875           0x000f1000      /* Id for SYM53C875 Chip*/
#define PCI_ID_LN_DEC21040      0x00021011      /* Id DEC chip 21040 */
#define PCI_ID_5434             0x00a81013      /* Id for CL-GD534 chip */
#define PCI_ID_5436             0x00ac1013      /* Id for CL-GD536 chip */
#define PCI_ID_BR_DEC21150      0x00221011      /* Id DEC 21150 PCI bridge */

#define PCI_ID_PRI_LAN		PCI_ID_LN_DEC21140 /* Id for Primary LAN */
#define PCI_ID_SEC_LAN		PCI_ID_LN_DEC21040 /* Id for Secondary LAN */

/* PCI Space Definitions  -- For configuring the RAVEN */

/* CPU to PCI definitions */

#define CPU2PCI_MSATT_MEM	0x00c2
#define CPU2PCI_MSATT_IO	0x00c0

#ifndef EXTENDED_VME

/* STANDARD ( PREP ) mapping of PCI space */

/* 
 *                      MAP FOR STANDARD vxWorks 
 * This maps: VME RANGE:     0x08000000 - (0x08000000 + VME_A32_SLV_SIZE - 1)
 *        to: PCI RANGE:     0x80000000 - 0x80000000 + VME_A32_SLV_SIZE-1
 *        to: MPU RANGE:     0x00000000 - VME_A32_SLV_SIZE-1
 */

/* setup address space 0 for PCI MEM space */
#define CPU2PCI_ADDR0_START_VAL	0xfd00
#define CPU2PCI_ADDR0_END_VAL	0xfdff
#define CPU2PCI_OFFSET0_VAL	((0x0-CPU2PCI_ADDR0_START_VAL) & 0xffff)

/* setup address space 1 for PCI I/O space */
#define CPU2PCI_ADDR1_START_VAL	0xfe00
#define CPU2PCI_ADDR1_END_VAL	0xfe7f
#define CPU2PCI_OFFSET1_VAL	((0x0-CPU2PCI_ADDR1_START_VAL) & 0xffff)
#define CPU2PCI_MSATT1_VAL	CPU2PCI_MSATT_IO

/* setup address space 2 for PCI MEM space -- maps VME address space */
#define CPU2PCI_ADDR2_START_VAL	CPU_PCI_MEM_UPPER_ADRS
#define CPU2PCI_ADDR2_END_VAL	0xfcff
#define CPU2PCI_OFFSET2_VAL	((0x0-CPU2PCI_ADDR2_START_VAL) & 0xffff)

/* setup address space 3 for PCI I/O space */
#define CPU2PCI_ADDR3_START_VAL	CPU_PCI_IO_UPPER_ADRS
#define CPU2PCI_ADDR3_END_VAL	0xbf7f
#define CPU2PCI_OFFSET3_VAL	((0x0-CPU2PCI_ADDR3_START_VAL) & 0xffff)

#else

/* EXTENDED VME PCI mapping */

/*
 *                      MAP FOR EXTENDED VME vxWorks
 * This maps: VME RANGE:     0x08000000 - (0x08000000 + VME_A32_SLV_SIZE - 1)
 *        to: PCI RANGE:     0x00000000 - VME_A32_SLV_SIZE-1
 *        to: MPU RANGE:     0x00000000 - VME_A32_SLV_SIZE-1
 */

/* setup address space 0 for PCI MEM space -- maps VME address space */
#define CPU2PCI_ADDR0_START_VAL	0x4000
#define CPU2PCI_ADDR0_END_VAL	0xfbff
#define CPU2PCI_OFFSET0_VAL	0x0

/* setup address space 1 for PCI MEM, for MPIC regs */
#define CPU2PCI_ADDR1_START_VAL	(MPIC_BASE_ADRS >>16)
#define CPU2PCI_ADDR1_END_VAL	(((MPIC_BASE_ADRS + 0x00ffffff) \
                                  >> 16) & 0x0000ffff)
#define CPU2PCI_OFFSET1_VAL	0x0
#define CPU2PCI_MSATT1_VAL	CPU2PCI_MSATT_MEM

/* setup address space 2 for PCI MEM -- maps reg. space */
#define CPU2PCI_ADDR2_START_VAL	(CPU_PCI_MEM_ADRS >>16)
#define CPU2PCI_ADDR2_END_VAL	(((CPU_PCI_MEM_ADRS + 0x00ffffff) \
                                  >> 16) & 0x0000ffff)
#define CPU2PCI_OFFSET2_VAL	0x0

/* setup address space 3 for PCI I/O */
#define CPU2PCI_ADDR3_START_VAL	(CPU_PCI_IO_ADRS >>16)
#define CPU2PCI_ADDR3_END_VAL	(((CPU_PCI_IO_ADRS + 0x007fffff) \
                                  >> 16) & 0x0000ffff)
#define CPU2PCI_OFFSET3_VAL	((0x0-CPU2PCI_ADDR3_START_VAL) & 0xffff)

#endif

/* defines that are used in romInit.s */

#define CPU2PCI_ADDR0_START	CPU2PCI_ADDR0_START_VAL
#define CPU2PCI_ADDR0_END	CPU2PCI_ADDR0_END_VAL
#define CPU2PCI_OFFSET0		CPU2PCI_OFFSET0_VAL
#define CPU2PCI_MSATT0		CPU2PCI_MSATT_MEM
#define CPU2PCI_ADDR1_START	CPU2PCI_ADDR1_START_VAL
#define CPU2PCI_ADDR1_END	CPU2PCI_ADDR1_END_VAL
#define CPU2PCI_OFFSET1		CPU2PCI_OFFSET1_VAL
#define CPU2PCI_MSATT1		CPU2PCI_MSATT1_VAL
#define CPU2PCI_ADDR2_START	CPU2PCI_ADDR2_START_VAL
#define CPU2PCI_ADDR2_END	CPU2PCI_ADDR2_END_VAL
#define CPU2PCI_OFFSET2		CPU2PCI_OFFSET2_VAL
#define CPU2PCI_MSATT2		CPU2PCI_MSATT_MEM
#define CPU2PCI_ADDR3_START	CPU2PCI_ADDR3_START_VAL
#define CPU2PCI_ADDR3_END	CPU2PCI_ADDR3_END_VAL
#define CPU2PCI_OFFSET3		CPU2PCI_OFFSET3_VAL
#define CPU2PCI_MSATT3		CPU2PCI_MSATT_IO

/* PCI to CPU definitions */

#ifdef LOCAL_MEM_AUTOSIZE
# define DRAM_SIZE		((ULONG)sysPhysMemTop() - LOCAL_MEM_LOCAL_ADRS)
#else
# define DRAM_SIZE		(LOCAL_MEM_SIZE - LOCAL_MEM_LOCAL_ADRS)
#endif

/* Raven PCI Slave Window definitions */

#define PCI2CPU_ADDR0_START     (PCI2DRAM_BASE_ADRS & 0xffff0000)
# define PCI2CPU_ADDR0_END       ((PCI2DRAM_BASE_ADRS + DRAM_SIZE \
                                  - 0x10001) >> 16)
#define PCI2CPU_ADDR0_RANGE     (PCI2CPU_ADDR0_START | PCI2CPU_ADDR0_END)
#define PCI2CPU_OFFSET0         (((0x0-PCI2DRAM_BASE_ADRS)>>16) & 0x0000ffff)
#define PCI2CPU_ATT0            0xf2

#define PCI2CPU_ADDR1_START     ((PCI2DRAM_BASE_ADRS + DRAM_SIZE \
                                  - 0x10000) & 0xffff0000)
#define PCI2CPU_ADDR1_END       ((PCI2DRAM_BASE_ADRS + DRAM_SIZE \
                                  - 0x10000) >> 16)
#define PCI2CPU_ADDR1_RANGE     (PCI2CPU_ADDR1_START | PCI2CPU_ADDR1_END)
#define PCI2CPU_OFFSET1         (((0x0-PCI2DRAM_BASE_ADRS)>>16) & 0x0000ffff)
#define PCI2CPU_ATT1            0xe2

/*
 * Address decoders 2 and 3 are not currently used, so they are
 * set to point to an address that is not used on the PCI bus
 */
#define PCI2CPU_ADDR2_RANGE     0xfff0fff0
#define PCI2CPU_OFFSET2         0x0
#define PCI2CPU_ATT2            0x0
#define PCI2CPU_ADDR3_RANGE     0xfff0fff0
#define PCI2CPU_OFFSET3         0x0
#define PCI2CPU_ATT3            0x0

/*
 * Allocate PCI Memory and I/O Space Offsets for PCI devices
 *
 * All devices on the primary and secondary busses are allocated 64 kb spaces.
 * The PMC Span can control up to four PMCs.
 */

#define SCSI_DEV_SPACE		0x10000
#define LAN_DEV_SPACE		0x20000
#define VGA_DEV_SPACE		0x30000
#define PMC_DEV_SPACE		0x40000
#define VME_DEV_SPACE		0x50000
#define LAN2_DEV_SPACE		0x60000
#define SCSI_DEV_SPACE2		0x70000
#define	SPAN_IO_DEV_SPACE	0x80000
#define	SPAN_IO_DEV_SIZE	0x40000
#define SPAN_MEM_DEV_SPACE	0x02000000
#define SPAN_MEM_DEV_SIZE	0x01000000
#define SPAN_PREF_DEV_SPACE	0x01000000
#define SPAN_PREF_DEV_SIZE	0x01000000

/* PCI view of PCI I/O Space for PCI devices */

#define PCI_IO_SCSI_ADRS	(PCI_IO_ADRS + SCSI_DEV_SPACE)	/* 53C825 */
#define PCI_IO_LN_ADRS		(PCI_IO_ADRS + LAN_DEV_SPACE)	/* PCnet */
#define PCI_IO_VGA_ADRS		(PCI_IO_ADRS + VGA_DEV_SPACE)	/* GD5434 */
#define PCI_IO_PMC_ADRS		(PCI_IO_ADRS + PMC_DEV_SPACE)	/* extra */
#define PCI_IO_LN2_ADRS		(PCI_IO_ADRS + LAN2_DEV_SPACE)  /* 21040   */
#define PCI_IO_SCSI_ADRS2	(PCI_IO_ADRS + SCSI_DEV_SPACE2) /* 53C825A */

/* PCI view of PCI Memory Space for PCI devices */

#define PCI_MEM_UNIVERSE_ADRS    (PCI_MEM_ADRS + VME_DEV_SPACE)	/* UNIVERSE */

#ifndef INCLUDE_MPIC
/* PCI IACK for ISA */

#define ISA_INTR_ACK_REG	(CPU_PCI_IACK_ADRS + 0x1ff0)
#endif /* INCLUDE_MPIC */

/* Allocated base address of HW devices as seen from CPU */

#define SCSI_BASE_ADRS		( CPU_PCI_IO_ADRS + SCSI_DEV_SPACE )
#define LAN_BASE_ADRS		( CPU_PCI_IO_ADRS + LAN_DEV_SPACE )
#define UNIVERSE_BASE_ADRS	( CPU_PCI_MEM_ADRS + VME_DEV_SPACE )
#define LAN2_BASE_ADRS		( CPU_PCI_IO_ADRS + LAN2_DEV_SPACE )
#define SCSI_BASE_ADRS2		( CPU_PCI_IO_ADRS + SCSI_DEV_SPACE2 )

/* pc87303 ISA super IO device (ISASIO) keybrd, serial, Parallel port */

#define pc87303_KBD_CTRL	(CPU_PCI_ISA_IO_ADRS + 0x0064)	/* keyboard */
#define pc87303_INDX_REG	(CPU_PCI_ISA_IO_ADRS + 0x0398)	/* index reg */
#define pc87303_DATA_REG	(CPU_PCI_ISA_IO_ADRS + 0x0399)	/* data reg */
#define pc87303_PP		(CPU_PCI_ISA_IO_ADRS + 0x03bc)	/* parallel */
#define pc87303_COM1		(CPU_PCI_ISA_IO_ADRS + 0x03f8)	/* serial 1 */
#define pc87303_COM2		(CPU_PCI_ISA_IO_ADRS + 0x02f8)	/* serial 2 */
#define pc87303_FDC		(CPU_PCI_ISA_IO_ADRS + 0x03f0)	/* floppy */

/* z85230 synchronous & Asynchronous serial communications chip */

#define z85230_PORTB_CTRL	(CPU_PCI_ISA_IO_ADRS + 0x0840)	/* serial 4 */
#define z85230_PORTB_DATA	(CPU_PCI_ISA_IO_ADRS + 0x0841)	
#define z85230_PORTA_CTRL	(CPU_PCI_ISA_IO_ADRS + 0x0842)	/* serial 3 */
#define z85230_PORTA_DATA	(CPU_PCI_ISA_IO_ADRS + 0x0843)

/* z8536 aux timer and I/O chip */

#define	z8536_PORTC_DATA	(CPU_PCI_ISA_IO_ADRS + 0x0844)
#define	z8536_PORTB_DATA	(CPU_PCI_ISA_IO_ADRS + 0x0845)
#define	z8536_PORTA_DATA	(CPU_PCI_ISA_IO_ADRS + 0x0846)
#define	z8536_PORT_CTRL		(CPU_PCI_ISA_IO_ADRS + 0x0847)
#define ZCIO_CNTRL_ADRS		(UINT8 *)(CPU_PCI_ISA_IO_ADRS + 0x847)
#define ZCIO_IACK_ADRS		(UINT8 *)(CPU_PCI_ISA_IO_ADRS + 0x84F)

/* m48TXX non volatile ram, RTC and watchdog timer */

#define m48TXX_LSB_REG		(CPU_PCI_ISA_IO_ADRS + 0x0074)
#define	m48TXX_MSB_REG		(CPU_PCI_ISA_IO_ADRS + 0x0075)
#define m48TXX_DAT_REG		(CPU_PCI_ISA_IO_ADRS + 0x0077)

/* CPU type */

#define CPU_TYPE                ((vxPvrGet() >> 16) & 0xffff)
#define CPU_TYPE_601		0x01	/* PPC 601 CPU */
#define CPU_TYPE_602		0x02	/* PPC 602 CPU */
#define CPU_TYPE_603		0x03	/* PPC 603 CPU */
#define CPU_TYPE_603E           0x06    /* PPC 603e CPU */
#define CPU_TYPE_603P           0x07    /* PPC 603p CPU */
#define CPU_TYPE_750            0x08    /* PPC 750 CPU */
#define CPU_TYPE_604		0x04	/* PPC 604 CPU */
#define CPU_TYPE_604E		0x09	/* PPC 604e CPU */
#define CPU_TYPE_604R		0x0A	/* PPC 604r CPU */

/* L2CR register (MPC750 - Arthur) */

#define MPC750_L2CR_E           0x80000000
#define MPC750_L2CR_256K        0x10000000
#define MPC750_L2CR_512K        0x20000000
#define MPC750_L2CR_1024K       0x30000000
#define MPC750_L2CR_I           0x00200000
#define MPC750_L2CR_SL          0x00008000
#define MPC750_L2CR_IP          0x00000001

/* System Configuration register */

#define	MV2600_GCR		((unsigned int *)(FALCON_BASE_ADRS + 0x08))
#define	MV2600_GCR_MSK		0x0000011e
#define	MV2600_GCR_FREF		0x00000008
#define MV2600_GCR_DRAM_70ns	0x00000000
#define MV2600_GCR_DRAM_60ns 	0x00000002
#define MV2600_GCR_DRAM_50ns 	0x00000006


#define MV2600_CCR_		(FALCON_BASE_ADRS + 0x400)
#define MV2600_CCR		((unsigned int *)(FALCON_BASE_ADRS + 0x400))

#define MV2600_CCR_ID_MSK	0xff000000	/* System ID mask */
#define MV2600_CCR_GEN2x	0xfe000000	/* genesis 2.x cpu type */
#define MV2600_CCR_2300         0xfd000000      /* hummingbird board type */

#define MV2600_CCR_CLK_MSK	0x00f00000	/* Bus clock Mask */
#define MV2600_CCR_CPU_CLK_66	0x00f00000 /* cpu external Bus clock 66 Mhz */
#define MV2600_CCR_CPU_CLK_60	0x00e00000 /* cpu external Bus clock 60 Mhz */
#define MV2600_CCR_CPU_CLK_50	0x00d00000 /* cpu external Bus clock 50 Mhz */

#define MV2600_CCR_SYSXC_MSK	0x000f0000	/* lookaside l2 cache mask */
#define MV2600_CCR_SYSXC_256	0x000e0000	/* lookaside 256kb L2 cache */
#define MV2600_CCR_SYSXC_512	0x000d0000	/* lookaside 512kb L2 cache */
#define MV2600_CCR_SYSXC_1024	0x000c0000	/* lookaside 1Mb L2 cache */
#define MV2600_CCR_SYSXC_NC	0x000f0000	/* lookaside no cache */

#define MV2600_CCR_P0STAT_MSK	0x0000f000	/* in-line l2 cache mask */
#define MV2600_CCR_P0STAT_256	0x00006000	/* in-line 256kb L2 cache */
#define MV2600_CCR_P0STAT_512	0x00005000	/* in-line 512kb L2 cache */
#define MV2600_CCR_P0STAT_1024	0x00004000	/* in-line 1Mb L2 cache */
#define MV2600_CCR_P0STAT_NC	0x00007000	/* in-line no cache */

/* DRAM configuration registers */

#define MV2600_MCR_		(FALCON_BASE_ADRS + 0x404)
#define MV2600_MCR		((unsigned int *)(FALCON_BASE_ADRS + 0x404))
#define MV2600_MCR_L2TYPE_MSK   0x0000F000
#define MV2600_MCR_L2TYPE_LWP   0x00000000
#define MV2600_MCR_L2TYPE_BP    0x00001000
#define MV2600_MCR_L2TYPE_LWNP  0x00002000
#define MV2600_MCR_L2TYPE_BNP   0x00003000
#define MV2600_MCR_L2PLL_MSK    0x00000F00

#define MV2600_MCR_MSK		0x03000000
#define MV2600_MCR_DRAM_50ns	0x03000000
#define MV2600_MCR_DRAM_60ns	0x01000000
#define MV2600_MCR_DRAM_70ns	0x00000000

#define DRAM_70ns		0x0
#define DRAM_60ns 		0x02
#define DRAM_50ns 		0x06

#define DRAM_REG_SIZE           (FALCON_BASE_ADRS + 0x10)
#define DRAM_REG_BASE           (FALCON_BASE_ADRS + 0x18)

/*
 * Base Module Feature Register
 *
 * The bits in this register use negative logic, i.e., a feature is present
 * when its corresponding bit is cleared, not set.  Not all bits are used
 * by all base modules; each base module has its own set of features.
 */

#define MV2600_CCR_OLD		((char *)(CPU_PCI_ISA_IO_ADRS + 0x0800))
#define MV2600_BMFR		((char *)(CPU_PCI_ISA_IO_ADRS + 0x0802))

#define MV2600_BMFR_GIOP	0x80	/* genio Module */
#define MV2600_BMFR_SCCP	0x40	/* z85230 sync serial Port */
#define MV2600_BMFR_PMC2P       0x20    /* pmc #2 Present (MVME2300) */
#define	MV2600_BMFR_PMCP	0x10	/* pmc Present */
#define MV2600_BMFR_VMEP	0x08	/* vme bus Present */
#define MV2600_BMFR_GFXP	0x04	/* graphics Present */
#define MV2600_BMFR_LANP	0x02	/* ethernet Present */
#define MV2600_BMFR_SCIP	0x01	/* scsi present */

#ifdef MV2300
# define MV2600_BMFR_BRGP	0x80	/* PMC Span (Bridge) present */
#else
# define MV2600_BMFR_BRGP	0x20	/* PMC Span (Bridge) present */
#endif /* MV2300 */

#define DEVICE_PRESENT(x) 	(!((*MV2600_BMFR) & (x)))

/* Base Module Status Register */

#define	MV2600_BMSR		((char *)(CPU_PCI_ISA_IO_ADRS + 0x0803))

#define MV2600_BMSR_2300	0xf9    /* Hummingbird */
#define MV2600_BMSR_2300_SC	0xfa    /* mv2300SC (has 21143) */
#define MV2600_BMSR_SG712	0xfb	/* Slim Gen with 712 */
#define	MV2600_BMSR_SG761	0xfc	/* Slim Gen with 761 */
#define MV2600_BMSR_FG712	0xfd	/* Full Gen with 712 */
#define MV2600_BMSR_FG761	0xfe	/* Full Gen with 761 */
#define MV2600_BMSR_1600	0xff	/* MV1600 */

/* Assembly define for L2 cache */

#define MV2600_SXCCR_A		(FALCON_BASE_ADRS + 0x8000)

/* defines for L2 cache routines */

#define MV2600_SXCCR		((unsigned char *)(FALCON_BASE_ADRS + 0x8000))

#define L2_DISABLE		0x80
#define L2_RESET		0x40
#define L2_ENABLE		0x80
#define L2_FLUSH		0x10
#define L2_END_FLUSH		0x10
#define L2_FLUSH_LOOP		4100

/* z8536 I/O port bit mapping */

#define	z8536_PORTA_BRDFAIL	0x40
#define	z8536_PORTB_FUSE	0x40
#define	z8536_PORTB_ABORT	0x80

/*
 * Raven Extensions to Standard PCI Header
 *
 * Type declarations for the PCI Header and the macros in regards to the
 * PCI BUS.  These definitions have been made with respect to PCI LOCAL
 * BUS SPECIFICATION REVISION 2.1.  Every device on the PCI BUS has to
 * support 256 bytes of configuration space of which the first 64 bytes
 * are a predefined header portion defined by the PCI commitee.  Bytes
 * 64 to 255 are dedicated to the device specific registers.