mv2600.h

VxWorkS下 MV2604的BSP源代码

/* mv2600.h - Motorola PowerPlus board header */

/* Copyright 1984-2001 Wind River Systems, Inc. */
/* Copyright 1996,1997,1998,1999 Motorola, Inc. All Rights Reserved */

/*
modification history
--------------------
02r,21oct01,dtr  Changing default secondary scsi id.
02q,09oct01,dat  SPR 24258 adding prototypes for unique functions
02p,16sep01,dat  Use of WRS_ASM macro
02o,11oct99,dmw  Removed VME_A32_MSTR_LOCAL, moved to config.h
02n,27sep99,stv	 added reporting of configuration error for mv2300 (SPR 28572). 
02m,18aug99,dmw  Added 21143 define and mv2300SC define.
02l,16feb99,mas  added RAVEN_MPC_WDT1CNTL/_WDT2CNTL defs for Raven3 (SPR 24453)
02k,10feb99,tm   Fixed duplicate definition of PCI2DRAM_BASE_ADRS (SPR 21488)
02j,07aug98,tb   Fixed support for SM_OFF_BOARD
02i,07aug98,tb   Added TAS support which uses VMEbus RMW
02h,07aug98,scb  added support for MPC750 (Arthur).
02g,13oct98,dat  SPR 20654, added ravenAuxClk for mv2300
02f,17jul98,tm   added PCI_ID_PRI_LAN, PCI_ID_SEC_LAN for PCI AutoConfig
02e,12jun98,mas  made MV2600_BMFR_BRGP define board dependent (SPR 21402).
02d,15apr98,db   added support for floppy disk driver.
02c,14apr98,ms_  merged Motorola mv2700 support
02b,06apr98,dat  added PCI_ID_SEC_SCSI and INCLUDE_PCI
02a,07nov97,mas/ corrected VME range comments on A32 slave window; changed VME
	    tb   A24 base address to 0xff000000; enabled 64-bit PCI xfers for
		 VME A32 slave window (SPR 9726).
01z,05nov97,mas  made all VME master windows D64 with write posting (SPR 9717).
01y,31oct97,mas  fixed P2P_NPMEM_SPACE_LIMIT_ADRS definition (SPR 9654).
01x,10sep97,mas  added PMC_INT_LVL1 - 4 for non-MPIC configurations.
01w,02sep97,mas  removed un-needed check of VME_A32_MSTR_BUS, VME_A24_MSTR_BUS.
01v,14aug97,mas  Extended VME addressing is now default; no slave VME A24 space
		 (for cumulative patch release 9/97).
01u,01aug97,mas  added primary PCI bus interrupt vector numbers PCI_PRI_INTA_VEC
		 PCI_PRI_INTB_VEC, PCI_PRI_INTC_VEC, PCI_PRI_INTD_VEC (SPR 9063)
01t,25jul97,srr/ added 604r (Mach 5) type define CPU_TYPE_604R (SPR 8911).
	    mas
01s,17jul97,mas  added FALCON_DRAM_ATTR and DRAM_SIZE (SPR 8824).
01r,14jul97,mas  added IS_VME_ADDRESS and IS_PCI_ADDRESS defs (SPR 8022).
		 Added reg bit masks for MPC Error Enable/Status and PCI Status.
01q,09jul97,mas  added UNIV_VOWN_INT_VEC definition (SPR 8896); added 'volatile'
		 to in-line assembler macros; disabled write posting in Universe
		 VME slave setup (SPR 8897); NCR810_DELAY_MULT is now defined as
		 actual loop count (SPR 8842).
01p,05jun97,mas  added support for serial ports 3 & 4 (Z85230 ESCC). (SPR 8566)
01o,29may97,srr  Add RAVEN macros for vxMemProbe, chg'd mislabelled macros
		 (MCG MR #67, 69)
01n,12may97,dat  moving things between config.h and mv2600.h
01m,09may97,mas  added extended VME addressing (SPR 8410).
		 added z8536 I/O port bit mappings (SPR 8432).
01l,29apr97,dat  added PCI_CLINE_SZ and PCI_LAT_TIMER, from old pci.h
01k,24apr97,mas  added Motorola support for MPIC (SPR 8170).
01j,11apr97,dat  moved macros between here and config.h.  User configurable
		 macros are in config.h, fixed ones are here in mv2600.h
01i,10apr97,mas  added defs for EIEIO_SYNC, EIEIO, PCI_PRIMARY_CAR,
                 PCI_PRIMARY_CDR, CNFG_PMCSPAN_ADRS, PCI_PRIMARY_BUS,
                 PCI_SECONDARY_BUS, PCI_SUBORD_BUS, MV2600_BMFR_BRGP,
                 PCI_ID_BR_DEC21150, PCI_MAX_BUS and PMC_SPAN; updated 
		 PCI_ID_IBC (SPR 8226).
01h,01apr97,dat  new VME configuration macros, SPR 8271
01g,18feb97,mas  added DEC_CLOCK_FREQ definition; changed UNIV_SW_IACK_INT_VEC
		 to UNIV_PCI_SW_INT_VEC; added UNIV_VME_SW_IACK_INT_VEC
		 (SPR 7772, 7811).
01f,10jan97,dat  chg'd BBRAM_SIZE, to exclude RTC chip
01e,02jan97,dat  mod history fix, chg'd MV1600_SIOP* to MV2600_SIOP*
01d,18dec96,tb   [Motorola] added MV2600_MCR_ (SPR 7525).
01c,17dec96,mas  moved raven.h contents to this file (SPR 7525).
01b,14jul96,rcp  modified the reference to the PCI configuration regs.
01a,14jul96,mot  written. (from ver 01f, mv1600.h)
*/

/*
This file contains I/O addresses and related constants for the
Motorola PowerPlus VME board. 
*/

#ifndef	INCmv260xh
#define	INCmv260xh

#ifdef __cplusplus
extern "C" {
#endif

/* Prototypes for special BSP functions, may be useful for customer */

#ifndef _ASMLANGUAGE
void	sysUsDelay (UINT32);	/* spin delay for X microseconds */
int	sysGetBusSpd (void);	/* return MPC bus speed */
UINT	sysGetMpuSpd (void);	/* return MPU speed */
void	sysDebugMsg (char *);	/* print message using polled mode */
#endif /* _ASMLANGUAGE*/

/* Aux Clock available only with MPIC for mv2300 */

#if defined(MV2300) && (!defined(INCLUDE_MPIC)) && defined(INCLUDE_AUXCLK)
#   error "INCLUDE_AUXCLK not available on MV2300 without INCLUDE_MPIC"
#endif				

#define INCLUDE_PCI		/* always include pci */

/* Floppy disk support */

#define FD_MAX_DRIVES	4
#define FD_BASE_ADDR	pc87303_FDC	/* See super I/O section */
#define FD_DMA_CHAN	2

#ifdef	INCLUDE_FD
#   ifndef	INCLUDE_DOSFS
#       define	INCLUDE_DOSFS	/* file system to be used */
#   endif
#   ifndef	INCLUDE_ISADMA
#       define	INCLUDE_ISADMA	/* uses ISA DMA driver */
#   endif
#   ifndef _ASMLANGUAGE
#	include "blkIo.h"
	/* to stop compiler warnings */
	IMPORT STATUS	fdDrv (UINT, UINT);
	IMPORT BLK_DEV*	fdDevCreate (UINT, UINT, UINT, UINT);
#   endif
#endif


/* Boot Line parameters are stored in the 2nd 256 byte block */

#undef	NV_BOOT_OFFSET
#define NV_BOOT_OFFSET		256 /* skip 1st 256 bytes */
#define NV_RAM_SIZE    		BBRAM_SIZE		
#define NV_RAM_ADRS    		((char *) BBRAM_ADRS)
#define NV_RAM_INTRVL           1

/* Dec 21140 (unit 0) vector and level */

#define	INT_VEC_DC	LN_INT_VEC 		/* interrupt vector */
#define	INT_LVL_DC	LN_INT_LVL		/* interrupt level */
#define DC_DATA_WIDTH   NONE			/* all data widths */
#define IO_ADRS_DC      LAN_BASE_ADRS		/* Base adrs */
#define DC_RAM_PCI_ADRS PCI2DRAM_BASE_ADRS	/* RAM seen from PCI */

/* Dec 21040 (unit 1) vector and level */

#define INT_VEC_DC1     LN2_INT_VEC		/* interrupt vector */
#define INT_LVL_DC1     PMC_INT_LVL2		/* interrupt level */
#define DC1_DATA_WIDTH  NONE			/* all data widths */
#define IO_ADRS_DC1     LAN2_BASE_ADRS		/* Base adrs */
#define DC1_RAM_PCI_ADRS        PCI2DRAM_BASE_ADRS /* RAM seen from PCI */

/* PMC-Span setup values */

#define P2P_IO_SPACE_BASE_ADRS  ((P2P_IO_BASE & 0x0000F000) >> 8)
#define P2P_IO_SPACE_LIMIT_ADRS ((P2P_IO_BASE + P2P_IO_SIZE - 1) & 0x0000F000)
#define	P2P_IO_HI16_BASE_ADRS   ((P2P_IO_BASE & 0xFFFF0000) >> 16)
#define	P2P_IO_HI16_LIMIT_ADRS  ((P2P_IO_BASE + P2P_IO_SIZE - 1) & 0xFFFF0000)
#define P2P_NPMEM_SPACE_BASE_ADRS ((P2P_NONPREF_MEM_BASE & 0xFFFF0000) >> 16)
#define P2P_NPMEM_SPACE_LIMIT_ADRS ((P2P_NONPREF_MEM_BASE + \
                                     P2P_NONPREF_MEM_SIZE - 1) & 0xFFFF0000)
#define P2P_PREF_MEM_BASE_ADRS  ((P2P_PREF_MEM_BASE & 0xFFFF0000) >> 16)
#define P2P_PREF_MEM_LIMIT_ADRS ((P2P_PREF_MEM_BASE + P2P_PREF_MEM_SIZE - 1) & \
                                 0xFFFF0000)

/* PCI I/O function defines */

#define INT_NUM_IRQ0            INT_VEC_IRQ0

#ifndef _ASMLANGUAGE

#ifndef PCI_IN_BYTE
#define PCI_IN_BYTE(x)          sysPciInByte (x)
IMPORT  UINT8                   sysPciInByte  (UINT32 address);
#endif
#ifndef PCI_IN_WORD
#define PCI_IN_WORD(x)          sysPciInWord (x)
IMPORT  UINT16                  sysPciInWord  (UINT32 address);
#endif
#ifndef PCI_IN_LONG
#define PCI_IN_LONG(x)          sysPciInLong (x)
IMPORT  UINT32                  sysPciInLong  (UINT32 address);
#endif
#ifndef PCI_OUT_BYTE
#define PCI_OUT_BYTE(x,y)       sysPciOutByte (x,y)
IMPORT  void                    sysPciOutByte (UINT32 address, UINT8  data);
#endif
#ifndef PCI_OUT_WORD
#define PCI_OUT_WORD(x,y)       sysPciOutWord (x,y)
IMPORT  void                    sysPciOutWord (UINT32 address, UINT16 data);
#endif
#ifndef PCI_OUT_LONG
#define PCI_OUT_LONG(x,y)       sysPciOutLong (x,y)
IMPORT  void                    sysPciOutLong (UINT32 address, UINT32 data);
#endif

#endif  /* _ASMLANGUAGE */

/* Cache Line Size - 32 32-bit value = 128 bytes */

#define PCI_CLINE_SZ		0x20

/* Latency Timer value - 255 PCI clocks */

#define PCI_LAT_TIMER		0xff

/* clock rates */

/* Calculate Memory Bus Rate in Hertz */

#define MEMORY_BUS_SPEED                ( sysGetBusSpd() * 1000000)

/* System clock (decrementer counter) frequency determination */

#define DEC_CLOCK_FREQ          ((sysGetBusSpd()==67)?66666666:33333333)

/* CIO clocks and stuff */

#define	CIO_RESET_DELAY		5000
#define	ZCIO_HZ			2500000 /* 2.5 MHz clock */
#define	CIO_INT_VEC		9
#define	Z8536_TC		ZCIO_HZ

/*
 * The PowerPC Decrementer is used as the system clock.
 * It is always included in this BSP.  The following defines
 * are used by the system clock library.
 */

#define SYS_CLK_RATE_MIN  	10		/* minimum system clock rate */
#define SYS_CLK_RATE_MAX  	5000		/* maximum system clock rate */

/*
 * This macro returns the positive difference between two signed ints.
 * Useful for determining delta between two successive decrementer reads.
 */

#define DELTA(a,b)	( abs((int)a - (int)b) )

/*
 * Auxiliary Clock support is an optional feature that is not supported
 * by all BSPs.  The following defines are used by the aux clock library.
 */

#define AUX_CLK_RATE_MIN  	40		/* min auxiliary clock */
#define AUX_CLK_RATE_MAX	5000		/* max auxiliary clock rate */

/*
 * Shared Memory Interrupt Type.
 * Interrupt this target with a 1-byte write mailbox.
 * VME_A32 space, address based on procNum, value is SIG1_INTR_SET.
 */

#define SM_INT_ARG1 	VME_AM_EXT_SUP_DATA
#define SM_INT_ARG2 	(VME_A32_REG_BASE +(sysProcNumGet() * VME_A32_REG_SIZE))
#define SM_INT_ARG3	SIG1_INTR_SET

/*
 * Semaphore Test-and-Set Register as seen from a slave
 * Only used with a special version of sysBusTas().
 */

#define OFFBRD_VME_SEM_REG1	(CPU_VME_WINDOW_REG_BASE + \
				 (CPU_VME_SEM_REG1 - CPU_VME_HW_REGS_BASE)) 

/* Common I/O synchronizing instructions */

#ifndef EIEIO_SYNC
# define EIEIO_SYNC  WRS_ASM (" eieio; sync")
#endif  /* EIEIO_SYNC */
#ifndef EIEIO
# define EIEIO    WRS_ASM (" eieio")
#endif  /* EIEIO */

#ifndef EXTENDED_VME

/* Psuedo PREP memory map as seen from CPU */

#define CPU_PCI_ISA_IO_ADRS     0x80000000      /* base of ISA I/O space */
#define CPU_PCI_ISA_MEM_ADRS    0xc0000000      /* base of ISA mem space */
#define CPU_PCI_IO_ADRS         0x81000000      /* base of PCI I/O space */
#define CPU_PCI_MEM_ADRS        0xc1000000      /* base of PCI mem space */

#else

/* Extended VME memory map as seen from the CPU */

#define CPU_PCI_ISA_IO_ADRS     0xfe000000      /* base of ISA I/O space */
#define CPU_PCI_ISA_MEM_ADRS    0xfd000000      /* base of ISA mem space */
#define CPU_PCI_IO_ADRS         CPU_PCI_ISA_IO_ADRS  /* base of PCI I/O space */
#define CPU_PCI_MEM_ADRS        CPU_PCI_ISA_MEM_ADRS /* base of PCI mem space */
#endif

#define CPU_PCI_ISA_IO_SIZE	0x00010000	/* 64 kbytes */
#define CPU_PCI_IO_SIZE		0x00800000	/* 8 meg */
#define CPU_PCI_IO_UPPER_ADRS   (CPU_PCI_ISA_IO_ADRS>>16)
#define CPUCRA_HI               (CPU_PCI_ISA_IO_ADRS>>16)
#define CPUCRA_LO               0x0800

#define CPU_PCI_ISA_MEM_SIZE	0x00010000	/* 64 kbytes */
#define CPU_PCI_MEM_SIZE	0x01000000	/* 16 meg */
#define CPU_PCI_MEM_UPPER_ADRS  (CPU_PCI_ISA_MEM_ADRS>>16)

/*
 * PCI MASTER MEMORY WINDOW LIMITS
 *
 * These values are strictly defined by the base memory addresses and window
 * sizes of the spaces defined above.  These values must be correct for the
 * sysBusProbe() memory range checks for the PCI bus to work properly.
 */

#ifndef EXTENDED_VME
#  define PCI_MSTR_LO_ADRS      (CPU_PCI_ISA_IO_ADRS)
#  define PCI_MSTR_HI_ADRS      (CPU_PCI_MEM_ADRS + CPU_PCI_MEM_SIZE)
#else
#  define PCI_MSTR_LO_ADRS      (CPU_PCI_MEM_ADRS)
#  define PCI_MSTR_HI_ADRS      (CPU_PCI_IO_ADRS + CPU_PCI_IO_SIZE)
#endif  /* EXTENDED_VME */

#ifndef INCLUDE_MPIC

/*
 * All starting addresses are correct except for CPU_PCI_IACK_ADRS.
 * This address was selected to allow a minimum 8k memory range
 * for the MMU table entry.
 */

#define CPU_PCI_IACK_ADRS	0xbfffe000	/* covers PCI IACK space */
						/* base = 0xbffffff0; */
#define CPU_PCI_IACK_SIZE	0x00002000	/* 8 kbytes */

#define MPIC_ADDR(reg)		(MPIC_BASE_ADRS + reg)
#define MPIC_GLOBAL_CONFIG_REG	0x01020
#define RESET_CNTRLR		0x80000000

#endif  /* INCLUDE_MPIC */

/* Base address of HW devices as seen from CPU */

#define FALCON_BASE_ADRS	0xfef80000
#define	FALCON_REG_SIZE		0x00010000
#define FALCON_BASE_UPPER_ADRS	(FALCON_BASE_ADRS>>16)
#define FALCON_DRAM_ATTR	0xfef80010
#define RAVEN_BASE_ADRS		0xfeff0000
#define	RAVEN_REG_SIZE		0x00010000
#define	FLASH_BASE_ADRS		0xFF000000
#define	FLASH_MEM_SIZE		0x01000000

/* MPIC configuration defines */

#define MPIC_BASE_ADRS		0xfc000000
#define MPIC_REG_SIZE		0x00040000
#ifndef EXTENDED_VME 
#  define MPIC_PCI_BASE_ADRS	( MPIC_BASE_ADRS - CPU_PCI_ISA_MEM_ADRS )
#else
#  define MPIC_PCI_BASE_ADRS	MPIC_BASE_ADRS
#endif /* Extended VME config */

/* memory map as seen on the PCI bus */

#define PCI_CNFG_ADRS		0x00800000      /* base of PCI config space */
#ifndef EXTENDED_VME
#  define PCI_IO_ADRS		0x01000000      /* base of PCI I/O address */
#  define PCI_MEM_ADRS		0x01000000      /* base of PCI MEM address */
#  define PCI2DRAM_BASE_ADRS	0x80000000      /* memory seen from PCI bus */
#else
#  define PCI_IO_ADRS		0x00000000      /* base of PCI I/O address */
#  define PCI_MEM_ADRS		CPU_PCI_MEM_ADRS  /* base of PCI MEM address */
#  define PCI2DRAM_BASE_ADRS	0x00000000      /* memory seen from PCI bus */
#endif /* Extended VME config */

/*
 * Primary PCI bus configuration space address and data register addresses
 * as seen by the CPU on the local bus.
 */

#ifndef EXTENDED_VME
#  define PCI_PRIMARY_CAR	0x80000CF8 /* PCI config address register */
#  define PCI_PRIMARY_CDR	0x80000CFC /* PCI config data    register */
#else
#  define PCI_PRIMARY_CAR	0xFE000CF8 /* PCI config address register */
#  define PCI_PRIMARY_CDR	0xFE000CFC /* PCI config data    register */
#endif /* Extended VME config */


/*
 * PCI Config Space device addresses based on their device number
 *
 * Bit 32 is set to enable CONFIG_DATA accesses to PCI Cycles
 */

#define CNFG_START_SEARCH	0x5800     /* PCI Space starting offset */
#define CNFG_RAVEN_ADRS		CPU_PCI_ISA_IO_ADRS /* Raven PCI and MPIC ASIC*/
#define CNFG_IBC_ADRS		0x80005800 /* IBC */
#define CNFG_SCSI_ADRS		0x80006000 /* SCSI */
#define CNFG_UNIVERSE_ADRS	0x80006800 /* VMEbus Bridge */
#define CNFG_LN_ADRS		0x80007000 /* Ethernet Device */