rominit.s

VxWorkS下 MV2604的BSP源代码

	bc	12,2,.sioInit_87308_fa	/* if equal, yes, goto to 87308 init */

	addi	r3,r6,0x015C		/* adjust to superI/O 87308 base */
	addi	r4,r0,SIO_SIDPNP	/* select SID register */
	bl	.sio_br
	andi.	r3,r3,SIO_SIDMASK	/* mask to identifier bits */
	cmpli	0,0,r3,SIO_SID87308	/* is it a 87308? */
	addi	r4,r0,0x015C		/* adjust to superI/O 87308 base */
	bc	12,2,.sioInit_87308_fa	/* if equal, yes, goto to 87308 init */

	b	.sioInit_done		/* don't know what to do... */

.sioInit_87308_fa:
	add	r6,r6,r4		/* add offset to base */
	or	r3,r6,r6		/* make a copy */
/*
;	enable PS/2 mode in SIO configuration register #1
*/
	addi	r4,r0,SIO_CNFG1		/* select CNFG1 */
	bl	.sio_br
	andi.	r5,r3,0xFB		/* keep all but PS/2-AT mode bit */
	addi	r4,r0,SIO_CNFG1		/* select CNFG1 */
	or	r3,r6,r6		/* make a copy */
	bl	.sio_bw
/*
;	KBC (LUN 0)
*/
	addi	r4,r0,SIO_LUNINDEX	/* select KBC LUN */
	addi	r5,r0,0x0
	bl	.sio_bw
	addi	r4,r0,SIO_ACTIVATE	/* disable KBC */
	addi	r5,r0,SIO_LUNDISABLE
	bl	.sio_bw
	addi	r4,r0,SIO_LUNCNFGR	/* initialize KBC clock to 8 Mhz */
	addi	r5,r0,0x0
	bl	.sio_bw
	addi	r4,r0,SIO_DBASEHI	/* initialize KBC data base address to 0x060 */
	addi	r5,r0,0x00
	bl	.sio_bw
	addi	r4,r0,SIO_DBASELO
	addi	r5,r0,0x60
	bl	.sio_bw
	addi	r4,r0,SIO_CBASEHI	/* initialize KBC command base address to 0x064 */
	addi	r5,r0,0x00
	bl	.sio_bw
	addi	r4,r0,SIO_CBASELO
	addi	r5,r0,0x64
	bl	.sio_bw
	addi	r4,r0,SIO_ACTIVATE	/* enable KBC */
	addi	r5,r0,SIO_LUNENABLE
	bl	.sio_bw
/*
;	FDC (LUN 3)
*/
	addi	r4,r0,SIO_LUNINDEX	/* select FDC LUN */
	addi	r5,r0,0x3
	bl	.sio_bw
	addi	r4,r0,SIO_IOBASEHI	/* initialize FDC address to 0x3F0 */
	addi	r5,r0,0x03
	bl	.sio_bw
	addi	r4,r0,SIO_IOBASELO
	addi	r5,r0,0xF0
	bl	.sio_bw
	addi	r4,r0,SIO_LUNCNFGR	/* initialize FDC to PS-2 mode */
	addi	r5,r0,0x40
	bl	.sio_bw
	addi	r4,r0,SIO_ACTIVATE	/* enable FDC */
	addi	r5,r0,SIO_LUNENABLE
	bl	.sio_bw
/*
;	COM2 (LUN 5)
*/
	addi	r4,r0,SIO_LUNINDEX	/* select COM2 LUN */
	addi	r5,r0,0x5
	bl	.sio_bw
	addi	r4,r0,SIO_IOBASEHI	/* initialize COM2 address to 0x2F8 */
	addi	r5,r0,0x02
	bl	.sio_bw
	addi	r4,r0,SIO_IOBASELO
	addi	r5,r0,0xF8
	bl	.sio_bw
	addi	r4,r0,SIO_ACTIVATE	/* enable COM2 */
	addi	r5,r0,SIO_LUNENABLE
	bl	.sio_bw
/*
;	COM1 (LUN 6)
*/
	addi	r4,r0,SIO_LUNINDEX	/* select COM1 LUN */
	addi	r5,r0,0x6
	bl	.sio_bw
	addi	r4,r0,SIO_IOBASEHI	/* initialize COM1 address to 0x3F8 */
	addi	r5,r0,0x03
	bl	.sio_bw
	addi	r4,r0,SIO_IOBASELO
	addi	r5,r0,0xF8
	bl	.sio_bw
	addi	r4,r0,SIO_ACTIVATE	/* enable COM1 */
	addi	r5,r0,SIO_LUNENABLE
	bl	.sio_bw
/*
;	LPT (LUN 4)
*/
	addi	r4,r0,SIO_LUNINDEX	/* select LPT LUN */
	addi	r5,r0,0x4
	bl	.sio_bw
	addi	r4,r0,SIO_IOBASEHI	/* initialize LPT address to 0x3BC */
	addi	r5,r0,0x03
	bl	.sio_bw
	addi	r4,r0,SIO_IOBASELO
	addi	r5,r0,0xBC
	bl	.sio_bw
	addi	r4,r0,SIO_LUNCNFGR	/* Put in 87303 compatible mode. */
	addi	r5,r0,0x12
	bl	.sio_bw
	addi	r4,r0,SIO_ACTIVATE	/* enable LPT */
	addi	r5,r0,SIO_LUNENABLE
	bl	.sio_bw
	b	.sioInit_done		/* branch to done */
/*
;	87303/87323 initialization
*/
.sioInit_87303:
	add	r6,r6,r4		/* add offset to base */
	or	r3,r6,r6		/* make a copy */

	addi	r4,r0,0			/* initialize FER with 0x4F */
	addi	r5,r0,0x4F
	bl	.sio_bw
	addi	r4,r0,1			/* initialize FAR with 0x11 */
	addi	r5,r0,0x11
	bl	.sio_bw
	addi	r4,r0,9			/* initialize ASC to PS-2 mode */
	addi	r5,r0,0x40
	bl	.sio_bw
	addi	r4,r0,5			/* retrieve KBC/RTC control register */
	bl	.sio_br
	andi.	r5,r3,0xD0		/* keep KBC_CSS, CSE */
	ori	r5,r5,0x0F		/* add RTC_E, PAE, KBC_SC, KBC_E */
	or	r3,r6,r6		/* load base address of SIO device */
	bl	.sio_bw
.sioInit_done:
/*
;	for VIPER H/W we need to enable the CSx registers of the SIO
;	to point to the MCG classic RTC/NVRAM device
*/
	addis	r3,r0,CPUCRA_HI		/* load addr to CPU config reg */
	ori	r3,r3,CPUCRA_LO
	lbz	r3,0(r3)		/* read CPU config reg */
	andi.	r3,r3,PID_MASK		/* mask off unwanted data bits */
	cmpli	0,0,r3,PID_VIPER	/* is it a VIPER? */
	bc	4,2,.sioInit_viper_no	/* if not equal, no, branch */

	/*
	 *	Get base addr of ISA I/O space
	 */
	lis	r3,HI(CPU_PCI_ISA_IO_ADRS)
	ori	r3,r3,LO(CPU_PCI_ISA_IO_ADRS)

	addi	r3,r3,0x015C		/* adjust to superI/O 87308 base */
	or	r6,r3,r3		/* make a copy */
/*
;	CS0
*/
	addi	r4,r0,SIO_PCSCI		/* select PCSCIR */
	addi	r5,r0,0x00
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCD		/* select PCSCDR */
	addi	r5,r0,0x00
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCI		/* select PCSCIR */
	addi	r5,r0,0x01
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCD		/* select PCSCDR */
	addi	r5,r0,0x76
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCI		/* select PCSCIR */
	addi	r5,r0,0x02
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCD		/* select PCSCDR */
	addi	r5,r0,0x40
	bl	.sio_bw
/*
;	CS1
*/
	addi	r4,r0,SIO_PCSCI		/* select PCSCIR */
	addi	r5,r0,0x05
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCD		/* select PCSCDR */
	addi	r5,r0,0x00
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCI		/* select PCSCIR */
	addi	r5,r0,0x05
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCD		/* select PCSCDR */
	addi	r5,r0,0x70
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCI		/* select PCSCIR */
	addi	r5,r0,0x06
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCD		/* select PCSCDR */
	addi	r5,r0,0x1C
	bl	.sio_bw
/*
;	CS2
*/
	addi	r4,r0,SIO_PCSCI		/* select PCSCIR */
	addi	r5,r0,0x08
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCD		/* select PCSCDR */
	addi	r5,r0,0x00
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCI		/* select PCSCIR */
	addi	r5,r0,0x09
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCD		/* select PCSCDR */
	addi	r5,r0,0x71
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCI		/* select PCSCIR */
	addi	r5,r0,0x0A
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCD		/* select PCSCDR */
	addi	r5,r0,0x1C
	bl	.sio_bw
/*
;	PMC (LUN 8)
*/
	addi	r4,r0,SIO_LUNINDEX	/* select PMC LUN */
	addi	r5,r0,0x8
	bl	.sio_bw
	addi	r4,r0,SIO_IOBASEHI	/* initialize PMC address to 0x460 */
	addi	r5,r0,0x04
	bl	.sio_bw
	addi	r4,r0,SIO_IOBASELO
	addi	r5,r0,0x60
	bl	.sio_bw
	addi	r4,r0,SIO_ACTIVATE	/* enable PMC */
	addi	r5,r0,SIO_LUNENABLE
	bl	.sio_bw
.sioInit_viper_no:
	mtspr	8,r7			/* restore link register */
	bclr	20,0			/* return to caller */
/*
; routine: sio_bw
;	this function writes a register to the SIO chip
; call:
;	sio_bw(sioaddr, regnum, value)
; return:
;	none
*/
.sio_bw:
	stb	r4,0(r3)	/* write index register with register offset */
	eieio
	sync
	stb	r5,1(r3)	/* 1st write */
	eieio
	sync
	stb	r5,1(r3)	/* 2nd write */
	eieio
	sync
	bclr	20,0		/* return to caller */
/*
; routine: sio_br
;	this function reads a register from the SIO chip
; call:
;	sioInit(sioaddr, regnum)
; return:
;	register value
*/
.sio_br:
	stb	r4,0(r3)	/* write index register with register offset */
	eieio
	sync
	lbz	r3,1(r3)	/* retrieve specified reg offset contents */
	eieio
	sync
	bclr	20,0		/* return to caller */

#endif  /* MV2300 */

		
/******************************************************************************
*
* dCacheOn - Turn Data Cache On
*
* void dCacheOn (void)
*/
_dCacheOn:
dCacheOn:
	/* Get cpu type */

	mfspr	r3,PVR
	rlwinm	r3,r3,16,16,31

	cmpli	0,0,r3,CPU_TYPE_603
	bc	12,2,ccdataon_603
	cmpli	0,0,r3,CPU_TYPE_604
	bc	12,2,ccdataon_604
	cmpli	0,0,r3,CPU_TYPE_603E
	bc	12,2,ccdataon_603
        cmpli   0,0,r3,CPU_TYPE_603P
        bc      12,2,ccdataon_603
        cmpli   0,0,r3,CPU_TYPE_750
        bc	12,2,ccdataon_603
        cmpli   0,0,r3,CPU_TYPE_604E
        bc      12,2,ccdataon_604
        cmpli   0,0,r3,CPU_TYPE_604R
        bc      12,2,ccdataon_604
	bclr	0x14,0x0		/* invalid cpu type */

ccdataon_603:
	addis	r3,r0,0x0000	/* Setup bit pattern for DCE */
	ori	r3,r3,0x4000

	mfspr	r4,HID0		/* Modify HID0 to enable D cache (DCE) */
	or	r4,r4,r3
	mtspr	HID0,r4
	isync			/* may not be needed - precaution */
	bclr	0x14,0x0	/* return to caller */

ccdataon_604:
	addis	r3,r0,0x0000	/* Setup bit pattern for DCE */
	ori	r3,r3,0x4000

	mfspr	r4,HID0		/* Modify HID0 to enable D cache (DCE) */
	or	r4,r4,r3
	mtspr	HID0,r4
	isync			/* may not be needed - precaution */
	bclr	0x14,0x0	/* return to caller */


/******************************************************************************
*
* dCacheOff - Turn Data Cache Off
*
* void dCacheOff (void)
*/
_dCacheOff:
dCacheOff:
	/* Get cpu type */

	mfspr	r3,PVR
	rlwinm	r3,r3,16,16,31

	cmpli	0,0,r3,CPU_TYPE_603
	bc	12,2,ccdataoff_603
	cmpli	0,0,r3,CPU_TYPE_604
	bc	12,2,ccdataoff_604
	cmpli	0,0,r3,CPU_TYPE_603E
	bc	12,2,ccdataoff_603
        cmpli   0,0,r3,CPU_TYPE_603P
        bc      12,2,ccdataoff_603
        cmpli   0,0,r3,CPU_TYPE_750
        bc	12,2,ccdataoff_603
        cmpli   0,0,r3,CPU_TYPE_604E
        bc      12,2,ccdataoff_604
        cmpli   0,0,r3,CPU_TYPE_604R
        bc      12,2,ccdataoff_604
	bclr	0x14,0x0		/* invalid cpu type */

ccdataoff_603:
	addis	r3,r0,0x0000	/* Setup bit pattern for DCE */
	ori	r3,r3,0x4000	

	mfspr	r4,HID0		/* Modify HID0 to disable D cache (DCE) */
	andc	r4,r4,r3
	mtspr	HID0,r4
	isync			/* may not be needed - precaution */
	bclr	0x14,0x0	/* return to caller */

ccdataoff_604:
	addis	r3,r0,0x0000	/* Setup bit pattern for DCE */
	ori	r3,r3,0x4000

	mfspr	r4,HID0		/* Modify HID0 to disable D cache (DCE) */
	andc	r4,r4,r3
	mtspr	HID0,r4
	isync			/* may not be needed - precaution */
	bclr	0x14,0x0	/* return to caller */


/******************************************************************************
*
* dCacheInval - Invalidate Data Cache
*
* void dCacheInval (void)
*/
_dCacheInval:
dCacheInval:
	/* Get cpu type */

	mfspr	r3,PVR
	rlwinm	r3,r3,16,16,31

	cmpli	0,0,r3,CPU_TYPE_603
	bc	12,2,ccdatainvl_603
	cmpli	0,0,r3,CPU_TYPE_604
	bc	12,2,ccdatainvl_604
	cmpli	0,0,r3,CPU_TYPE_603E
	bc	12,2,ccdatainvl_603
        cmpli   0,0,r3,CPU_TYPE_603P
        bc      12,2,ccdatainvl_603
        cmpli   0,0,r3,CPU_TYPE_750
        bc	12,2,ccdatainvl_603
        cmpli   0,0,r3,CPU_TYPE_604E
        bc      12,2,ccdatainvl_604
        cmpli   0,0,r3,CPU_TYPE_604R
        bc      12,2,ccdatainvl_604
	bclr	0x14,0x0		/* invalid cpu type */

/*
 * To invalidate the Data Cache on a 603/750, it's necessary
 * to toggle the DCFI bit.
 */

ccdatainvl_603:
	addis	r3,r0,0x0000	/* Setup bit pattern for DCFI */
	ori	r3,r3,0x0400

	mfspr	r4,HID0		/* Modify HID0 to SET DCFI bit */
	or	r4,r4,r3
	mtspr	HID0,r4
	isync			/* may not be needed - precaution */

	andc	r4,r4,r3	/* Modify HID0 to CLEAR DCFI bit */
	mtspr	HID0,r4
	isync			/* may not be needed - precaution */
	bclr	0x14,0x0	/* return to caller */

/*
 * To invalidate the Data Cache on a 604, it's necessary
 * to toggle the DCFI bit while the Data Cache is enabled (DCE).
 * It is also necessary to delay between setting and clearing DCFI.
 */

ccdatainvl_604:
	addis	r3,r0,0x0000	/* Setup bit pattern for DCFI + DCE */
	ori	r3,r3,0x4400

	mfspr	r4,HID0		/* Modify HID0 to SET DCFI + DCE bits */
	or	r4,r4,r3
	mtspr	HID0,r4
	isync			/* may not be needed - precaution */

	addis	r5,r0,0x0000		/* Setup for small delay */
	ori	r5,r5,0x1000
	mtspr	CTR,r5			/* Load PPC Counter reg */
ccdatainvl_604_d:
	nop
	bdnz	ccdatainvl_604_d	/* branch till counter reaches zero */

	andc	r4,r4,r3	/* Modify HID0 to CLEAR DCFI + DCE bits */
	mtspr	HID0,r4
	isync			/* may not be needed - precaution */
	bclr	0x14,0x0	/* return to caller */