rominit.s

VxWorkS下 MV2604的BSP源代码

	sync				/* data synchronize */
	addi	r10,r10,12		/* increment to next address */
	lwz	r12,0(r10)		/* load write data pattern address */
	cmpl	0,0,r12,r23		/* check for table entry end */
	bc	4,2,.falcon_i_pp_w	/* if not equal, no, branch */

	or	r10,r19,r19		/* copy current table entry pointer */
	addi	r10,r10,DRAM_CHCK1	/* move pointer to data patterns */
.falcon_i_pp_r:
	lwz	r12,0(r10)		/* load write data pattern address */
	lwz	r13,4(r10)		/* load write data pattern hi */
	lwz	r14,8(r10)		/* load write data pattern lo */
	eieio				/* data synchronize */
	sync				/* data synchronize */
	lwz	r15,0(r12)		/* read data pattern hi */
	eieio				/* data synchronize */
	sync				/* data synchronize */
	lwz	r16,4(r12)		/* read data pattern lo */
	eieio				/* data synchronize */
	sync				/* data synchronize */
	cmpl	0,0,r13,r15		/* do they verify? */
	bc	4,2,.falcon_i_pp_f	/* if not equal, no, branch */
	cmpl	0,0,r14,r16		/* do they verify? */
	bc	4,2,.falcon_i_pp_f	/* if not equal, no, branch */
	b	.falcon_i_pp_p		/* verification passed */
.falcon_i_pp_f:
	addi	r21,r21,1		/* increment verify error flag */
.falcon_i_pp_p:
	addi	r10,r10,12		/* increment to next address */
	lwz	r12,0(r10)		/* load write data pattern address */
	cmpl	0,0,r12,r23		/* check for table entry end */
	bc	4,2,.falcon_i_pp_r	/* if not equal, no, branch */

	addi	r10,r10,4		/* increment to one pass the end */
	cmpli	0,0,r21,0		/* any errors? */
	bc	4,2,.falcon_i_pp_d	/* if not equal, yes, branch */
	lbzx	r8,r7,r4		/* read DRAM attributes register */
	eieio				/* data synchronize */
	sync				/* data synchronize */
	andi.	r8,r8,0x7F		/* mask off the bank enable bit */
	stbx	r8,r7,r4		/* write DRAM attributes register */
	eieio				/* data synchronize */
	sync				/* data synchronize */
	b	.falcon_i_pp_n		/* branch to bank by bank loop control*/

.falcon_i_pp_d:
	addi	r8,r0,0x00		/* disable and set to no-size */
	stbx	r8,r7,r4		/* write DRAM attributes register */
	eieio				/* data synchronize */
	sync				/* data synchronize */
	lwz	r12,0(r10)		/* load write data pattern address */
	cmpl	0,0,r12,r23		/* check for table end */
	bc	4,2,.falcon_i_pp_i	/* if not equal, no, branch */

.falcon_i_pp_n:
	addi	r7,r7,1			/* increment bank index */
	cmpli	0,0,r7,NBANKS		/* are we done yet? */
	bc	4,2,.falcon_i_pp	/* if not equal, no, branch */

/*
 *	at this point the DRAM bank attributes registers will be initialized
 *	to the size-encoding of the DRAM which is present (i.e., probed),
 *	else the DRAM attributes registers contain zero indicating no DRAM
 *	was found
 *
 *	the DRAM that was found must be aligned to a boundary of its size
 *
 *	the following code will begin allocating memory address spaces
 *	starting with the largest first, and working itself to the
 *	smallest
 *
 *	memory will start address zero
 */

	bl	.falcon_i_tp_s		/* branch around tables */
	.long	0x40000000,0x00000006	/* 1024MB */
	.long	0x10000000,0x00000005	/* 256MB */
	.long	0x08000000,0x00000004	/* 128MB */
	.long	0x04000000,0x00000003	/* 64MB */
	.long	0x02000000,0x00000002	/* 32MB */
	.long	0x01000000,0x00000001	/* 16MB */
	.long	TBLEND			/* table entry end */

.falcon_i_tp_s:
	mfspr	r6,8			/* load pointer to table */
	or	r10,r6,r6		/* copy table pointer */
	addi	r23,r0,TBLEND		/* setup table end indicator */
	addi	r3,r0,0			/* clear total DRAM size (in bytes) */
	addi	r13,r0,0		/* memory base address (zero) */
	addi	r18,r0,0		/* clear total DRAM size save register */
.falcon_i_sz:
	addi	r7,r0,0			/* clear DRAM bank index register */
	lwz	r8,DRAM_ATTR1(r10)	/* load DRAM attributes for this entry*/
.falcon_i_sz_b:
	lbzx	r9,r7,r4		/* read DRAM attributes register */
	andi.	r9,r9,0x7		/* mask off unwanted data bits */
	cmpl	0,0,r8,r9		/* do the attributes match? */
	bc	4,2,.falcon_i_sz_no	/* if not equal, no, branch */

	rlwinm	r9,r13,8,8,31		/* extract PowerPC A0-A7 bits */
	stbx	r9,r7,r5		/* write DRAM bank base-address reg */
	eieio				/* data synchronize */
	sync				/* data synchronize */
	lbzx	r9,r7,r4		/* read DRAM attributes register */
	ori	r9,r9,0x80		/* set bank enable bit */
	stbx	r9,r7,r4		/* write DRAM attributes register */
	eieio				/* data synchronize */
	sync				/* data synchronize */

/*
 *  Update total DRAM size and current top of memory address
 *  When finished, r3 will contain the total DRAM size (in bytes) and
 *  r13 will contain one past the top of memory address.
 */

	lwz	r9,DRAM_SIZE1(r10)	/* load DRAM size for this entry */
	add	r3,r3,r9		/* add to the total DRAM size */
	add	r18,r18,r9		/* add to the total DRAM size save register */
	add	r13,r13,r9		/* update current top of memory addr */

.falcon_i_sz_no:
	addi	r7,r7,1			/* increment bank index */
	cmpli	0,0,r7,NBANKS		/* are we done yet? */
	bc	4,2,.falcon_i_sz_b	/* if not equal, no, branch */

	addi	r10,r10,8		/* increment to next table entry */
	lwz	r14,0(r10)		/* load memory size variable */
	cmpl	0,0,r14,r23		/* check for table end */
	bc	4,2,.falcon_i_sz	/* if not equal, no, branch */

        /* work-around for a scrubber/refresh logic bug */

	lwz	r4,0x10(r22)		/* copy the bank enables/sizes reg */
	eieio				/* data synchronize */
	sync				/* data synchronize */
	addis	r5,r0,0			/* gimme a zero */
	stw	r5,0x10(r22)		/* disable all, set sizes to zero */
	eieio				/* data synchronize */
	sync				/* data synchronize */
	stw	r5,0x48(r22)		/* clr ROW/COL addr of refresh/scrub */
	eieio				/* data synchronize */
	sync				/* data synchronize */
	stw	r4,0x10(r22)		/* restore the bank enables/sizes reg */
	eieio				/* data synchronize */
	sync				/* data synchronize */

/*
 *		The purpose of this section is to enable the ECC of the
 *		DRAM.  To do this, it is first necessary to initialize the
 *		ECC check bits.  The ECC check bits are initialized by
 *		initializing all of DRAM.
 *
 *	input:
 *		r3	= Total DRAM size (in bytes)
 *	notes:
 *		1. must run as a supervisor function
 *		2. interrupts must be masked
 *		3. address translation (MMU) disabled
 *		4. assumes ECC Control register is in a power-up state
 *		5. The scrubber is not enabled (SWEN=0).  This provides
 *		   better performance at the expense of less fault
 *		   tolerance.
 */

.falcon_scrub:

/* setup local variables */

	addi	r15,r0,0		/* load starting addr - always zero */
	or	r16,r3,r3		/* load number of bytes		    */
	rlwinm	r16,r16,29,3,31		/* calculate number of doubles      */

/* Make sure FPU is enabled; it's needed for DRAM loads and stores */

	mfmsr	r14			/* Save current value of MSR in r14 */
	addi	r4,r0,0x2000		/* FP bit definition */
	or	r4,r4,r14
	mtmsr	r4
	isync

/*
 * invalidate/enable the processor data cache, one of the assumptions
 * is that address translation is disabled, the default caching mode
 * is copy-back when address translation is disabled, copy-back mode
 * is the recommended caching mode
 */

	stwu	sp, -64(sp)		/* Create an ABI stack frame */
	bl	dCacheInval
	bl	dCacheOn
	addi	sp,sp,64		/* Remove ABI stack frame */

/*
 * Loop through the entire DRAM array and initialize memory.  This has
 * the side effect of initializing the ECC check bits because they are
 * always updated when the DRAM is written.
 *
 * The data path to DRAM is the size of a cache line (128-bits), this
 * is why the data cache is enabled, the initialization of the ECC check
 * bits are optimized when a cache line write/flush occurs
 */

falcon_scrub_start:
	addi	r17,r15,-8		/* starting address - munged */
	mtspr	9,r16			/* load number of doubles in counter */
falcon_scrub_iloop:
	lfdu	0,8(r17)
	stfd	0,0(r17)
	bc	16,0,falcon_scrub_iloop	/* branch till counter == 0 */

	eieio
	sync
/*
 * Loop through the entire DRAM array again.
 * Looping through the entire DRAM array is not necessary just convenient.
 * What is necessary is flushing the data cache from the previous loop
 * so that the last segment (data cache size) of DRAM is initialized.
 */
	addi	r17,r15,-8		/* starting address - munged */
	mtspr	9,r16			/* load number of doubles in counter */
falcon_scrub_floop:
	lfdu	0,8(r17)
	bc	16,0,falcon_scrub_floop	/* branch till counter == 0 */

	eieio
	sync

/* disable the data cache */

	stwu	sp, -64(sp)		/* Create an ABI stack frame */
	bl	dCacheInval
	bl	dCacheOff
	addi	sp,sp,64		/* Remove ABI stack frame */

/* Restore original value of MSR */

	mtmsr	r14
	isync

/* Clear any possible error conditions that occurred during init */

	lis	r14, HI(FALCON_BASE_ADRS)
	ori	r14, r14, LO(FALCON_BASE_ADRS)

	addis	r9,r0,0x8000		/* ELOG=1,ESEN=0,SCOF=1 */
	ori	r9,r9,0x0100
	stw	r9,0x30(r14)		/* Update Error Logger register */
	eieio
	sync

/* Enable ECC and multiple-bit error detection */

	addis	r9,r0,0x0000		/* RWCB=0,DERC=0,xIEN=0,MCKEN=1 */
	ori	r9,r9,0x0001
	stw	r9,0x28(r14)		/* Update ECC Control register */
	eieio
	sync

/* End of Falcon Init */

#ifdef EXTENDED_VME
/*
 * Verify that the end of DRAM does not overlap VME_A32_MSTR_LOCAL.
 * If it does, set MSADD0 to the size of DRAM.  A message will be displayed
 * in sysPhysMemTop prompting the user to increase VME_A32_MSTR_LOCAL.
 * 
 * The size of DRAM is saved in r18 from the memory probe.
 */
	lis	r3, HI(RAVEN_BASE_ADRS)
	ori	r3, r3, LO(RAVEN_BASE_ADRS)

	lis	r5, HI(VME_A32_MSTR_LOCAL)
	ori	r5, r5, LO(VME_A32_MSTR_LOCAL)

	cmpl	0,0,r18,r5		/* If r18 < VME_A32_MSTR_LOCAL */
	bc	12,0,memMapGood		/* Set MSADD0 to DRAM size */

	ori	r18,r18,CPU2PCI_ADDR0_END	/* MSADD0: */
	stw	r18,RAVEN_MPC_MSADD0(r3)	/* write MSADD0 w DRAM size */

	b	doneMSAddr0Calc

memMapGood:
	addis	r4,r0,(VME_A32_MSTR_LOCAL>>16)	/* MSADD0: */
	ori	r4,r4,CPU2PCI_ADDR0_END		/* MSADD0: */
	stw	r4,RAVEN_MPC_MSADD0(r3)		/* write MSADD0 */
	
doneMSAddr0Calc:
	eieio					/* synchronize */
	sync					/* synchronize */
#endif

#if	FALSE				/* XXX TPR SDA not supported yet */
        /* initialize r2 and r13 according to EABI standard */

	lis     r2, HI(_SDA2_BASE_)
	ori	r2, r2, LO(_SDA2_BASE_)
	lis     r13, HI(_SDA_BASE_)
	ori	r13, r13, LO(_SDA_BASE_)
#endif

	/* go to C entry point */

	or	r3, r11, r11
	addi	sp, sp, -FRAMEBASESZ	/* get frame stack */

        lis     r6, HI(romStart)
        ori	r6, r6, LO(romStart)

        lis     r7, HI(romInit)
        ori	r7, r7, LO(romInit)

        lis     r8, HI(ROM_TEXT_ADRS)
        ori	r8, r8, LO(ROM_TEXT_ADRS)

	sub	r6, r6, r7
	add	r6, r6, r8 

	mtlr	r6
	blr

#ifndef MV2300

	.set	SIO_LUNINDEX,0x07	/* SIO LUN index register */
	.set	SIO_CNFG1,0x21		/* SIO configuration #1 register */
	.set	SIO_CNFG2,0x22		/* SIO configuration #2 register */
	.set	SIO_PCSCI,0x23		/* SIO PCS configuration index reg */
	.set	SIO_PCSCD,0x24		/* SIO PCS configuration data reg */
	.set	SIO_SID,0x08		/* SIO identifier register */
	.set	SIO_SIDPNP,0x20		/* SIO identifier register - PnP */
	.set	SIO_SIDMASK,0xF8	/* SIO identifier mask */
	.set	SIO_SID87303,0x30	/* SIO identifier - 87303 */
	.set	SIO_SID87323,0x20	/* SIO identifier - 87323 */
	.set	SIO_SID87308,0xA0	/* SIO identifier - 87308 */
	.set	SIO_ACTIVATE,0x30	/* SIO activate register */
	.set	SIO_IOBASEHI,0x60	/* SIO I/O port base address, 15:8 */
	.set	SIO_IOBASELO,0x61	/* SIO I/O port base address,  7:0 */
	.set	SIO_DBASEHI,0x60	/* SIO KBC data base address, 15:8 */
	.set	SIO_DBASELO,0x61	/* SIO KBC data base address,  7:0 */
	.set	SIO_CBASEHI,0x62	/* SIO KBC command base addr, 15:8 */
	.set	SIO_CBASELO,0x63	/* SIO KBC command base addr,  7:0 */
	.set	SIO_LUNENABLE,0x01	/* SIO LUN enable */
	.set	SIO_LUNDISABLE,0x00	/* SIO LUN disable */
	.set	SIO_LUNCNFGR,0xF0	/* SIO LUN configuration register */
        .set    PID_CLARIION,0xC0       /* processor identifier, CLARIION */
        .set    PID_VIPER,0xD0          /* processor identifier, VIPER */
        .set    PID_GENESIS2,0xE0       /* processor identifier, GENESIS2 */
        .set    PID_MASK,0xF0           /* processor identifier mask */

/*
;
;	This function initializes the superio chip to a functional 
;	state.
;
;	Upon completion, SIO resource registers are mapped as follows:
;	Resource	Enabled		Address
;	FDC		Yes		PRI	3F0-3F7
;	IDE		Yes		PRI	1F0-1F7 3F6, 3F7
;	UART1		Yes		COM1	3F8-3FF
;	UART2		Yes		COM2	2F8-2FF
;	||PORT		Yes		LPT1	3BC-3BE
;	RTC		Yes			070, 071
;	KBC		Yes			060, 064
;
;
*/

.sioInit:
	mfspr	r7,8			/* save link register */
/*
;
;	check the type of superI/O that we're dealing with (read the
;	identifier register of the 87303/87323), all possible locations
;	are checked, this is done in the case the configuration straps
;	are not installed correctly, this will give us the ability to
;	have basic serial COM for console I/O
;
*/
	/*
	 *	Get base addr of ISA I/O space
	 */
	lis	r6,HI(CPU_PCI_ISA_IO_ADRS)
	ori	r6,r6,LO(CPU_PCI_ISA_IO_ADRS)
/*
 *	Probe the 4 possible locations of the SIO's Index Register
 *	in ISA I/O space.
 *		398/399
 *		26E/26F
 *		15C/15D
 *		02E/02F
 */
	addi	r3,r6,0x0398		/* Get superI/O 87303/87323 base */
	addi	r4,r0,SIO_SID		/* load identifier register offset */
	bl	.sio_br
	addi	r4,r0,0x0398		/* Get superI/O 87303/87323 base */
	andi.	r3,r3,SIO_SIDMASK	/* mask to identifier bits */
	cmpli	0,0,r3,SIO_SID87303	/* is it a 87303? */
	bc	12,2,.sioInit_87303	/* if equal, yes, goto to 87303 init */
	cmpli	0,0,r3,SIO_SID87323	/* is it a 87323? */
	bc	12,2,.sioInit_87303	/* if equal, yes, goto to 87303 init */

	addi	r3,r6,0x026E		/* Get superI/O 87303/87323 base */
	addi	r4,r0,SIO_SID		/* load identifier register offset */
	bl	.sio_br
	addi	r4,r0,0x026E		/* Get superI/O 87303/87323 base */
	andi.	r3,r3,SIO_SIDMASK	/* mask to identifier bits */
	cmpli	0,0,r3,SIO_SID87303	/* is it a 87303? */
	bc	12,2,.sioInit_87303	/* if equal, yes, goto to 87303 init */
	cmpli	0,0,r3,SIO_SID87323	/* is it a 87323? */
	bc	12,2,.sioInit_87303	/* if equal, yes, goto to 87303 init */

	addi	r3,r6,0x015C		/* Get superI/O 87303/87323 base */
	addi	r4,r0,SIO_SID		/* load identifier register offset */
	bl	.sio_br
	addi	r4,r0,0x015C		/* Get superI/O 87303/87323 base */
	andi.	r3,r3,SIO_SIDMASK	/* mask to identifier bits */
	cmpli	0,0,r3,SIO_SID87303	/* is it a 87303? */
	bc	12,2,.sioInit_87303	/* if equal, yes, goto to 87303 init */
	cmpli	0,0,r3,SIO_SID87323	/* is it a 87323? */
	bc	12,2,.sioInit_87303	/* if equal, yes, goto to 87303 init */

	addi	r3,r6,0x002E		/* Get superI/O 87303/87323 base */
	addi	r4,r0,SIO_SID		/* load identifier register offset */
	bl	.sio_br
	addi	r4,r0,0x002E		/* Get superI/O 87303/87323 base */
	andi.	r3,r3,SIO_SIDMASK	/* mask to identifier bits */
	cmpli	0,0,r3,SIO_SID87303	/* is it a 87303? */
	bc	12,2,.sioInit_87303	/* if equal, yes, goto to 87303 init */
	cmpli	0,0,r3,SIO_SID87323	/* is it a 87323? */
/*
;
;	if we make it here, the SIO device is not a 87303/87323 type,
;	check for an 87308 SIO device type (PnP capable), for right
;	now only motherboard mode addresses will be probed
;
;
;	87308 initialization
;
*/
.sioInit_87308:

/*
;
;	determine the base address (motherboard mode - 15C/15D, 2E/2F)
;
*/
	/*
	 *	Get base addr of ISA I/O space
	 */
	lis	r6,HI(CPU_PCI_ISA_IO_ADRS)
	ori	r6,r6,LO(CPU_PCI_ISA_IO_ADRS)

	addi	r3,r6,0x002E		/* adjust to superI/O 87308 base */
	addi	r4,r0,SIO_SIDPNP	/* select SID register */
	bl	.sio_br
	andi.	r3,r3,SIO_SIDMASK	/* mask to identifier bits */
	cmpli	0,0,r3,SIO_SID87308	/* is it a 87308? */
	addi	r4,r0,0x002E		/* adjust to superI/O 87308 base */