rominit.s

VxWorkS下 MV2604的BSP源代码

nodiswdog:

/*
#	Initialize the RAVEN MPC registers.
#	notes:
#               1. For the standard vxWorks configuration the  MPC to
#                  PCI mapping registers are
#                  initialized to the PReP model with some additions:
#
#	MPC Address Range       PCI Address Range       Definition
#       -----------------       -----------------       ------------------------
#	80000000 BF7FFFFF	00000000 3F7FFFFF	ISA/PCI I/O space
#	C0000000 FCFFFFFF	00000000 3CFFFFFF	ISA/PCI Mem space w/MPIC
#	FD000000 FDFFFFFF	00000000 00FFFFFF	ISA/PCI Mem space
#	FE000000 FE7FFFFF	00000000 007FFFFF	ISA/PCI I/O space
#
#		2. This assignments do not include the entire PReP PCI
#		   address space, this is due to the conflicting local
#		   resources of the H/W.
#
#               3. When EXTENDED_VME is defined the mapping is as follows:
#
#       MPC Address Range           PCI Address Range      Definition
# --------------------------- ---------------------------  ---------------------
# VME_A32_MSTR_LOCAL FBFFFFFF VME_A32_MSTR_LOCAL FBFFFFFF  VME address space
#       FC000000 FCFFFFFF           FC000000 FCFFFFFF      MPIC/Reg space
#       FD000000 FDFFFFFF           FD000000 FDFFFFFF      ISA/PCI Memory space
#       FE000000 FE7FFFFF           00000000 007FFFFF      ISA/PCI I/O space
#
*/
	lis	r3, HI(RAVEN_BASE_ADRS)
	ori	r3, r3, LO(RAVEN_BASE_ADRS)

	addis	r4,r0,0x0000		/* GCSR:FLBRD=0,MBT=256us */
	ori	r4,r4,0x0000		/* GCSR:FLBRD=0,MBT=256us */
	sth	r4,RAVEN_MPC_GCSR(r3)	/* write GCSR */
	eieio				/* synchronize */
	sync				/* synchronize */

	addis	r4,r0,0x0000		/* MARB:BRENx=1,PKEN=0,PKMD=0,DEFMx=1 */
	ori	r4,r4,0x0703		/* MARB:BRENx=1,PKEN=0,PKMD=0,DEFMx=1 */
	sth	r4,RAVEN_MPC_MARB(r3)	/* write MARB */
	eieio				/* synchronize */
	sync				/* synchronize */

	addis	r4,r0,0x0000		/* PADJ:BE=66MHZ */
	ori	r4,r4,0x00BE		/* PADJ:BE=66MHZ */
	stb	r4,RAVEN_MPC_PADJ(r3)	/* write PADJ */
	eieio				/* synchronize */
	sync				/* synchronize */

	addis	r4,r0,0x0000		/* MEREN:(all error enables disabled) */
	ori	r4,r4,0x0000		/* MEREN:(all error enables disabled) */
	sth	r4,RAVEN_MPC_MEREN(r3)	/* write MEREN */
	eieio				/* synchronize */
	sync				/* synchronize */

	addis	r4,r0,0x0000		/* MERST:(clear all error status) */
	ori	r4,r4,0x00ff		/* MERST:(clear all error status) */
	stb	r4,RAVEN_MPC_MERST(r3)	/* write MERST */
	eieio				/* synchronize */
	sync				/* synchronize */

	addis	r4,r0,0x0000		/* MSATTx:(all attributes disabled) */
	ori	r4,r4,0x0000		/* MSATTx:(all attributes disabled) */
	stb	r4,RAVEN_MPC_MSATT0(r3)	/* write MSATT0 */
	eieio				/* synchronize */
	sync				/* synchronize */
	stb	r4,RAVEN_MPC_MSATT1(r3)	/* write MSATT1 */
	eieio				/* synchronize */
	sync				/* synchronize */
	stb	r4,RAVEN_MPC_MSATT2(r3)	/* write MSATT2 */
	eieio				/* synchronize */
	sync				/* synchronize */
	stb	r4,RAVEN_MPC_MSATT3(r3)	/* write MSATT3 */
	eieio				/* synchronize */
	sync				/* synchronize */

	addis	r4,r0,CPU2PCI_ADDR0_START	/* MSADD0: */
	ori	r4,r4,CPU2PCI_ADDR0_END		/* MSADD0: */
	stw	r4,RAVEN_MPC_MSADD0(r3)	/* write MSADD0 */
	eieio				/* synchronize */
	sync				/* synchronize */

	addis	r4,r0,0x0000		/* MSOFF0: */
	ori	r4,r4,CPU2PCI_OFFSET0	/* MSOFF0: */
	sth	r4,RAVEN_MPC_MSOFF0(r3)	/* write MSOFF0 */
	eieio				/* synchronize */
	sync				/* synchronize */

	addis	r4,r0,0x0000		/* MSATT0: */
	ori	r4,r4,CPU2PCI_MSATT0	/* MSATT0: */
	stb	r4,RAVEN_MPC_MSATT0(r3)	/* write MSATT0 */
	eieio				/* synchronize */
	sync				/* synchronize */

	addis	r4,r0,CPU2PCI_ADDR1_START	/* MSADD1: */
	ori	r4,r4,CPU2PCI_ADDR1_END		/* MSADD1: */
	stw	r4,RAVEN_MPC_MSADD1(r3)	/* write MSADD1 */
	eieio				/* synchronize */
	sync				/* synchronize */

	addis	r4,r0,0x0000		/* MSOFF1: */
	ori	r4,r4,CPU2PCI_OFFSET1	/* MSOFF1: */
	sth	r4,RAVEN_MPC_MSOFF1(r3)	/* write MSOFF1 */
	eieio				/* synchronize */
	sync				/* synchronize */

	addis	r4,r0,0x0000		/* MSATT1: */
	ori	r4,r4,CPU2PCI_MSATT1	/* MSATT1: */
	stb	r4,RAVEN_MPC_MSATT1(r3)	/* write MSATT1 */
	eieio				/* synchronize */
	sync				/* synchronize */

	addis	r4,r0,CPU2PCI_ADDR2_START	/* MSADD2: */
	ori	r4,r4,CPU2PCI_ADDR2_END		/* MSADD2: */
	stw	r4,RAVEN_MPC_MSADD2(r3)	/* write MSADD2 */
	eieio				/* synchronize */
	sync				/* synchronize */

	addis	r4,r0,0x0000		/* MSOFF2: */
	ori	r4,r4,CPU2PCI_OFFSET2	/* MSOFF2: */
	sth	r4,RAVEN_MPC_MSOFF2(r3)	/* write MSOFF2 */
	eieio				/* synchronize */
	sync				/* synchronize */

	addis	r4,r0,0x0000		/* MSATT2: */
	ori	r4,r4,CPU2PCI_MSATT2	/* MSATT2: */
	stb	r4,RAVEN_MPC_MSATT2(r3)	/* write MSATT2 */
	eieio				/* synchronize */
	sync				/* synchronize */

/*
 * PCI address space 3 registers supports config. space access and
 * special cycle generation.  It should be configured for I/O space.
 */

	addis	r4,r0,CPU2PCI_ADDR3_START	/* MSADD3: */
	ori	r4,r4,CPU2PCI_ADDR3_END		/* MSADD3: */
	stw	r4,RAVEN_MPC_MSADD3(r3)	/* write MSADD3 */
	eieio				/* synchronize */
	sync				/* synchronize */

	addis	r4,r0,0x0000		/* MSOFF3: */
	ori	r4,r4,CPU2PCI_OFFSET3	/* MSOFF3: */
	sth	r4,RAVEN_MPC_MSOFF3(r3)	/* write MSOFF3 */
	eieio				/* synchronize */
	sync				/* synchronize */

	addis	r4,r0,0x0000		/* MSATT3: */
	ori	r4,r4,CPU2PCI_MSATT3	/* MSATT3: */
	stb	r4,RAVEN_MPC_MSATT3(r3)	/* write MSATT3 */
	eieio				/* synchronize */
	sync				/* synchronize */

/* End of Raven Init */

/* 
 * Do the init for the SIO, now that the Raven is configured.
 * This was moved after the Raven init for the Extended VME config.
 */

#ifndef MV2300
        bl .sioInit
#endif  /* MV2300 */

/*
# 	DRAM Initialization/Sizing for FALCON Module
#	Initialize the FALCON (DRAM Controller) registers.
#	The registers are initialized with values from the
#	results of the probe (see below).
#
#	algorithm:
#
#	Each memory bank size that is possible is tried.  This starts
#	with the largest to the smallest.   A table is used to inform
#	the sizing code of the needed information.  The information
#	consists of the memory bank size, probe addresses, and the data
#	pattern associated with each of the probe address.  All off the
#	probe addresses are written to first with associative write data
#	pattern, then they are read.  An exact match of the data is
#	required to deem the memory bank size has been found.
#
#	Size			Key Address Lines
#	40000000 (1GB)		A2
#	10000000 (256MB)	A4/A6
#	08000000 (128MB)	A5/A6/A18
#	04000000 (64MB)		A6/A18
#	02000000 (32MB)		A7/A18/A19
#	01000000 (16MB)		N/A
#
#	As you can see, this algorithm is coupled very tightly with the
#	H/W, if it ever changes, this algorithm will need to be modified.
#
#	register-usage:
#		r1	= SP (not modified)
#		r2	= TOC (not modified)
#		r3	= size of DRAM in bytes
#		r4	= DRAM attributes register address
#		r5	= DRAM base-address register address
#		r6	= test pattern's table pointer
#		r7	= DRAM bank index (0 to 3)
#		r8-r10,r12-r19	= run-time (scratch)
#		r11	= VxWorks 
#		r20	= saved return instruction pointer
#		r21	= verify error flag
#		r22	= FALCON base address
#		r23	= run-time (scratch)
#
*/

	.set	NBANKS,4		/* number of DRAM banks */

	xor	r0,r0,r0		/* insure r0 is zero */
	or	r3,r0,r0		/* set to no memory present state */
	mfspr	r20,8			/* save return instruction pointer */

	bl	.falcon_i_ra		/* branch around tables */
        
        /* DRAM controller register addresses table */

	.long	FALCON_BASE_ADRS
	.long	DRAM_REG_BASE		/* DRAM base-address register addr */
	.long	DRAM_REG_SIZE		/* DRAM attributes register address */

.falcon_i_ra:
	mfspr	r4,8			/* load pointer to table */

        /* load register address values */

	lwz	r8,0x00(r4)		/* FALCON register base address */
	lwz	r5,0x04(r4)		/* DRAM base-address register address */
	lwz	r4,0x08(r4)		/* DRAM attributes register address */
	or	r22,r8,r8		/* save it for later use */

	eieio				/* synchronize the data stream */
	sync				/* synchronize the data stream */

        /* initialize to DRAM control registers to a known state */

	/* get the DRAM speed (RSPD, in r3) */

	lis	r9, HI(MV2600_MCR_)	/* load address of Mem Config Reg */
	ori	r9, r9, LO(MV2600_MCR_)
	lwz	r9, 0(r9)
	lis	r10, HI(MV2600_MCR_MSK)	/* load mask for DRAM speed */
	ori	r10, r10, LO(MV2600_MCR_MSK)
	and	r9, r9, r10

	lis	r10, HI(MV2600_MCR_DRAM_60ns)	/* load value for 60 ns DRAM */
	ori	r10, r10, LO(MV2600_MCR_DRAM_60ns)
	cmpw	1,  r9, r10
	bc	12, 6, dram60ns

	lis	r10, HI(MV2600_MCR_DRAM_50ns)	/* load value for 50 ns DRAM */
	ori	r10, r10, LO(MV2600_MCR_DRAM_50ns)
	cmpw	1,  r9, r10
	bc	12, 6, dram50ns
	li	r3, DRAM_70ns			/* default: 70 ns */
	b	endDramSpd

dram60ns:
	li	r3, DRAM_60ns
	b	endDramSpd
dram50ns:
	li	r3, DRAM_50ns

endDramSpd:
	lis	r9, HI(MV2600_MCR_)	/* load address of Mem Config Reg */
	ori	r9, r9, LO(MV2600_MCR_)
	lwz	r9,0(r9)		/* read Memory Configuration Register */
	eieio				/* data synchronize */
	sync				/* data synchronize */
	rlwinm	r9,r9,7,28,28 		/* mask off all but the M_FREF bit */

	or	r9,r3,r9		/* IHEN=0,ADIS=0,RFREF=M_FREF */
	stw	r9,0x08(r8)		/* general control register */
	eieio				/* synchronize the data stream */
	sync				/* synchronize the data stream */

	/* get bus speed in MHZ, r3 has value */

	lis	r9, HI(MV2600_CCR_)	/* load address of System Config Reg */
	ori	r9, r9, LO(MV2600_CCR_)
	lwz	r9, 0(9)
	lis	r10, HI(MV2600_CCR_CLK_MSK)	/* load mask for bus speed */
	ori	r10, r10, LO(MV2600_CCR_CLK_MSK)
	and	r9, r9, r10

	lis	r10, HI(MV2600_CCR_CPU_CLK_60)	/* load value for 60 */
	ori	r10, r10, LO(MV2600_CCR_CPU_CLK_60)
	cmpw	1,  r9, r10
	bc	12, 6, bus60mhz

	lis	r10, HI(MV2600_CCR_CPU_CLK_50)	/* load value for 50 */
	ori	r10, r10, LO(MV2600_CCR_CPU_CLK_50)
	cmpw	1,  r9, r10
	bc	12, 6, bus50mhz
	li	r3, 67					/* default: 67 MHz */
	b	endBusSpd

bus60mhz:
	li	r3, 60
	b	endBusSpd
bus50mhz:
	li	r3, 50

endBusSpd:
	slwi	r3,r3,24		/* move to upper byte */
	stw	r3,0x20(r8)		/* CLK frequency register */
	eieio				/* synchronize the data stream */
	sync				/* synchronize the data stream */

	addis	r9,r0,0x0000		/* SWEN=0,RTEST=000 */
	ori	r9,r9,0x0000		/* SWEN=0,RTEST=000 */
	stw	r9,0x40(r8)		/* DRAM scrub/refresh register */
	eieio				/* synchronize the data stream */
	sync				/* synchronize the data stream */

	addis	r9,r0,0x0100		/* RWCB=0,DERC=1,xIEN=0,MCKEN=0 */
	ori	r9,r9,0x0000		/* RWCB=0,DERC=1,xIEN=0,MCKEN=0 */
	stw	r9,0x28(r8)		/* DRAM ECC control register */
	eieio				/* synchronize the data stream */
	sync				/* synchronize the data stream */

	addis	r9,r0,0x8000		/* ELOG=1,ESEN=0,SCOF=1 */
	ori	r9,r9,0x0100		/* ELOG=1,ESEN=0,SCOF=1 */
	stw	r9,0x30(r8)		/* DRAM ECC error-logger register */
	eieio				/* synchronize the data stream */
	sync				/* synchronize the data stream */

	bl	.falcon_i_tp		/* branch around tables */

        /* write-addresses/data-patterns table (address/hi-data/lo-data) */

	.set	DRAM_SIZE1,0		/* size index */
	.set	DRAM_ATTR1,4		/* attributes index */
	.set	DRAM_CHCK1,8		/* address/pattern starting index */
	.set	TBLEND,-1		/* table end marker */

        /* 1GB */

	.long	0x40000000,0x06
	.long	0x00000000,0x01010101,0xFEFEFEFE
	.long	0x20000000,0x02020202,0xFDFDFDFD
	.long	-1					/* table entry end */

        /* 256MB */

	.long	0x10000000,0x05
	.long	0x00000000,0x03030303,0xFCFCFCFC
	.long	0x02000000,0x04040404,0xFBFBFBFB
	.long	0x08000000,0x05050505,0xFAFAFAFA
	.long	0x0A000000,0x06060606,0xF9F9F9F9
	.long	-1					/* table entry end */

        /* 128MB */

	.long	0x08000000,0x04
	.long	0x00000000,0x07070707,0xF8F8F8F8
	.long	0x00002000,0x08080808,0xF7F7F7F7
	.long	0x02000000,0x09090909,0xF6F6F6F6
	.long	0x02002000,0x0A0A0A0A,0xF5F5F5F5
	.long	0x04000000,0x0B0B0B0B,0xF4F4F4F4
	.long	0x04002000,0x0C0C0C0C,0xF3F3F3F3
	.long	0x06000000,0x0D0D0D0D,0xF2F2F2F2
	.long	0x06002000,0x0E0E0E0E,0xF1F1F1F1
	.long	-1					/* table entry end */

        /* 64MB */

	.long	0x04000000,0x03
	.long	0x00000000,0x0F0F0F0F,0xF0F0F0F0
	.long	0x00002000,0x10101010,0xEFEFEFEF
	.long	0x02000000,0x11111111,0xEEEEEEEE
	.long	0x02002000,0x12121212,0xEDEDEDED
	.long	-1					/* table entry end */

        /* 32MB */

	.long	0x02000000,0x02
	.long	0x00000000,0x13131313,0xECECECEC
	.long	0x00001000,0x14141414,0xEBEBEBEB
	.long	0x00002000,0x15151515,0xEAEAEAEA
	.long	0x00003000,0x16161616,0xE9E9E9E9
	.long	0x01000000,0x17171717,0xE8E8E8E8
	.long	0x01001000,0x18181818,0xE7E7E7E7
	.long	0x01002000,0x19191919,0xE6E6E6E6
	.long	0x01003000,0x1A1A1A1A,0xE5E5E5E5
	.long	-1					/* table entry end */

        /* 16MB */

	.long	0x01000000,0x01
	.long	0x00000000,0x1B1B1B1B,0xE4E4E4E4
	.long	-1					/* table entry end */

	.long	-1					/* table end */

.falcon_i_tp:
	mfspr	r6,8			/* load pointer to table */

/*
 *	disable all DRAM banks and set to "block not present" size
 *	set all DRAM banks base-address register to zero
 */

	addi	r7,r0,0			/* clear DRAM bank index register */
	addi	r8,r0,0x00		/* disable and set to no-size */
.falcon_i_ks:
	stbx	r8,r7,r4		/* write DRAM attributes register */
	stbx	r8,r7,r5		/* write DRAM bank base-address reg */
	addi	r7,r7,1			/* increment bank index */
	cmpli	0,0,r7,NBANKS		/* are we done yet? */
	bc	4,2,.falcon_i_ks	/* if not equal, no, branch */

/*
 *	probe for the existance of all possible DRAM banks
 *
 *	on a DRAM bank basis, the DRAM bank is enabled with the size
 *	as specified by the current table entry, then perform the data
 *	writes at the specified addresses as specified by the current table
 *	entry, then read and verify the locations written with the
 *	expected data
 *
 *	following each probe the DRAM bank will be disabled, if the DRAM
 *	bank is present, its attributes register will be initialized to
 *	the size found (i.e., size-encoding bits set to proper state)
 */

	addi	r23,r0,TBLEND		/* setup table end indicator */
	addi	r7,r0,0			/* clear DRAM bank index register */
.falcon_i_pp:
	or	r19,r6,r6		/* copy pointer to table */
	or	r10,r6,r6		/* copy pointer to table */

        /* write test data patterns (as specified by the current table entry)*/

.falcon_i_pp_i:
	or	r19,r10,r10		/* copy current table entry pointer */
	addi	r21,r0,0		/* clear verify error flag */
	lwz	r14,DRAM_ATTR1(r10)	/* load DRAM attributes(encoded size)*/
	ori	r14,r14,0x80		/* set bank enable bit */
	stbx	r14,r7,r4		/* write DRAM attributes register */
	eieio				/* data synchronize */
	sync				/* data synchronize */
	addi	r10,r10,DRAM_CHCK1	/* move pointer to data patterns */
.falcon_i_pp_w:
	lwz	r12,0(r10)		/* load write data pattern address */
	lwz	r13,4(r10)		/* load write data pattern hi */
	lwz	r14,8(r10)		/* load write data pattern lo */
	eieio				/* data synchronize */
	sync				/* data synchronize */
	stw	r13,0(r12)		/* write data pattern hi */
	eieio				/* data synchronize */
	sync				/* data synchronize */
	stw	r14,4(r12)		/* write data pattern lo */
	eieio				/* data synchronize */