sysalib.s

VxWorkS下 MV2604的BSP源代码

*/

sysPciOutLong:

        /*
         *      Write a big-endian long to little-endian PCI space
         */
        stwbrx  r4,r0,r3
        /*
         *      Sync I/O operation
         */
        mr      r3,r4
	eieio
        /*
         *      Return to caller
         */
        bclr    20,0

/*******************************************************************************
*
* sysMemProbeSup - sysBusProbe support routine
*
* This routine is called to try to read byte, word, or long, as specified
* by length, from the specified source to the specified destination.
*
* RETURNS: OK if successful probe, else ERROR

STATUS sysMemProbeSup (length, src, dest)
    (
    int         length, // length of cell to test (1, 2, 4, 8, 16) *
    char *      src,    // address to read *
    char *      dest    // address to write *
    )

*/

sysMemProbeSup:
        addi    p7, p0, 0       /* save length to p7 */
        xor     p0, p0, p0      /* set return status */
        cmpwi   p7, 1           /* check for byte access */
        bne     sbpShort        /* no, go check for short word access */
        lbz     p6, 0(p1)       /* load byte from source */
        eieio
        sync
        stb     p6, 0(p2)       /* store byte to destination */
        eieio
        sync
        isync                   /* enforce for immediate exception handling */
        blr
sbpShort:
        cmpwi   p7, 2           /* check for short word access */
        bne     sbpWord         /* no, check for word access */
        lhz     p6, 0(p1)       /* load half word from source */
        eieio
        sync
        sth     p6, 0(p2)       /* store half word to destination */
        eieio
        sync
        isync                   /* enforce for immediate exception handling */
        blr
sbpWord:
        cmpwi   p7, 4           /* check for short word access */
        bne     sysProbeExc     /* no, check for double word access */
        lwz     p6, 0(p1)       /* load half word from source */
        eieio
        sync
        stw     p6, 0(p2)       /* store half word to destination */
        eieio
        sync
        isync                   /* enforce for immediate exception handling */
        blr
sysProbeExc:
        li      p0, -1          /* shouldn't ever get here, but... */
        blr

#ifndef MV2300

	.set	SIO_LUNINDEX,0x07	/* SIO LUN index register */
	.set	SIO_CNFG1,0x21		/* SIO configuration #1 register */
	.set	SIO_CNFG2,0x22		/* SIO configuration #2 register */
	.set	SIO_PCSCI,0x23		/* SIO PCS configuration index reg */
	.set	SIO_PCSCD,0x24		/* SIO PCS configuration data reg */
	.set	SIO_SID,0x08		/* SIO identifier register */
	.set	SIO_SIDPNP,0x20		/* SIO identifier register - PnP */
	.set	SIO_SIDMASK,0xF8	/* SIO identifier mask */
	.set	SIO_SID87303,0x30	/* SIO identifier - 87303 */
	.set	SIO_SID87323,0x20	/* SIO identifier - 87323 */
	.set	SIO_SID87308,0xA0	/* SIO identifier - 87308 */
	.set	SIO_ACTIVATE,0x30	/* SIO activate register */
	.set	SIO_IOBASEHI,0x60	/* SIO I/O port base address, 15:8 */
	.set	SIO_IOBASELO,0x61	/* SIO I/O port base address,  7:0 */
	.set	SIO_DBASEHI,0x60	/* SIO KBC data base address, 15:8 */
	.set	SIO_DBASELO,0x61	/* SIO KBC data base address,  7:0 */
	.set	SIO_CBASEHI,0x62	/* SIO KBC command base addr, 15:8 */
	.set	SIO_CBASELO,0x63	/* SIO KBC command base addr,  7:0 */
	.set	SIO_LUNENABLE,0x01	/* SIO LUN enable */
	.set	SIO_LUNDISABLE,0x00	/* SIO LUN disable */
	.set	SIO_LUNCNFGR,0xF0	/* SIO LUN configuration register */
        .set    PID_CLARIION,0xC0       /* processor identifier, CLARIION */
        .set    PID_VIPER,0xD0          /* processor identifier, VIPER */
        .set    PID_GENESIS2,0xE0       /* processor identifier, GENESIS2 */
        .set    PID_MASK,0xF0           /* processor identifier mask */

/*
;
;	This function initializes the superio chip to a functional 
;	state.
;
;	Upon completion, SIO resource registers are mapped as follows:
;	Resource	Enabled		Address
;	FDC		Yes		PRI	3F0-3F7
;	IDE		Yes		PRI	1F0-1F7 3F6, 3F7
;	UART1		Yes		COM1	3F8-3FF
;	UART2		Yes		COM2	2F8-2FF
;	||PORT		Yes		LPT1	3BC-3BE
;	RTC		Yes			070, 071
;	KBC		Yes			060, 064
;
;
*/

.sioInit:
	mfspr	r7,8			/* save link register */
/*
;
;	check the type of superI/O that we're dealing with (read the
;	identifier register of the 87303/87323), all possible locations
;	are checked, this is done in the case the configuration straps
;	are not installed correctly, this will give us the ability to
;	have basic serial COM for console I/O
;
*/
	/*
	 *	Get base addr of ISA I/O space
	 */
	lis	r6,HI(CPU_PCI_ISA_IO_ADRS)
	ori	r6,r6,LO(CPU_PCI_ISA_IO_ADRS)
/*
 *	Probe the 4 possible locations of the SIO's Index Register
 *	in ISA I/O space.
 *		398/399
 *		26E/26F
 *		15C/15D
 *		02E/02F
 */
	addi	r3,r6,0x0398		/* Get superI/O 87303/87323 base */
	addi	r4,r0,SIO_SID		/* load identifier register offset */
	bl	.sio_br
	addi	r4,r0,0x0398		/* Get superI/O 87303/87323 base */
	andi.	r3,r3,SIO_SIDMASK	/* mask to identifier bits */
	cmpli	0,0,r3,SIO_SID87303	/* is it a 87303? */
	bc	12,2,.sioInit_87303	/* if equal, yes, goto to 87303 init */
	cmpli	0,0,r3,SIO_SID87323	/* is it a 87323? */
	bc	12,2,.sioInit_87303	/* if equal, yes, goto to 87303 init */

	addi	r3,r6,0x026E		/* Get superI/O 87303/87323 base */
	addi	r4,r0,SIO_SID		/* load identifier register offset */
	bl	.sio_br
	addi	r4,r0,0x026E		/* Get superI/O 87303/87323 base */
	andi.	r3,r3,SIO_SIDMASK	/* mask to identifier bits */
	cmpli	0,0,r3,SIO_SID87303	/* is it a 87303? */
	bc	12,2,.sioInit_87303	/* if equal, yes, goto to 87303 init */
	cmpli	0,0,r3,SIO_SID87323	/* is it a 87323? */
	bc	12,2,.sioInit_87303	/* if equal, yes, goto to 87303 init */

	addi	r3,r6,0x015C		/* Get superI/O 87303/87323 base */
	addi	r4,r0,SIO_SID		/* load identifier register offset */
	bl	.sio_br
	addi	r4,r0,0x015C		/* Get superI/O 87303/87323 base */
	andi.	r3,r3,SIO_SIDMASK	/* mask to identifier bits */
	cmpli	0,0,r3,SIO_SID87303	/* is it a 87303? */
	bc	12,2,.sioInit_87303	/* if equal, yes, goto to 87303 init */
	cmpli	0,0,r3,SIO_SID87323	/* is it a 87323? */
	bc	12,2,.sioInit_87303	/* if equal, yes, goto to 87303 init */

	addi	r3,r6,0x002E		/* Get superI/O 87303/87323 base */
	addi	r4,r0,SIO_SID		/* load identifier register offset */
	bl	.sio_br
	addi	r4,r0,0x002E		/* Get superI/O 87303/87323 base */
	andi.	r3,r3,SIO_SIDMASK	/* mask to identifier bits */
	cmpli	0,0,r3,SIO_SID87303	/* is it a 87303? */
	bc	12,2,.sioInit_87303	/* if equal, yes, goto to 87303 init */
	cmpli	0,0,r3,SIO_SID87323	/* is it a 87323? */
/*
;
;	if we make it here, the SIO device is not a 87303/87323 type,
;	check for an 87308 SIO device type (PnP capable), for right
;	now only motherboard mode addresses will be probed
;
;
;	87308 initialization
;
*/
.sioInit_87308:

/*
;
;	determine the base address (motherboard mode - 15C/15D, 2E/2F)
;
*/
	/*
	 *	Get base addr of ISA I/O space
	 */
	lis	r6,HI(CPU_PCI_ISA_IO_ADRS)
	ori	r6,r6,LO(CPU_PCI_ISA_IO_ADRS)

	addi	r3,r6,0x002E		/* adjust to superI/O 87308 base */
	addi	r4,r0,SIO_SIDPNP	/* select SID register */
	bl	.sio_br
	andi.	r3,r3,SIO_SIDMASK	/* mask to identifier bits */
	cmpli	0,0,r3,SIO_SID87308	/* is it a 87308? */
	addi	r4,r0,0x002E		/* adjust to superI/O 87308 base */
	bc	12,2,.sioInit_87308_fa	/* if equal, yes, goto to 87308 init */

	addi	r3,r6,0x015C		/* adjust to superI/O 87308 base */
	addi	r4,r0,SIO_SIDPNP	/* select SID register */
	bl	.sio_br
	andi.	r3,r3,SIO_SIDMASK	/* mask to identifier bits */
	cmpli	0,0,r3,SIO_SID87308	/* is it a 87308? */
	addi	r4,r0,0x015C		/* adjust to superI/O 87308 base */
	bc	12,2,.sioInit_87308_fa	/* if equal, yes, goto to 87308 init */

	b	.sioInit_done		/* don't know what to do... */

.sioInit_87308_fa:
	add	r6,r6,r4		/* add offset to base */
	or	r3,r6,r6		/* make a copy */
/*
;	enable PS/2 mode in SIO configuration register #1
*/
	addi	r4,r0,SIO_CNFG1		/* select CNFG1 */
	bl	.sio_br
	andi.	r5,r3,0xFB		/* keep all but PS/2-AT mode bit */
	addi	r4,r0,SIO_CNFG1		/* select CNFG1 */
	or	r3,r6,r6		/* make a copy */
	bl	.sio_bw
/*
;	KBC (LUN 0)
*/
	addi	r4,r0,SIO_LUNINDEX	/* select KBC LUN */
	addi	r5,r0,0x0
	bl	.sio_bw
	addi	r4,r0,SIO_ACTIVATE	/* disable KBC */
	addi	r5,r0,SIO_LUNDISABLE
	bl	.sio_bw
	addi	r4,r0,SIO_LUNCNFGR	/* initialize KBC clock to 8 Mhz */
	addi	r5,r0,0x0
	bl	.sio_bw
	addi	r4,r0,SIO_DBASEHI	/* initialize KBC data base address to 0x060 */
	addi	r5,r0,0x00
	bl	.sio_bw
	addi	r4,r0,SIO_DBASELO
	addi	r5,r0,0x60
	bl	.sio_bw
	addi	r4,r0,SIO_CBASEHI	/* initialize KBC command base address to 0x064 */
	addi	r5,r0,0x00
	bl	.sio_bw
	addi	r4,r0,SIO_CBASELO
	addi	r5,r0,0x64
	bl	.sio_bw
	addi	r4,r0,SIO_ACTIVATE	/* enable KBC */
	addi	r5,r0,SIO_LUNENABLE
	bl	.sio_bw
/*
;	FDC (LUN 3)
*/
	addi	r4,r0,SIO_LUNINDEX	/* select FDC LUN */
	addi	r5,r0,0x3
	bl	.sio_bw
	addi	r4,r0,SIO_IOBASEHI	/* initialize FDC address to 0x3F0 */
	addi	r5,r0,0x03
	bl	.sio_bw
	addi	r4,r0,SIO_IOBASELO
	addi	r5,r0,0xF0
	bl	.sio_bw
	addi	r4,r0,SIO_LUNCNFGR	/* initialize FDC to PS-2 mode */
	addi	r5,r0,0x40
	bl	.sio_bw
	addi	r4,r0,SIO_ACTIVATE	/* enable FDC */
	addi	r5,r0,SIO_LUNENABLE
	bl	.sio_bw
/*
;	COM2 (LUN 5)
*/
	addi	r4,r0,SIO_LUNINDEX	/* select COM2 LUN */
	addi	r5,r0,0x5
	bl	.sio_bw
	addi	r4,r0,SIO_IOBASEHI	/* initialize COM2 address to 0x2F8 */
	addi	r5,r0,0x02
	bl	.sio_bw
	addi	r4,r0,SIO_IOBASELO
	addi	r5,r0,0xF8
	bl	.sio_bw
	addi	r4,r0,SIO_ACTIVATE	/* enable COM2 */
	addi	r5,r0,SIO_LUNENABLE
	bl	.sio_bw
/*
;	COM1 (LUN 6)
*/
	addi	r4,r0,SIO_LUNINDEX	/* select COM1 LUN */
	addi	r5,r0,0x6
	bl	.sio_bw
	addi	r4,r0,SIO_IOBASEHI	/* initialize COM1 address to 0x3F8 */
	addi	r5,r0,0x03
	bl	.sio_bw
	addi	r4,r0,SIO_IOBASELO
	addi	r5,r0,0xF8
	bl	.sio_bw
	addi	r4,r0,SIO_ACTIVATE	/* enable COM1 */
	addi	r5,r0,SIO_LUNENABLE
	bl	.sio_bw
/*
;	LPT (LUN 4)
*/
	addi	r4,r0,SIO_LUNINDEX	/* select LPT LUN */
	addi	r5,r0,0x4
	bl	.sio_bw
	addi	r4,r0,SIO_IOBASEHI	/* initialize LPT address to 0x3BC */
	addi	r5,r0,0x03
	bl	.sio_bw
	addi	r4,r0,SIO_IOBASELO
	addi	r5,r0,0xBC
	bl	.sio_bw
	addi	r4,r0,SIO_LUNCNFGR	/* Put in 87303 compatible mode. */
	addi	r5,r0,0x12
	bl	.sio_bw
	addi	r4,r0,SIO_ACTIVATE	/* enable LPT */
	addi	r5,r0,SIO_LUNENABLE
	bl	.sio_bw
	b	.sioInit_done		/* branch to done */
/*
;	87303/87323 initialization
*/
.sioInit_87303:
	add	r6,r6,r4		/* add offset to base */
	or	r3,r6,r6		/* make a copy */

	addi	r4,r0,0			/* initialize FER with 0x4F */
	addi	r5,r0,0x4F
	bl	.sio_bw
	addi	r4,r0,1			/* initialize FAR with 0x11 */
	addi	r5,r0,0x11
	bl	.sio_bw
	addi	r4,r0,9			/* initialize ASC to PS-2 mode */
	addi	r5,r0,0x40
	bl	.sio_bw
	addi	r4,r0,5			/* retrieve KBC/RTC control register */
	bl	.sio_br
	andi.	r5,r3,0xD0		/* keep KBC_CSS, CSE */
	ori	r5,r5,0x0F		/* add RTC_E, PAE, KBC_SC, KBC_E */
	or	r3,r6,r6		/* load base address of SIO device */
	bl	.sio_bw
.sioInit_done:
/*
;	for VIPER H/W we need to enable the CSx registers of the SIO
;	to point to the MCG classic RTC/NVRAM device
*/
	addis	r3,r0,CPUCRA_HI		/* load addr to CPU config reg */
	ori	r3,r3,CPUCRA_LO
	lbz	r3,0(r3)		/* read CPU config reg */
	andi.	r3,r3,PID_MASK		/* mask off unwanted data bits */
	cmpli	0,0,r3,PID_VIPER	/* is it a VIPER? */
	bc	4,2,.sioInit_viper_no	/* if not equal, no, branch */

	/*
	 *	Get base addr of ISA I/O space
	 */
	lis	r3,HI(CPU_PCI_ISA_IO_ADRS)
	ori	r3,r3,LO(CPU_PCI_ISA_IO_ADRS)

	addi	r3,r3,0x015C		/* adjust to superI/O 87308 base */
	or	r6,r3,r3		/* make a copy */
/*
;	CS0
*/
	addi	r4,r0,SIO_PCSCI		/* select PCSCIR */
	addi	r5,r0,0x00
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCD		/* select PCSCDR */
	addi	r5,r0,0x00
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCI		/* select PCSCIR */
	addi	r5,r0,0x01
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCD		/* select PCSCDR */
	addi	r5,r0,0x76
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCI		/* select PCSCIR */
	addi	r5,r0,0x02
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCD		/* select PCSCDR */
	addi	r5,r0,0x40
	bl	.sio_bw
/*
;	CS1
*/
	addi	r4,r0,SIO_PCSCI		/* select PCSCIR */
	addi	r5,r0,0x05
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCD		/* select PCSCDR */
	addi	r5,r0,0x00
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCI		/* select PCSCIR */
	addi	r5,r0,0x05
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCD		/* select PCSCDR */
	addi	r5,r0,0x70
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCI		/* select PCSCIR */
	addi	r5,r0,0x06
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCD		/* select PCSCDR */
	addi	r5,r0,0x1C
	bl	.sio_bw
/*
;	CS2
*/
	addi	r4,r0,SIO_PCSCI		/* select PCSCIR */
	addi	r5,r0,0x08
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCD		/* select PCSCDR */
	addi	r5,r0,0x00
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCI		/* select PCSCIR */
	addi	r5,r0,0x09
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCD		/* select PCSCDR */
	addi	r5,r0,0x71
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCI		/* select PCSCIR */
	addi	r5,r0,0x0A
	bl	.sio_bw
	addi	r4,r0,SIO_PCSCD		/* select PCSCDR */
	addi	r5,r0,0x1C
	bl	.sio_bw
/*
;	PMC (LUN 8)
*/
	addi	r4,r0,SIO_LUNINDEX	/* select PMC LUN */
	addi	r5,r0,0x8
	bl	.sio_bw
	addi	r4,r0,SIO_IOBASEHI	/* initialize PMC address to 0x460 */
	addi	r5,r0,0x04
	bl	.sio_bw
	addi	r4,r0,SIO_IOBASELO
	addi	r5,r0,0x60
	bl	.sio_bw
	addi	r4,r0,SIO_ACTIVATE	/* enable PMC */
	addi	r5,r0,SIO_LUNENABLE
	bl	.sio_bw
.sioInit_viper_no:
	mtspr	8,r7			/* restore link register */
	bclr	20,0			/* return to caller */
/*
; routine: sio_bw
;	this function writes a register to the SIO chip
; call:
;	sio_bw(sioaddr, regnum, value)
; return:
;	none
*/
.sio_bw:
	stb	r4,0(r3)	/* write index register with register offset */
	eieio
	sync
	stb	r5,1(r3)	/* 1st write */
	eieio
	sync
	stb	r5,1(r3)	/* 2nd write */
	eieio
	sync
	bclr	20,0		/* return to caller */
/*
; routine: sio_br
;	this function reads a register from the SIO chip
; call:
;	sioInit(sioaddr, regnum)
; return:
;	register value
*/
.sio_br:
	stb	r4,0(r3)	/* write index register with register offset */
	eieio
	sync
	lbz	r3,1(r3)	/* retrieve specified reg offset contents */
	eieio
	sync
	bclr	20,0		/* return to caller */

#endif  /* MV2300 */
/*******************************************************************************
*
* sysL2crPut - write to L2CR register of Arthur CPU
*
* This routine will write the contents of r3 to the L2CR
* register.
*             )
* From a C point of view, the routine is defined as follows:
*
*    void sysL2crPut
*             (
*             ULONG       value to write
*             )
*
* RETURNS: NA
*/

sysL2crPut:
	mtspr	1017,r3
	bclr	20,0

/*******************************************************************************
*
* sysL2crGet - read from L2CR register of Arthur CPU
*
* This routine will read the contents the L2CR register.
*
* From a C point of view, the routine is defined as follows:
*
*    UINT sysL2crGet()
*
* RETURNS: value of SPR1017 (in r3)
*/

sysL2crGet:
	mfspr	r3,1017
	bclr	20,0

/******************************************************************************
*
* sysTimeBaseLGet - Get lower half of Time Base Register
*
* This routine will read the contents the lower half of the Time
* Base Register (TBL - TBR 268).
*
* This is not a standard routine.  The library call vxTimeBaseGet returns a
* 64-bit quantity.  This is a special fix to get access to just the lower
* 32-bits of the timebase.
*
* From a C point of view, the routine is defined as follows:
*
*    UINT32 sysTimeBaseLGet(void)
*
* RETURNS: value of TBR 268 (in r3)
*/

sysTimeBaseLGet:
	mftb 3
	bclr 20,0

/******************************************************************************
*
* sysHid1Get - read from HID1 register SPR1009.
*
* This routine will read the contents the HID1 (SPR1009)
*
* From a C point of view, the routine is defined as follows:
*
*    UINT sysHid1Get()
*
* RETURNS: value of SPR1009 (in r3)
*/

sysHid1Get:
	mfspr r3,1009
	bclr 20,0