sysalib.s

VxWorkS下 MV2604的BSP源代码

/* sysALib.s - Motorola MVME2600 system-dependent assembly routines */

/* Copyright 1984-2000 Wind River Systems, Inc. */
/* Copyright 1996-1999 Motorola, Inc. All Rights Reserved */
        .data
	.globl	copyright_wind_river
	.long	copyright_wind_river

/*
modification history
--------------------
01u,08may01,pch  Add assembler abstractions (FUNC_EXPORT, FUNC_BEGIN, etc.)
01t,21jan00,dat  fixed assembler warning
01s,16feb99,mas  Added Raven3, MPC750, HID0 support (SPR 24453).
01r,07aug98,tb   added support for VMEbus DMA
01q,16apr98,dat  moved sysHid1Get() from sysLib.c to here.
01p,14apr98,ms_  merged Motorola mv2700 support
01o,22jan98,rhk  SPR 20104, correct use of HI and HIADJ macros.
01n,17dec97,srr  modified sysInByte to read value into r3.
01m,16oct97,scb  added routines to get L2CR, HID1 and put L2CR.
01l,08oct97,srr  removed second disabling of GLANCE.
01k,05nov97,mas  added eieio/sync pair to sysMemProbeSup() (SPR 9717).
01j,25jul97,srr/ added 604r (Mach 5) support (SPR 8911).
            mas
01i,14jul97,mas  added sysMemProbeSup(), sysIn16(), sysOut16(), sysIn32(),
		 sysOut32() (SPR 8022).
01h,29may97,srr  Duplicate the GLANCE, RAVEN, and SIO code in sysALib.s as in
		 romInit.s. Chg the RAVEN #defines to support vxMemProbe and
		 replace the hard coded values with #defines.  Replace the
		 isync instructions with eieio in sysPci... routines.
		 (MCG MR #67, 69, 74). SPRs 8289, 8560.
01g,06may97,mas  added extended VME support: 0xfef8 -> FALCON_BASE_UPPER_ADRS
		 (SPR 8410).
01f,24apr97,mas  added Moto support for MPIC: sysPciRead32, sysPciWrite32
		 (SPR 8170).
01e,11apr97,mas  added sysPciInByte, sysPciOutByte, sysPciInWord, sysPciOutWord,
                 sysPciInLong, sysPciOutLong; removed doPciCSA, pciIoSync
                 (SPR 8226).
01d,19feb97,mas  in sysInit changed BOOT_COLD to BOOT_WARM_AUTOBOOT (SPR 8024).
01c,02jan97,dat  documentation, mod history fix
01b,17dec96,mas  moved sysPciIo.s contents here (SPR 7525).
01a,01sep96,mot  written (mv1603/sysALib.s ver 01k)
*/

/*
DESCRIPTION
This module contains system-dependent routines written in assembly
language.

This module must be the first specified in the \f3ld\f1 command used to
build the system.  The sysInit() routine is the system start-up code.
*/

#define _ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "config.h"
#include "regs.h"	
#include "asm.h"

	/* globals */

	FUNC_EXPORT(_sysInit)		/* start of system code */
	FUNC_EXPORT(sysInByte)
	FUNC_EXPORT(sysOutByte)
	FUNC_EXPORT(sysIn16)
	FUNC_EXPORT(sysOut16)
	FUNC_EXPORT(sysIn32)
	FUNC_EXPORT(sysOut32)
        FUNC_EXPORT(sysPciRead32)
        FUNC_EXPORT(sysPciWrite32)
        FUNC_EXPORT(sysPciInByte)
        FUNC_EXPORT(sysPciOutByte)
        FUNC_EXPORT(sysPciInWord)
        FUNC_EXPORT(sysPciOutWord)
        FUNC_EXPORT(sysPciInLong)
        FUNC_EXPORT(sysPciOutLong)
        FUNC_EXPORT(sysMemProbeSup)
        FUNC_EXPORT(sysProbeExc)
	FUNC_EXPORT(sysL2crPut)
	FUNC_EXPORT(sysL2crGet)
	FUNC_EXPORT(sysTimeBaseLGet)
	FUNC_EXPORT(sysHid1Get)


	/* externals */

	.extern usrInit
	
	.text

/*******************************************************************************
*
* sysInit - start after boot
*
* This is the system start-up entry point for VxWorks in RAM, the
* first code executed after booting.  It disables interrupts, sets up
* the stack, and jumps to the C routine usrInit() in usrConfig.c.
*
* The initial stack is set to grow down from the address of sysInit().  This
* stack is used only by usrInit() and is never used again.  Memory for the
* stack must be accounted for when determining the system load address.
*
* NOTE: This routine should not be called by the user.
*
* RETURNS: N/A

* sysInit (void)              /@ THIS IS NOT A CALLABLE ROUTINE @/

*/

_sysInit:

	/* disable external interrupts */

	xor	p0, p0, p0
        mtmsr   p0                      /* clear the MSR register  */

        /* Zero-out registers: r0 & SPRGs */

        xor     r0,r0,r0
        mtspr   272,r0
        mtspr   273,r0
        mtspr   274,r0
        mtspr   275,r0

        /*
         *      Set MPU/MSR to a known state
         *      Turn on FP
         */

        andi.   r3, r3, 0
        ori     r3, r3, 0x2000
        sync
        mtmsr   r3
        isync

        /* Init the floating point control/status register */

        mtfsfi  7,0x0
        mtfsfi  6,0x0
        mtfsfi  5,0x0
        mtfsfi  4,0x0
        mtfsfi  3,0x0
        mtfsfi  2,0x0
        mtfsfi  1,0x0
        mtfsfi  0,0x0
        isync

        /* Initialize the floating point data registers to a known state */

        bl      ifpdrValue
        .long   0x3f800000      /* 1.0 */
ifpdrValue:
        mfspr   r3,8
        lfs     f0,0(r3)
        lfs     f1,0(r3)
        lfs     f2,0(r3)
        lfs     f3,0(r3)
        lfs     f4,0(r3)
        lfs     f5,0(r3)
        lfs     f6,0(r3)
        lfs     f7,0(r3)
        lfs     f8,0(r3)
        lfs     f9,0(r3)
        lfs     f10,0(r3)
        lfs     f11,0(r3)
        lfs     f12,0(r3)
        lfs     f13,0(r3)
        lfs     f14,0(r3)
        lfs     f15,0(r3)
        lfs     f16,0(r3)
        lfs     f17,0(r3)
        lfs     f18,0(r3)
        lfs     f19,0(r3)
        lfs     f20,0(r3)
        lfs     f21,0(r3)
        lfs     f22,0(r3)
        lfs     f23,0(r3)
        lfs     f24,0(r3)
        lfs     f25,0(r3)
        lfs     f26,0(r3)
        lfs     f27,0(r3)
        lfs     f28,0(r3)
        lfs     f29,0(r3)
        lfs     f30,0(r3)
        lfs     f31,0(r3)
        sync

        /*
         *      Set MPU/MSR to a known state
         *      Turn off FP
         */

        andi.   r3, r3, 0
        sync
        mtmsr   r3
        isync

        /* Init the Segment registers */

        andi.   r3, r3, 0
        isync
        mtsr    0,r3
        isync
        mtsr    1,r3
        isync
        mtsr    2,r3
        isync
        mtsr    3,r3
        isync
        mtsr    4,r3
        isync
        mtsr    5,r3
        isync
        mtsr    6,r3
        isync
        mtsr    7,r3
        isync
        mtsr    8,r3
        isync
        mtsr    9,r3
        isync
        mtsr    10,r3
        isync
        mtsr    11,r3
        isync
        mtsr    12,r3
        isync
        mtsr    13,r3
        isync
        mtsr    14,r3
        isync
        mtsr    15,r3
        isync

#ifndef MV2300
        /* Turn off the GLANCE - L2 Cache */

        lis     r3, HI(MV2600_SXCCR_A)
        ori     r3, r3, (MV2600_SXCCR_A & 0xFFFF) /* Hack to remove warning */
	addis	r4, r0, 0x0
	ori	r4, r4, 0x0070
	stb	r4, 0x0(r3)
#endif  /* MV2300 */

        /* return from decrementer exceptions */

        addis   p1, r0, 0x4c00
        addi    p1, p1, 0x0064          /* load rfi (0x4c000064) to p1      */
        stw     p1, 0x900(r0)           /* store rfi at 0x00000900          */

	/* initialize the stack pointer */
	
	lis     sp, HIADJ(RAM_LOW_ADRS)
	addi    sp, sp, LO(RAM_LOW_ADRS)
	
        /* Turn off data and instruction cache control bits */

        mfspr   r3, HID0
        isync
        rlwinm  r4, r3, 0, 18, 15       /* r4 has ICE and DCE bits cleared */
        sync
        isync
        mtspr   HID0, r4                /* HID0 = r4 */
        isync

        /* Get cpu type */

        mfspr   r28, PVR
        rlwinm  r28, r28, 16, 16, 31

        /* invalidate the MPU's data/instruction caches */

        lis     r3, 0x0
        cmpli   0, 0, r28, CPU_TYPE_750
        beq     cpuIs750
        cmpli   0, 0, r28, CPU_TYPE_603
        beq     cpuIs603
        cmpli   0, 0, r28, CPU_TYPE_603E
        beq     cpuIs603
        cmpli   0, 0, r28, CPU_TYPE_603P
        beq     cpuIs603
        cmpli   0, 0, r28, CPU_TYPE_604R
        bne     cpuNot604R

cpuIs604R:
        lis     r3, 0x0
        mtspr   HID0, r3        /* disable the caches */
        isync
        ori     r4, r4, 0x0002  /* disable BTAC by setting bit 30 */

cpuNot604R:
        ori     r3, r3, 0x0C00          /* r3 has invalidate bits set */
cpuIs603:
        ori     r3, r3, 0xC000          /* r3 has enable and bits set */
        or      r4, r4, r3              /* set bits */
        sync
        isync
        mtspr   HID0, r4                /* HID0 = r4 */
        andc    r4, r4, r3              /* clear bits */
        isync
        cmpli   0, 0, r28, CPU_TYPE_604
        beq     cpuIs604
        cmpli   0, 0, r28, CPU_TYPE_604E
        beq     cpuIs604
        cmpli   0, 0, r28, CPU_TYPE_604R
        beq     cpuIs604
        cmpli   0, 0, r28, CPU_TYPE_750
        beq     cpuIs604
        mtspr   HID0, r4
        isync

#ifdef USER_I_CACHE_ENABLE
        b       iCacheOn603
#else
        b       cacheEnableDone
#endif

cpuIs750:
#ifdef USER_I_CACHE_ENABLE
        mfspr   r3,HID0
        sync
        addi    r4,r0,0x0800
        or      r3,r4,r3
        mtspr   HID0,r3         /* set ICFI (bit 16) */
        sync

        andc    r3,r3,r4
        mtspr   HID0,r3         /* clear ICFI (bit 16) */
        sync

        addi    r4,r0,0xFFFFDFFF    /* Clear ILOCK (bit 18) */
        and     r3,r3,r4
        mtspr   HID0,r3
        sync

        ori     r3,r3,0x8000    /* Set ICE (bit 16) */
        mtspr   HID0,r3
        sync
#endif
        b       cacheEnableDone

cpuIs604:
        lis     r5, 0x0
        ori     r5, r5, 0x1000
        mtspr   CTR, r5
loopDelay:
        nop
        bdnz    loopDelay
        isync
        mtspr   HID0, r4
        isync

        /* turn the Instruction cache ON */

#ifdef USER_I_CACHE_ENABLE
        
        ori     r4, r4, 0x8800          /* set ICE & ICFI bit */
        isync                           /* Synchronize for ICE enable */
        b       writeR4
iCacheOn603:
        ori     r4, r4, 0x8800          /* set ICE & ICFI bit */
        rlwinm  r3, r4, 0, 21, 19       /* clear the ICFI bit */

        /*
         * The setting of the instruction cache enable (ICE) bit must be
         * preceded by an isync instruction to prevent the cache from being
         * enabled or disabled while an instruction access is in progress.
         */
        isync
writeR4:
        mtspr   HID0, r4                /* Enable Instr Cache & Inval cache */
        cmpli   0, 0, r28, CPU_TYPE_604
        beq     cacheEnableDone
        cmpli   0, 0, r28, CPU_TYPE_604E
        beq     cacheEnableDone
        cmpli   0, 0, r28, CPU_TYPE_604R
        beq     cacheEnableDone
        cmpli   0, 0, r28, CPU_TYPE_750
        beq     cacheEnableDone

        mtspr   HID0, r3                /* using 2 consec instructions */
                                        /* PPC603 recommendation */
#endif
cacheEnableDone:

        /* Enhance execution based on cpu type */

        cmpli   0, 0, r28, CPU_TYPE_603
        beq     raven3
        cmpli   0, 0, r28, CPU_TYPE_603E
        beq     raven3
        cmpli   0, 0, r28, CPU_TYPE_603P
        beq     raven3

        /* enable branch history table for the 604 and 750 */

        mfspr   r3, HID0
        ori     r3, r3, _PPC_HID0_BHTE
        cmpli   0, 0, r28, CPU_TYPE_750
        beq     enhanceAll

        /*
         * CPU is not 750 or 603x so it must be a 604x.
         * Disable sequential instruction execution (go superscalar) and
         * enable branch history table for the 604.
         */

        ori     r3, r3, _PPC_HID0_SIED

enhanceAll:
        mtspr   HID0, r3

raven3:

/* 
 * Disable Raven3's Watchdog Timers.
 *
 * Note: Both of Raven3's Watchdog timers must be disabled at powerup.
 * Otherwise Watchdog Timer 1 will time out in 512 msec and interrupt the 
 * board, Watchdog Timer 2 will time out in 576 msec and reset the board.
 */
        lis     r3,HI(RAVEN_BASE_ADRS)
        ori     r3, r3, LO(RAVEN_BASE_ADRS)

        isync                                   /* synchronize */

        lbz     r4,RAVEN_MPC_REVID(r3)          /* read REVID register */
        eieio                                   /* synchronize */
        sync                                    /* synchronize */
        cmpli   0,0,r4,0x3                      /* Raven version 3 or above? */
        bc      12,0,nodiswdog                  /* skip if Raven2 or lower */

        addis   r4,r0,0x0000                    /* disable Watchdog Timers */
        ori     r4,r4,0x0055                    /* load PATTERN_1 */
        isync                                   /* synchronize */
        stb     r4, RAVEN_MPC_WDT1CNTL(r3)      /* arm Watchdog Timer 1 */
        eieio                                   /* synchronize */
        sync                                    /* synchronize */

        addis   r4,r0,0x0000                    /* load PATTERN_2 */
        ori     r4,r4,0xaa0f                    /* max resolution */
        isync                                   /* synchronize */
        sth     r4, RAVEN_MPC_WDT1CNTL(r3)      /* disable Timer 1 */
        eieio                                   /* synchronize */
        sync                                    /* synchronize */

        addis   r4,r0,0x0000                    /* load PATTERN_1 */
        ori     r4,r4,0x0055
        isync                                   /* synchronize */
        stb     r4,RAVEN_MPC_WDT2CNTL(r3)       /* arm Watchdog Timer 2 */
        eieio                                   /* synchronize */
        sync                                    /* synchronize */

        addis   r4,r0,0x0000                    /* load PATTERN_2 */
        ori     r4,r4,0xaa0f                    /* max resolution */
        isync                                   /* synchronize */
        sth     r4,RAVEN_MPC_WDT2CNTL(r3)       /* disable Timer2 */
        eieio                                   /* synchronize */
        sync                                    /* synchronize */

nodiswdog:

	/* disable instruction and data translations in the MMU */

	sync
	mfmsr	r3			/* get the value in msr *
					/* clear bits IR and DR */
	
	rlwinm	r4, r3, 0, _PPC_MSR_BIT_DR+1, _PPC_MSR_BIT_IR - 1
	
	mtmsr	r4			/* set the msr */
	sync				/* SYNC */

	/* initialize the BAT register */

	li	p3,0	 		/* clear p0 */
	
	isync
	mtspr	IBAT0U,p3		/* SPR 528 (IBAT0U) */
	isync

	mtspr	IBAT0L,p3		/* SPR 529 (IBAT0L) */
	isync

	mtspr	IBAT1U,p3		/* SPR 530 (IBAT1U) */
	isync

	mtspr	IBAT1L,p3		/* SPR 531 (IBAT1L) */
	isync

	mtspr	IBAT2U,p3		/* SPR 532 (IBAT2U) */
	isync

	mtspr	IBAT2L,p3		/* SPR 533 (IBAT2L) */
	isync

	mtspr	IBAT3U,p3		/* SPR 534 (IBAT3U) */
	isync

	mtspr	IBAT3L,p3		/* SPR 535 (IBAT3L) */
	isync

	mtspr	DBAT0U,p3		/* SPR 536 (DBAT0U) */
	isync

	mtspr	DBAT0L,p3		/* SPR 537 (DBAT0L) */
	isync

	mtspr	DBAT1U,p3		/* SPR 538 (DBAT1U) */
	isync

	mtspr	DBAT1L,p3		/* SPR 539 (DBAT1L) */
	isync

	mtspr	DBAT2U,p3		/* SPR 540 (DBAT2U) */
	isync

	mtspr	DBAT2L,p3		/* SPR 541 (DBAT2L) */
	isync

	mtspr	DBAT3U,p3		/* SPR 542 (DBAT3U) */
	isync

	mtspr	DBAT3L,p3		/* SPR 543 (DBAT3L) */
	isync


	/*
	This following contains the entry code for the initialization code
	for the Raven, a Host PCI Bridge/Memory Controller used in
	Motorola's PowerPC based boards.
	*/

/*
#	Initialize the RAVEN MPC registers.
#	notes:
#               1. For the standard vxWorks configuration the  MPC to
#                  PCI mapping registers are
#                  initialized to the PReP model with some additions:
#
#	MPC Address Range       PCI Address Range       Definition
#       -----------------       -----------------       ------------------------
#	80000000 BF7FFFFF	00000000 3F7FFFFF	ISA/PCI I/O space
#	C0000000 FCFFFFFF	00000000 3CFFFFFF	ISA/PCI Mem space w/MPIC
#	FD000000 FDFFFFFF	00000000 00FFFFFF	ISA/PCI Mem space
#	FE000000 FE7FFFFF	00000000 007FFFFF	ISA/PCI I/O space
#
#		2. This assignments do not include the entire PReP PCI
#		   address space, this is due to the conflicting local
#		   resources of the H/W.
#
#               3. When EXTENDED_VME is defined the mapping is as follows:
#
#       MPC Address Range           PCI Address Range      Definition
# --------------------------- ---------------------------  ---------------------
# VME_A32_MSTR_LOCAL FBFFFFFF VME_A32_MSTR_LOCAL FBFFFFFF  VME address space
#       FC000000 FCFFFFFF           FC000000 FCFFFFFF      MPIC/Reg space
#       FD000000 FDFFFFFF           FD000000 FDFFFFFF      ISA/PCI Memory space
#       FE000000 FE7FFFFF           00000000 007FFFFF      ISA/PCI I/O space
#
*/
	lis	r3, HI(RAVEN_BASE_ADRS)
	ori	r3, r3, LO(RAVEN_BASE_ADRS)

	addis	r4,r0,0x0000		/* GCSR:FLBRD=0,MBT=256us */
	ori	r4,r4,0x0000		/* GCSR:FLBRD=0,MBT=256us */
	sth	r4,RAVEN_MPC_GCSR(r3)	/* write GCSR */
	eieio				/* synchronize */