universe.h

VxWorkS下 MV2604的BSP源代码

/* universe.h - VMEbus Interface Controller */

/* Copyright, 1996-1998 Wind River Systems, Inc. */
/* Copyright 1996,1997,1998 Motorola, Inc. All Rights Reserved */

/*
modification history
--------------------
01k,12jun02,kab  SPR 74987: cplusplus protection
01j,07aug98,tb   Added VMEbus DMA support
01i,14apr98,ms_  merged Motorola mv2700 support
01h,11feb98,tb   Added TAS which uses VMEbus RMW
01g,17dec97,tb   Added Universe II support; added #defines
01f,31oct97,mas  fixed VINT_MAP1* defs, added VINT_MAP0* defs. (SPR 9438).
01e,09jul97,mas  changed LVL0 to UNIVERSE_VOWN_INT; changed LINT_STAT_INT_MASK
		 from 0xd7ff to 0xf7ff; added defs for UNIVERSE_RESERVED_INT,
		 INT_LEVEL_MAP, UNIV_NUM_INT (SPR 8896).
01d,11jun97,mas  removed unused typedefs UNIV_BUS_ADRS, UNIVERSE_REG_TYPE and
		 UNIVERSE_CNFG_HDR.
01c,18feb97,mas  changed VINT...SW_IACK to VINT...SW_INT per MR #39; changed
		 UNIVERSE_VME_IACK_INT to UNIVERSE_VME_SW_INT (SPR 7811).
01b,02jan97,dat  documentation
01a,10jul96,rhk  written.
*/

#ifndef INCuniverseh
#define INCuniverseh

#ifdef __cplusplus
    extern "C" {
#endif

/*
This file contains constants for the Universe PCI-VME interface chip.
The macro UNIVERSE_BASE_ADRS must be defined when including this header.

The registers are listed in ascending (numerical) order; the definitions
for each register are started with a header eg.
*/

#ifdef  _ASMLANGUAGE
# define CASTINT
#else
# define CASTINT (unsigned int *)

/* Structure used to map Universe interrupts to priorities and vectors */

typedef struct int_level_map
{
    int  bitMask;	/* single bit set at associated Universe intr */
    int  vector;	/* vector associated with intr (-1 = query Universe) */
    int  intMask;	/* int enable mask for this level */
} INT_LEVEL_MAP;

#endif  /* _ASMLANGUAGE */

/* Type of PCI to VME bridge device */

#define UNIVERSE_I    1
#define UNIVERSE_II   2

/*
 * Number of interrupts to map in Universe 
 *
 * 32 total bits of which 15 are valid and 17 are reserved (not used),
 * one bit per interrupt.
 */

#define UNIV_NUM_INT	15

/*
 * on-board access, register definitions
 * these registers MUST BE WRITTEN 4-BYTE WRITES ONLY
 * they can be read as byte, two-bytes or 4-bytes.
 */

#ifndef UNIVERSE_ADRS   /* to permit alternative board addressing */
# define UNIVERSE_ADRS(reg)   (CASTINT (UNIVERSE_BASE_ADRS + reg )) 
#endif  /* UNIVERSE_ADRS */

/* VME interrupt level definitions */

#define	UNIVERSE_VOWN_INT	0x0001
#define LVL1			0x0002
#define LVL2			0x0004
#define LVL3			0x0008
#define LVL4			0x0010
#define LVL5			0x0020
#define LVL6			0x0040
#define LVL7			0x0080

/* additional VME interrupts supported by the UNIVERSE chip */

#define UNIVERSE_DMA_INT	0x0100  /* bit setting for DMA intr */
#define UNIVERSE_LERR_INT	0x0200  /* bit setting for PCI bus err intr */
#define UNIVERSE_VERR_INT	0x0400  /* bit setting for VMEbus err intr */
#define	UNIVERSE_RESERVED_INT	0x0800	/* reserved [DO NOT USE] */
#define UNIVERSE_VME_SW_IACK_INT 0x1000  /* bit setting for VME SW IACK intr */
#define UNIVERSE_PCI_SW_INT	0x2000  /* bit setting for SW intr */
#define UNIVERSE_SYSFAIL_INT	0x4000  /* bit setting for SYSFAIL intr */
#define UNIVERSE_ACFAIL_INT	0x8000  /* bit setting for ACFAIL intr */

#define UNIVERSE_INT_MASK	0x0000f700  /* mask for the interrupts
						defined above */

#define UNIVERSE_CNFG_OFFSET    0x100   /* offset VME specific part */

/* WRITES MUST BE 4-BYTE WRITES ONLY */

/*
 * Device ID - Newbridge allocated device ident    0x00    31-16
 * Vendor ID - PCI SIG allocated vendor identifier 0x00    15-00
 */

#define UNIVERSE_PCI_ID         UNIVERSE_ADRS(0x00)

/* PCI Configuration Space Control and Status Reg  0x00    31-00 */

#define UNIVERSE_PCI_CSR        UNIVERSE_ADRS(0x04)

/*
 * PCI Configuration Class Register
 * PCI Base Class Code - "PCI bridge device"       0x10    31-24
 * PCI Sub Class Code - "other bridge device"      0x10    23-16
 * PCI Programming Interface - (Not Applicable)    0x10    15-08
 * Revision ID                                     0x10    07-00
 */

#define UNIVERSE_PCI_CLASS      UNIVERSE_ADRS(0x08)

/* PCI Configuration Miscellaneous 0 Register      0x00    31-00 */

#define UNIVERSE_PCI_MISC0      UNIVERSE_ADRS(0x0c)

/*
 * PCI Base Address Register                       0x08    31-16
 * PCI Bus Address Space Register                  0x08    15-00
 */

#define UNIVERSE_PCI_BS         UNIVERSE_ADRS(0x10)

/* PCI Configuration Miscellaneous 1 Register      0x00    31-00 */

#define UNIVERSE_PCI_MISC1      UNIVERSE_ADRS(0x3c)

/* PCI Slave Image 0 Control Register              0x100   31-00 */

#define UNIVERSE_LSI0_CTL       UNIVERSE_ADRS(0x100)

/*
 * PCI Slave Image 0 Base Address Register         0x104   31-12
 * Universe Reserved                               0x104   11-00
 */

#define UNIVERSE_LSI0_BS        UNIVERSE_ADRS(0x104)

/*
 * PCI Slave Image 0 Bound Address Register        0x108   31-12
 * Universe Reserved                               0x108   11-00
 */

#define UNIVERSE_LSI0_BD        UNIVERSE_ADRS(0x108)

/*
 * PCI Slave Image 0 Translation Offset            0x10C   31-12
 * Universe Reserved                               0x10C   11-00
 */

#define UNIVERSE_LSI0_TO        UNIVERSE_ADRS(0x10c)

/* PCI Slave Image 1 Control Register              0x114   31-00 */

#define UNIVERSE_LSI1_CTL       UNIVERSE_ADRS(0x114)

/*
 * PCI Slave Image 1 Base Address Register         0x118   31-12
 * Universe Reserved                               0x118   11-00
 */

#define UNIVERSE_LSI1_BS        UNIVERSE_ADRS(0x118)

/*
 * PCI Slave Image 1 Bound Address Register        0x11C   31-12
 * Universe Reserved                               0x11C   11-00
 */

#define UNIVERSE_LSI1_BD        UNIVERSE_ADRS(0x11C)

/*
 * PCI Slave Image 1 Translation Offset            0x120   31-12
 * Universe Reserved                               0x120   11-00
 */

#define UNIVERSE_LSI1_TO        UNIVERSE_ADRS(0x120)

/* PCI Slave Image 2 Control Register              0x128   31-00 */

#define UNIVERSE_LSI2_CTL       UNIVERSE_ADRS(0x128)

/*
 * PCI Slave Image 2 Base Address Register         0x12C   31-12
 * Universe Reserved                               0x12C   11-00
 */

#define UNIVERSE_LSI2_BS        UNIVERSE_ADRS(0x12C)

/*
 * PCI Slave Image 2 Bound Address Register        0x130   31-12
 * Universe Reserved                               0x130   11-00
 */

#define UNIVERSE_LSI2_BD        UNIVERSE_ADRS(0x130)

/*
 * PCI Slave Image 2 Translation Offset            0x134   31-12
 * Universe Reserved                               0x134   11-00
 */

#define UNIVERSE_LSI2_TO        UNIVERSE_ADRS(0x134)

/* PCI Slave Image 3 Control Register              0x13C   31-00 */

#define UNIVERSE_LSI3_CTL       UNIVERSE_ADRS(0x13C)

/*
 * PCI Slave Image 3 Base Address Register         0x140   31-12
 * Universe Reserved                               0x140   11-00
 */

#define UNIVERSE_LSI3_BS        UNIVERSE_ADRS(0x140)

/*
 * PCI Slave Image 3 Bound Address Register        0x144   31-12
 * Universe Reserved                               0x144   11-00
 */

#define UNIVERSE_LSI3_BD        UNIVERSE_ADRS(0x144)

/*
 * PCI Slave Image 3 Translation Offset            0x148   31-12
 * Universe Reserved                               0x148   11-00
 */

#define UNIVERSE_LSI3_TO        UNIVERSE_ADRS(0x148)

/*
 * Universe Reserved                               0x170   31-02
 * Special Cycle                                   0x170   01-00
 */

#define UNIVERSE_SCYC_CTL       UNIVERSE_ADRS(0x170)

/*
 * Address for Special Cycle                       0x174   31-02
 * Universe Reserved                               0x174   01-00
 */

#define UNIVERSE_SCYC_ADDR      UNIVERSE_ADRS(0x174)

/* Special Cycle Bit Enable Mask                   0x178   31-00 */

#define UNIVERSE_SCYC_EN        UNIVERSE_ADRS(0x178)

/* Special Cycle Compare Register                  0x178   31-00 */

#define UNIVERSE_SCYC_CMP       UNIVERSE_ADRS(0x17c)

/* Special Cycle Swap Register                     0x178   31-00 */

#define UNIVERSE_SCYC_SWP       UNIVERSE_ADRS(0x180)

/* Other Registers */

#define UNIVERSE_LMISC          UNIVERSE_ADRS(0x184)
#define UNIVERSE_SLSI           UNIVERSE_ADRS(0x188)
#define UNIVERSE_L_CMDERR       UNIVERSE_ADRS(0x18c)
#define UNIVERSE_LAERR          UNIVERSE_ADRS(0x190)
#define UNIVERSE_DCTL           UNIVERSE_ADRS(0x200)
#define UNIVERSE_DTBC           UNIVERSE_ADRS(0x204)
#define UNIVERSE_DLA            UNIVERSE_ADRS(0x208)
#define UNIVERSE_DVA            UNIVERSE_ADRS(0x210)
#define UNIVERSE_DCPP           UNIVERSE_ADRS(0x218)
#define UNIVERSE_DGCS           UNIVERSE_ADRS(0x220)
#define UNIVERSE_D_LLUE         UNIVERSE_ADRS(0x224)
#define UNIVERSE_LINT_EN        UNIVERSE_ADRS(0x300)
#define UNIVERSE_LINT_STAT      UNIVERSE_ADRS(0x304)
#define UNIVERSE_LINT_MAP0      UNIVERSE_ADRS(0x308)
#define UNIVERSE_LINT_MAP1      UNIVERSE_ADRS(0x30C)
#define UNIVERSE_VINT_EN        UNIVERSE_ADRS(0x310)
#define UNIVERSE_VINT_STAT      UNIVERSE_ADRS(0x314)
#define UNIVERSE_VINT_MAP0      UNIVERSE_ADRS(0x318)
#define UNIVERSE_VINT_MAP1      UNIVERSE_ADRS(0x31C)
#define UNIVERSE_STATID         UNIVERSE_ADRS(0x320)
#define UNIVERSE_V1_STATID      UNIVERSE_ADRS(0x324)
#define UNIVERSE_V2_STATID      UNIVERSE_ADRS(0x328)
#define UNIVERSE_V3_STATID      UNIVERSE_ADRS(0x32C)
#define UNIVERSE_V4_STATID      UNIVERSE_ADRS(0x330)
#define UNIVERSE_V5_STATID      UNIVERSE_ADRS(0x334)
#define UNIVERSE_V6_STATID      UNIVERSE_ADRS(0x338)
#define UNIVERSE_V7_STATID      UNIVERSE_ADRS(0x33C)
#define UNIVERSE_MAST_CTL       UNIVERSE_ADRS(0x400)
#define UNIVERSE_MISC_CTL       UNIVERSE_ADRS(0x404)
#define UNIVERSE_MISC_STAT      UNIVERSE_ADRS(0x408)
#define UNIVERSE_USER_AM        UNIVERSE_ADRS(0x40C)
#define UNIVERSE_VSI0_CTL       UNIVERSE_ADRS(0xF00)
#define UNIVERSE_VSI0_BS        UNIVERSE_ADRS(0xF04)
#define UNIVERSE_VSI0_BD        UNIVERSE_ADRS(0xF08)
#define UNIVERSE_VSI0_TO        UNIVERSE_ADRS(0xF0C)
#define UNIVERSE_VSI1_CTL       UNIVERSE_ADRS(0xF14)
#define UNIVERSE_VSI1_BS        UNIVERSE_ADRS(0xF18)
#define UNIVERSE_VSI1_BD        UNIVERSE_ADRS(0xF1C)
#define UNIVERSE_VSI1_TO        UNIVERSE_ADRS(0xF20)
#define UNIVERSE_VSI2_CTL       UNIVERSE_ADRS(0xF28)
#define UNIVERSE_VSI2_BS        UNIVERSE_ADRS(0xF2C)
#define UNIVERSE_VSI2_BD        UNIVERSE_ADRS(0xF30)
#define UNIVERSE_VSI2_TO        UNIVERSE_ADRS(0xF34)
#define UNIVERSE_VSI3_CTL       UNIVERSE_ADRS(0xF3C)
#define UNIVERSE_VSI3_BS        UNIVERSE_ADRS(0xF40)
#define UNIVERSE_VSI3_BD        UNIVERSE_ADRS(0xF44)
#define UNIVERSE_VSI3_TO        UNIVERSE_ADRS(0xF48)
#define UNIVERSE_VRAI_CTL       UNIVERSE_ADRS(0xF70)
#define UNIVERSE_VRAI_BS        UNIVERSE_ADRS(0xF74)
#define UNIVERSE_VCSR_CTL       UNIVERSE_ADRS(0xF80)
#define UNIVERSE_VCSR_TO        UNIVERSE_ADRS(0xF84)
#define UNIVERSE_V_AMERR        UNIVERSE_ADRS(0xF88)
#define UNIVERSE_VAERR          UNIVERSE_ADRS(0xF8C)
#define UNIVERSE_VSI4_CTL       UNIVERSE_ADRS(0xF90)
#define UNIVERSE_VSI4_BS        UNIVERSE_ADRS(0xF94)
#define UNIVERSE_VSI4_BD        UNIVERSE_ADRS(0xF98)
#define UNIVERSE_VSI4_TO        UNIVERSE_ADRS(0xF9c)
#define UNIVERSE_VSI5_CTL       UNIVERSE_ADRS(0xFa4)
#define UNIVERSE_VSI5_BS        UNIVERSE_ADRS(0xFa8)
#define UNIVERSE_VSI5_BD        UNIVERSE_ADRS(0xFac)
#define UNIVERSE_VSI5_TO        UNIVERSE_ADRS(0xFb0)
#define UNIVERSE_VSI6_CTL       UNIVERSE_ADRS(0xFb8)