target.nr

VxWorkS下 MV2604的BSP源代码

    cp bootrom.bin /tftpboot/boot.bin
.CE

Power down the board and switch the ROM jumper to select socketed FLASH.
Connect the Ethernet and console serial port cables, then power the board back
up.

.SS "Flashing the Boot ROM Using Motorola PPC1-Bug:" 1

At the PPC1-Bug prompt, start the system clock then set up the network transfer
from a TFTP host using `niot'.  To start the system clock, the \f3set\f1
command must be used.  The format is: set MMDDYYhhmm  where MM is month, DD is
day of month, YY is year, hh is hour (24-hour format), and mm is minutes.  This
command starts the system clock and sets the current date and time.

.CS
   PPC1-Bug>set 1016971302
.CE

Using `niot', the
Client IP Address, Server IP Address, and Gateway IP Address must be set up for
the user's specific environment:

.CS
   PPC1-Bug>niot
   Controller LUN =00?
   Device LUN     =00?
   Node Control Memory Address =00FA0000?
   Client IP Address      =123.123.10.100? 123.321.12.123
   Server IP Address      =123.123.18.105? 123.321.21.100
   Subnet IP Address Mask =255.255.255.0?
   Broadcast IP Address   =255.255.255.255?
   Gateway IP Address     =123.123.10.254? 123.321.12.254
   Boot File Name ("NULL" for None)     =? .

   Update Non-Volatile RAM (Y/N)? y
   PPC1-Bug>
.CE

The file is transferred from the TFTP host to the target board using
the `niop' command.  Important: You must have a TFTP server running on your
host's subnet for the `niop' command to succeed.  The file name must be set to
the location of the binary file on the TFTP host.  The binary file must be
stored in the directory identified for TFTP accesses, but the file name is
a relative path and does not include the \f3/tftpboot\f1 directory name:

.CS
   PPC1-Bug>niop
   Controller LUN =00?
   Device LUN     =00?
   Get/Put        =G?
   File Name      =? boot.bin
   Memory Address =00004000?
   Length         =00000000?
   Byte Offset    =00000000?

   PPC1-Bug>
.CE

After the file is loaded onto the target, the `pflash' command is used
to put it into soldered FLASH parts.

.CS
   PPC1-Bug>pflash 4000:FFF00 ff000100
.CE

When the command is finished, power down the board and switch the ROM
jumper to select soldered FLASH.  Then power the board back up.

.SS "Flashing the Boot ROM Using Motorola Open Firmware:" 1

From the "ok" prompt on the console, use the `load' command to get the image
into RAM.  You must have a TFTP server running on your host's subnet for the
`load' command to succeed.  The command takes the following form:

.CS
    load /pci/ethernet@e:<host IP>,<file path/name>,<target IP>[,<gateway IP>]
.CE

.SS Note: 1
The modifiable parameter \f3load-base\f1 is set to the load-address of a
binary image to be loaded.  The factory preset value is 0x400000.

For example, \f3load-base\f1 must be modified to allow for the reserved 0x100
bytes at the beginning of a VxWorks boot image:

.CS
  ok load-base h# 100 + to load-base

  ok load /pci/ethernet@e:144.191.1.8,boot.bin,144.191.1.7

  Boot device: /pci/ethernet@e:144.191.1.8,boot.bin,144.191.1.7
  File and args:

  ok load-base h# 100 - to load-base
.CE

From the "ok" prompt, determine the starting memory address of soldered FLASH:

.CS
  ok 50 fal-l@
  fef80050  ff0b0006
            ^^^
.CE

Use the indicated first three nibbles followed by five zeros as the start
address.  In this example, the start address is ff000000.
(Note: "58 fal-l@" would return the socketed FLASH start address.)

From the "ok" prompt, use the \f3gflash\f1 command to program the image into
FLASH.  The command takes the following form:

.CS
    <start addr> <size> <flash start addr> (gflash)
.CE

To load the boot image into soldered FLASH, modify \f3load-base\f1 as follows:

.CS
  ok load-base 100000 ff000000 (gflash)

  Erasing ...
  Programming ...
  Verifying ....
  ok
.CE

Power down the board and switch the ROM jumper to select soldered FLASH.  Then
power the board back up.

.SH "SPECIAL CONSIDERATIONS"
This section describes miscellaneous information concerning this BSP and its
use.

.SS "Delivered Objects"
The delivered objects are: `bootrom.hex', `vxWorks', `vxWorks.sym', and
`vxWorks.st'.

.SS "Make Targets"
The make targets are listed as the names of object-format files.  Append `.hex'
to each to derive a hex-format file name.

.nf
`bootrom'
`bootrom_uncmp'
`bootrom_res_high'  (bootrom_res does not build)
`vxWorks' (with vxWorks.sym)
`vxWorks_rom'
`vxWorks.st'
`vxWorks.st_rom'
`vxWorks.res_rom_res_low' (vxWorks.res_rom does not build)
`vxWorks.res_rom_nosym_res_low' (vxWorks.res_rom_nosym does not build)
.fi

.SS "Special Routines"
For these boards, the value of the CPU clock speed is read from the CPU 
configuration register using the macro MEMORY_BUS_SPEED which is defined
in mv2600.h.  For example:

.CS
   clkFreqMhz = MEMORY_BUS_SPEED;
.CE

.SS "VME Interrupt Vectors"
Interrupt vectors chosen to generate normal VME interrupts under program
control must be even numbers.  

The Universe chip used on this board can be configured to generate VME bus
interrupts in response to DMA status, PCI bus conditions, and by specific
command from software.  During the VME interrupt acknowledge (IACK) cycle,
the STATUS/ID register of the Universe chip transmits an 8-bit interrupt
vector to the VME bus.  The seven most significant bits are the vector number
(hence the need for even vector numbers) and the least significant bit (LSB) is
set according to how the Universe is configured to respond to the IACK cycle.
If the interrupt was generated by software and the IACK cycle is received, the
Universe can be configured to send an acknowledging interrupt (SW_IACK)
back to the software over the PCI bus.  If the SW_IACK interrupt is enabled,
the LSB is set to 0, otherwise, it is set to 1.

The Universe chip can also be configured to receive VME interrupts.  

Note that, if software specifies an odd number as the interrupt vector to be
transmitted during the IACK cycle, the STATUS/ID register will truncate it to
an even number.  
There is no configuration option to compensate for this
feature of the Universe chip.

.SS "Known Problems"
The Universe chip provides both a VME interface and a PCI-VME bridge.  The
older Universe chip (Universe I) has numerous flaws that cause initialization
difficulties and prevent guaranteed atomic VMEbus read-modify-write (RMW)
cycles.  It is also not capable of receiving more than one VME bus interrupt
level under conditions of frequent interrupts; it may lock up and prevent
further VME bus interrupt activity.  For further information, refer to
\f2Tundra Universe Device Errata.\f1

A redesigned Universe chip (Universe II) is forthcoming 
from Tundra that addresses the known flaws.  
Later revisions of Motorola boards may utilize the new chip.

The Motorola Raven chip has a flaw which ignores PCI bus `LOCK' signals during
access of local memory from the PCI bus.  Thus, an atomic RMW transaction
from the Universe chip is not guaranteed to be atomic in local memory.  A new
chip (Raven 3) is forthcoming from Motorola and addresses this flaw.

Contact a Motorola representative for details on the new chips.

Older generation VME backplanes often do not have slot 1 (the system controller
slot) hard-wired for interrupt acknowledge (IACK) daisy chain operation,
leaving this to be done by a board plugged in to the slot.  Because the
MVME2600 family of Motorola boards does not do this, VME interrupts may not
be sensed by an MVME2600 board used as a system controller in an old VME
backplane.  New VME backplanes usually have the left-most slot P1 connector
hard-wired so that pin A20 (IACK) is connected to A21 (IACKIN).  On old VME
backplanes, the user must add a jumper between pins A20 and A21 on the wire wrap
pins behind the P1 connector of slot 1.

.SS "Pseudo-PReP Memory Model"
The following table describes the modified PowerPC Reference Platform (PReP)
address maps created for VME from the CPU point of view.  Tornado-compatible
mapping deviates only slightly from the model.

.TS E
expand;
lf3 lf3 lf3
l l lw(1.8i) .
.ne 6
.sp .5
Start	Size	Access to
_
0x0	LOCAL_MEM_SIZE (16MB min)	DRAM
LOCAL_MEM_SIZE	(0x80000000 - LOCAL_MEM_SIZE)	[Not used]
0x80000000	8MB	PCI I/O space
0x80800000	0x3f800000	[Not used]
0xC0000000	16MB	PCI MEM space
0xC1000000	0x17000000	[Not used]
0xD8000000	128MB	T{
PCI MEM (max. A32 VME space)
T}
0xE0000000	16MB	T{
PCI MEM (A24 VME space)
T}
0xE1000000	0x0EFF0000	[Not used]
0xEFFF0000	64KB	T{
PCI MEM (A16 VME space)
T}
0xF0000000	64KB	T{
PCI MEM (VME REG. (A32) space)
T}
0xF0010000	0x0BFF0000	[Not used]
0xFC000000	256KB	MPIC Reg space
0xFC040000	0x02F40000	[Not used]
0xFEF80000	128KB	Falcon/Raven regs.
0xFEFA0000	0x00060000	[Not used]
0xFF000000	16MB	T{
ROM space (No PCI/VME)
T}
.TE

.SS "VME Access in the Pseudo-PReP Memory Model" 1

The pseudo-PReP memory model does not offer much address space for mapping
VME master windows.  Only 128MB of A32 space is available.  The 128MB window
can be mapped anywhere in VME A32 space by setting the macro VME_A32_MSTR_BUS
in config.h.  The full A16 and A24 master window address spaces are mapped into
the system.

.ne 3
The master window address mappings are as follows:

.TS E
expand;
lf3 lf3 lf3 lf3
lf3 lf3 lf3 lf3
l l l l .
.ne 6
.sp .5
VME Master
Address Space	VME Base Address	Size	Local Base Address
_
A16	0x0000	64KB	0xEFFF0000
A24	0x000000	16MB	0xE0000000
A32	0x08000000	128MB	0xD8000000
A32 (Mailbox)	0x40000000	4KB	0xF0000000
.TE

The slave window address mappings are as follows:

.TS E
expand;
lf3 lf3 lf3 lf3
lf3 lf3 lf3 lf3
l l l l .
.ne 6
.sp .5
VME Slave
Address Space	VME Base Address	Size	Local Base Address
_
A16 (none)
A24 (none)
A32	0x00000000	128MB	0x00000000
A32 (Mailbox)	0x40000000	4KB	0x00001000 (PCI bus)
.TE

.SS "PCI Access in the Pseudo-PReP Memory Model" 1

The default pseudo-PReP mapping from the PCI bus point of view is:

.TS E
expand;
cf3 s s
lf3 lf3 lf3
l l l .
.ne 6
PCI I/O Space Access
.sp .5
Start	Size	Access to
_
0x00000000	8MB	PCI I/O space
0x00000000	64KB	ISA I/O space
0x00001000	4KB (fixed)	VME mailbox slave space
.TE

.TS E
expand;
cf3 s s
lf3 lf3 lf3
l l l .
.ne 6
PCI MEM Space Access
.sp .5
Start	Size	Access to
_
0x80000000	16MB (min)	DRAM space
0x18000000	16MB (std)	VME A32 master space
0x20000000	16MB (max)	VME A24 master space
0x2FFF0000	64KB (max)	VME A16 master space
0x30000000	64KB (fixed)	VME mailbox (A32) space
0x7C000000	256KB (fixed)	MPIC REGS
.TE

.SH "BOARD LAYOUT"
The diagram below shows flash EEPROM locations and jumpers relevant to VxWorks
configuration:

For the MVME260x boards, serial ports 1 through 4, the Ethernet port, and the
SCSI port appear on the VME P2 connector for use with the MVME712/MVME761
Transition Module.

.ne 4i

.bS
______________________________               ______________________________
|             P1             |    MVME260x   |             P2              |
|                            ----------------                              |
| " <-- J3 (L2 Cache)         Needs MVME712   J22 (system contoller) --> U |
|                              or MVME761                                  |
|                            Transition Module                             |
|                                                                          |
|                                                                          |
|                                                                          |
|------------------------------------------------                          |
|        Mezzanine Board                        |                          |
|                                               |                          |
|            ----                               |                          |
|            ====                               |                          |
|            ==== <== VxWorks boot flash        |                          |
|            ====     (soldered)                |                          |
|            ----                               |                          |
|                                               |                          |
|                                               |                          |
|                    +----+   +----+            |                          |
| Open Firmware==> X |    | X |    |            |                          |
| or PPC1-Bug      U |    | U |    |            |     J10 (ROM ctrl) --> D |
|                  1 +----+ 2 +----+            |                          |
|                                               |                          |
|       Floppy/LED             Keyboard  Mouse  |      PMC 1               |
|______-------------____________-----____-----__|_...................._____|
.bE
    Key: 
    X  vertical jumper installed
    :  vertical jumper absent
    -  horizontal jumper installed
    "  horizontal jumper absent
    0  switch off
    1  switch on
    U  three-pin vertical jumper, upper jumper installed
    D  three-pin vertical jumper, lower jumper installed
    L  three-pin horizontal jumper, left jumper installed
    R  three-pin horizontal jumper, right jumper installed

.SH "SEE ALSO"
.tG "Getting Started,"
.pG "Configuration"

.SH "BIBLIOGRAPHY"
.iB "Motorola MVME2600 Series Single Board Computer Programmer's Reference Guide,"
.iB "MVME761 Transition Module Installation and Use,"
.iB "MVME712M Transition Module and P2 Adapter Board User's Manual,"
.iB "Motorola PowerPC 603 RISC Microprocessor User's Manual,"
.iB "Motorola PowerPC 604 RISC Microprocessor User's Manual,"
.iB "Motorola PowerPC Microprocessor Family: The Programming Environments,"
.iB "Motorola MPC2604GA Integrated Secondary Cache for PowerPC Microprocessors (Glance) Data Sheets,"
.iB "Cirrus Logic Alpine VGA Family - CL-GD543X/4X Technical Reference Manual,"
.iB "DECchip 21140 PCI Fast Ethernet LAN Controller Hardware Reference Manual,"
.iB "National Semiconductor PC87308VUL (Super I/O Enhanced Sidewinder Lite) PC Controller Manual,"
.iB "SGS-Thompson MK48T59/559 CMOS 8K x 8 TIMEKEEPER SRAM Data Sheet,"
.iB "SYM53Cxx (was NCR53C8xx) Family PCI-SCSI I/O Processors Programming Guide,"
.iB "Zilog SCC (Serial Communications Controller) User's Manual,"
.iB "Zilog ZCIO Counter/Timer and Parallel I/O Unit User's Manual,"
.iB "Winbond W83C553 Enhanced System I/O Controller with PCI Arbiter Data Book,"
.iB "Tundra Universe User Manual,"
.iB "Tundra Universe Device Errata,"
.iB "ANSI/VITA 1-1994 VME64 Specification,"
.iB "ANSI/IEEE 1014-1987 Versatile Backplane Bus: VMEbus,"
.iB "IEEE P1386 Draft 2.0 - Common Mezzanine Card Specification (CMC),"
.iB "IEEE P1386.1 Draft 2.0 - PCI Mezzanine Card Specification (PMC),"
.iB "IEEE Standard 1284 Bidirectional Parallel Port Interface Specification,"
.iB "Peripheral Component Interconnect (PCI) Local Bus Specification, Rev 2.1,"
.iB "PCI to PCI Bridge Architecture Specification 2.0,"
.iB "ANSI X3.131.1990 Small Computer System Interface-2 (SCSI-2) Draft Document"