target.nr

VxWorkS下 MV2604的BSP源代码

To perform a PowerPC atomic access, it disables interrupts (to prevent
deadlocks) and issues the lwarx/stwcx sequence.

When the sysBusTasClear() routine performs a true-atomic clear operation, it
disables interrupts (to prevent deadlocks) and performs a VME RMW cycle.
To perform a pseudo-atomic clear operation, it
also disables interrupts and locks the VMEbus while
accessing the semaphore.
It waits up to 10 microseconds to gain bus ownership.  But, even if
the bus is not owned after this period, the routine attempts to clear the
semaphore.
The sysBusTasClear() routine does not perform a PowerPC atomic access.
Instead, it can perform a simple clear operation when all boards in the 
system are capable of performing a VME RMW cycle.

Special consideration must be given to boards not using this BSP in the
overall system design.  A board that utilizes RMW as its TAS operation
can be used as a master if and only if
all other boards (slaves) in the system utilize a RMW capability.  There
are no restrictions when boards not using this BSP are used as a slave.

.SS "Board Revision Determination"
Since components are now present on both sides of most boards, we
define the top of the board as the side on which the VME connecters
P1 and P2 are mounted.

On the bottom of the board, between the P1 and P2 VME connectors, there
is a yellow silk screened box and the letters "S/N". 
This is the serial number of the board, and in that area there should 
be a sticker with a bar code and a serial number.

Immediately below the serial number region will be a number
in yellow silk-screen. Immediately following this number should be
a sticker, with a few digits followed by a letter (e.g. 06C). This
final letter is the board revision level.

.SS "Interrupts"
The system interrupt vector table has 256 entries.  Vectors for the various
devices on the buses are assigned hierarchically as follows:

.TS C
center;
lf3 lf3
l lw(2.6i) .
.ne 6
.sp .5
Vector#	Assigned to
_
00 - 0f	ISA IRQ numbers 0 - 15
10 - 1f	All MPIC interrupts
20 - 23	Raven timers
24 - 27	Raven interprocessor dispatch
   28  	Raven detected internal errors
29 - 55	[User defined]
56 - 5f	Universe-specific interrupts
60 - ff	[User defined]
.TE

The specific ISA vector number assignments are:

.TS C
center;
lf3 lf3
l lw(2.6i) .
.ne 6
.sp .5
Vector#	Assigned to
_
   02	[Cascade interrupt from PIC2]
   03	COM2
   04	COM1
   09	Aux timers; serial ports 3 and 4
.TE

Vector numbers not in the table are not used by this BSP.

The standard ISA Intel 8259 Programmable Interrupt Controllers (PICs) assert
their interrupts through the Raven MPIC as an external interrupt.  The external
interrupt vector numbers are:

.TS C
center;
lf3 lf3
l lw(2.6i) .
.ne 6
.sp .5
Vector#	Assigned to
_
   10	ISA PICs
   11	Falcon-ECC error
   12	PCI Ethernet
   13	PCI SCSI
   15	PCI Universe VME INT 0
   16	PCI Universe VME INT 1
   17	PCI Universe VME INT 2
   18	PCI Universe VME INT 3
   19	PCI PMC1/PMC2 INTA
   1a	PCI PMC1/PMC2 INTB
   1b	PCI PMC1/PMC2 INTC
   1c	PCI PMC1/PMC2 INTD
   1d	LM/SIG (mailbox) 0
   1e	LM/SIG (mailbox) 1
.TE

Vector numbers not in the table are not used by this BSP.

The Raven Multi-Processor Interrupt Controller (MPIC) sets system interrupt
priorities and serves as controller of all external interrupts.  Each
of its 16 interrupt control registers, designated IRQ0 through IRQ15, can be
programmed with a relative priority from 15, the highest, to 0, the lowest.  A
priority of zero effectively disables the interrupt.  All but one of the 16
control registers has been hardwired to a particular interrupt source.  The IRQ
number and priority assignments are as follows:

.TS E
expand;
lf3 lf3 lf3
l l lw(2.6i) .
.ne 6
.sp .5
Raven MPIC IRQ	Priority	IRQ Source
_
IRQ0	8	Winbond PIB [all ISA interrupts]
IRQ1	0	Falcon ECC Error
IRQ2	14	Ethernet
IRQ3	3	SCSI
IRQ4	0	Graphics [not available]
IRQ5	10	Universe LINT0 [all Universe/VME interrupts]
IRQ6	0	Universe LINT1
IRQ7	0	Universe LINT2
IRQ8	0	Universe LINT3
IRQ9	7	PCI PMC1/PMC2 INTA
IRQ10	6 (13)	PCI PMC1/PMC2 INTB  (Secondary Ethernet)
IRQ11	5 (2)	PCI PMC1/PMC2 INTC  (Secondary SCSI)
IRQ12	4	PCI PMC1/PMC2 INTD
IRQ13	0	LM/SIG Interrupt 0
IRQ14	15	LM/SIG Interrupt 1 (mailbox)
IRQ15	N/A	[Not used]
.TE

For further details, refer to the appropriate board's reference guide.

There are only four PCI bus interrupts: A, B, C, and D.  They are shared among
all PCI bus devices and do not have levels.  PCI bus interrupts are wired
directly to the MPIC and, therefore, have pre-assigned system vector numbers
and interrupt levels.  The user enables one or more PCI interrupts and connects
vectored ISRs to the system by following these steps:

.IP "1)"
Identify the PCI interrupt letter(s) as required by
the application. Based on this, identify the
associated system interrupt level from the following
tables:

            Primary PCI Bus
            ----------------
            A = PMC_INT_LVL1
            B = PMC_INT_LVL2
            C = PMC_INT_LVL3
            D = PMC_INT_LVL4

            Secondary PCI Bus
            -----------------
            A = PMC_INT_LVL4
            B = PMC_INT_LVL3
            C = PMC_INT_LVL2
            D = PMC_INT_LVL1

.IP "2)"
Define the vector for each PCI interrupt as follows:
INT_VEC_IRQ0 + PMC_INT_LVLx where x is 1, 2, 3, or 4,
as determined above.
.IP "3)"
In the application code, perform intConnect() for
each vector and its associated ISR.
.IP "4)"
Perform IntEnable() for each identified system 
interrupt level.
.IP "5)"
When the application has finished, perform
IntDisable() for each identified level.

.SS "Serial Configuration"
The MVME2600 board family has four serial ports.  All are ISA bus devices.
Two, serial port 1 (COM1 or console) and serial port 2 (COM2),
originate from the PC87308 Super I/O (SIO) chip.  The SIO serial ports are
functional equivalents to those in an Intel 8250 UART.

The other two serial ports, Serial Ports 3 and 4, are implemented in the
Zilog Z85230 ESCC chip and the Zilog Z8536 CIO chip (DTR and DSR lines).  They
can be configured as synchronous serial ports but no support for this mode is
provided by this BSP.

By default, all serial ports are configured as asynchronous, 9600 baud, with
1 start bit, 8 data bits, 1 stop bit, no parity, and no hardware or software
handshake.  Hardware handshake using RTS/CTS is a supported option on all ports.

The four serial ports on MVME712 transition modules all utilize DB-25 female
connectors and are DTE/DCE configurable by jumpers.  For details, consult
\f2MVME712M Transition Module and P2 Adapter Board User's Manual.\f1

The MVME761 transition module has two DB-9 connectors for COM1 and COM2;
these are permanently configured as DCE.  Serial ports 3 and 4 have
special HD-26 connectors and require Serial Interface Modules (SIMs) that come
configured as DCE or DTE versions of EIA-232, EIA-530, X.21 or V.35.  Jumpers
J2 and J3 control DCE/DTE selection for ports 3 and 4, respectively.  Placing
the jumpers over pins 1 and 2 selects DTE configuration.  Jumpering pins 2 and
3 selects DCE.  These jumpers must match the type of SIM installed.
For details, consult \f2MVME761 Transition Module Installation and Use.\f1

.SS "SCSI Configuration"
Only the SCSI-2 bus standard is supported.  The MVME2600 board family
supports an 8-bit SCSI bus using the MVME712 and MVME761-001 transition modules.
It also supports a 16-bit wide SCSI bus if an MVME761-011 transition module
is used and the \f3#undef\f1 of SCSI_WIDE_ENABLE is changed to \f3#define\f1 in
config.h.

The MVME712 module and the attached P2 adapter card have socketed SCSI
terminators that are removed or installed according to the system
configuration.  For details, consult the \f2MVME712M Transition Module and P2
Adapter Board User's Manual.\f1

The MVME761 module has an attached P2 adapter card that uses a jumper to
activate SCSI bus termination.  For details, consult 
\f2MVME761 Transition Module Installation and Use.\f1

.SS "Network Configuration"
All boards have one Ethernet port which is 10baseT and 100baseTX
compatible.  The MVME2600 board family uses transition modules to
connect to this facility.

The MVME712 transition module uses an AUI connector and is not compatible with
100baseTX.  Only MVME2600-1 boards can utilize 100baseTX
communications.  The MVME761 transition module uses an RJ45 (twisted pair)
jack and can be used with either 10baseT or 100baseTX.  The Ethernet driver
automatically senses and configures the port as 10baseT or 100baseTX.  The
Ethernet driver is compatible with both DEC21040 and DEC21140 devices.

The Media Access Control (Ethernet) address for each port is obtained from a
serial ROM contained in the DEC21140 chip.  If the address is not found in
serial ROM, the driver attempts to read it from NVRAM at offset 0x202c.

.SS "VME Access"
A VME access is one in which one VME board obtains VMEbus mastership and 
accesses resources on another VME board.  The VMEbus master board initiates 
the access through a "master window" which resides on the VMEbus master 
board and which translates addresses which originate on the VMEbus master 
board's local bus and go out to the VMEbus.  The VMEbus slave board responds 
to the access through a "slave window" which resides on the VMEbus slave board 
and translates addresses which come in from the VMEbus and go to the 
VMEbus slave's local bus.  A VMEbus slave or master "window" is defined by an 
association between a base address on the VMEbus, the associated base 
address on the local bus, and a window size.  Different windows may be 
defined to facilitate accessing the various VMEbus spaces (A32, A24 etc.).  

The normal VxWorks default is to define shared resources on CPU 0 (master
node) and enable access to these resources via a slave window on the master
node.  In addition, each and every node 
in the system will configure a VME slave
window to allow access to an associated mailbox register.

The default configuration maps all local memory onto VME A32.  There are 
no A24 or A16 slave windows.

There is no support for the A64/D64 VME extensions.

To disable any VME master or slave window, just set the appropriate
VME_Axx_xxx_SIZE macro (in config.h) to 0.  Only the macros in config.h are
considered user options.  Macros in mv2600.h should not be changed by
the user.

There are two addressing models supported: the default Extended VME A32 and one
for the optional pseudo-PReP address model.  For more information on the
pseudo-PReP model, see \f2SPECIAL CONSIDERATIONS.\f1

The following lists the window parameters that the user may change in config.h
for both models:

.CS
    #define VME_A32_MSTR_BUS  0x08000000
    #define VME_A32_MSTR_SIZE 0x08000000  /* (128MB) */
    #define VME_A24_MSTR_BUS  0x00000000
    #define VME_A24_MSTR_SIZE 0x01000000  /* (16MB) */
    #define VME_A16_MSTR_SIZE 0x00010000  /* (64KB) */

    #define VME_A32_SLV_LOCAL LOCAL_MEM_LOCAL_ADRS
    #define VME_A32_SLV_BUS   VME_A32_MSTR_BUS
    #define VME_A32_SLV_SIZE  LOCAL_MEM_SIZE
.CE

The Extended VME A32 Memory Model provides extended mapping to VME A32 space.
The A32 window size can extend to address more than 3.5GB on the VMEbus.

.ne 6
The master window address mappings are as follows:

.TS E
expand;
lf3 lf3 lf3 lf3
lf3 lf3 lf3 lf3
l l l l .
.ne 6
.sp .5
VME Master
Address Space	VME Base Address	Size	Local Base Address
_
A16	0x0000	64KB	0xFBFF0000
A24	0x000000	16MB	0xFA000000
A32	0x10000000	128MB	0x10000000
A32 (Mailbox)	0xFB000000	4KB	0xFB000000
.TE

The slave window address mappings are as follows:

.TS E
expand;
lf3 lf3 lf3 lf3
lf3 lf3 lf3 lf3
l l l l .
.ne 6
.sp .5
VME Slave
Address Space	VME Base Address	Size	Local Base Address
_
A16 (none)
A24 (none)
A32	0x00000000	128MB	0x00000000
A32 (Mailbox)	0xFB000000	4KB	0x00001000 (PCI bus)
.TE

DMA support is implemented as a synchronous "VxWorks driver",
that is, the calling task will be blocked until the DMA transfer has
terminated.  However, the driver itself is a polled driver, and it will
not relinquish the CPU waiting for an interrupt; instead, it will enter
a busy loop periodically sampling the DMA transfer status for termination.
A major intended use of this driver is to transfer TCP/IP packets
(packet size approx. 2K).  In light of its' intended use and to keep this
driver as simple as possible, only direct-mode operations will be
implemented, that is, linked-list mode will not be supported.
	
This driver is strictly non-sharable; however, it contains no guards
to prevent multiple tasks from calling it simultaneously.  It assumes
that the application layer will provide atomic access to this driver
through the use of a semaphore or similar guards.

As a precaution,
it is recommended by the Tundra User's Manual that the calling
task set up a background timer to prevent an infinite wait
caused by a system problem.  Also, tasks transferring large
blocks of data should lower their priority level to allow other
tasks to run, and tasks transferring small blocks of data
should use bcopy() instead of calling this driver.

.SS "PCI Access"
The 32-bit PCI bus is fully supported under the \f2PCI Local Bus Specification,
Revision 2.1.\f1  The 64-bit extensions are not supported.  All configuration
space accesses are made with BDF (bus number, device number, function number)
format calls in the pciConfigLib module.  For more information, refer to the 
reference entries \f2mv260x_pciXxx\f1.

The PCI address mappings are affected by the VME address model selected.
See \f2SPECIAL CONSIDERATIONS.\f1

The Extended VME A32 address model produces the following PCI address mapping:

.TS E
expand;
cf3 s s
lf3 lf3 lf3
l l l .
.ne 6
PCI I/O Space Access
.sp .5
Start	Size	Access to
_
0x00000000	8MB	PCI I/O space
0x00000000	64KB	ISA I/O space
0x00001000	4KB (fixed)	VME mailbox slave space
.TE

.TS E
expand;
cf3 s s
lf3 lf3 lf3
l l l .
.ne 6
PCI MEM Space Access
.sp .5
Start	Size	Access to
_
0x00000000	16MB (min)	DRAM space
0x10000000	~3.7GB (max)	VME A32 master space
  	128MB (std)
0x20000000	16MB (max)	VME A24 master space [1]
0xFB000000	64KB (fixed)	VME mailbox (A32) space
0xFBFF0000	64KB (max)	VME A16 master space
0xFC000000	256KB (fixed)	MPIC REGS
.TE

    NOTE: [1] A24 and A32 address ranges must not overlap.

.SS "Boot Devices"
The supported boot devices are:

    \f3sm\f1 - shared memory
    \f3dc\f1 - Ethernet (10baseT or 100baseTX or AUI)

Motorola's Open Firmware and PPC1-Bug can be used to download and run VxWorks.
Consult the relevant user's manuals for details.

.SS "Boot Methods"
The boot methods are affected by the boot parameters.  If no password is
specified, RSH (remote shell) protocol is used.  If a password is specified,
FTP protocol is used, or, if the flag is set, TFTP protocol is used.

These protocols are used for both Ethernet and shared memory boot devices.

.SS "ROM Considerations"
Use the following command sequence on the host to re-make the BSP boot ROM:
.CS    
    cd target/config/mv260x
    make clean
    make bootrom.bin