target.nr

VxWorkS下 MV2604的BSP源代码

'\" t
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.\" NexGen/target.nr - Motorola NexGen target-specific documentation
.\"
.\" Copyright 2002 Wind River Systems, Inc.
.\" Copyright 1996,1997 Motorola, Inc., All Rights Reserved
.\"
.\" modification history
.\" --------------------
.\" 01y,29apr02,sbs  updating documentation (SPR 62308)
.\" 01x,21mar02,kab  remove ref to elfToBin (obs in T2.2); 
.\"		     add supported target list.
.\" 01w,27aug01,dgp  change manual pages to reference entries per SPR 23698
.\" 01v,07aug98,tb   added support for VMEbus DMA
.\" 01u,08apr98,dat  chg'd pciIomapLib to pciConfigLib,
.\"                  chg'd dec21140 to if_dc.o
.\" 01t,05nov97,mas  added Universe Device Errata to bibliography (SPR 9717).
.\" 01s,31oct97,mas  added more info on Universe VME interrupts (SPR 9438).
.\" 01r,16oct97,mas  added info on using PPC1-Bug 'set' command (SPR 9482).
.\" 01q,10oct97,mas  added known problem with VME int handling (SPR 9438).
.\" 01p,03oct97,mas  updated MPIC int priorities for PCI INTA-D (SPR 9388).
.\" 01o,19sep97,mas  added comments on VME interrupt vector numbers (SPR 9310).
.\" 01n,18sep97,mas  added comments on enabling wide (16-bit) SCSI.
.\" 01m,27aug97,dgp  doc: final editing
.\" 01l,13aug97,mas  split into seperate files for each board family.
.\" 01k,24jul97,mas  added VME interrupt info and guidelines; added MPIC
.\"		     priority scheme (SPR 8956).
.\" 01j,17jul97,mas  added dynamic memory sizing info (SPR 8824).
.\" 01i,09jul97,mas  added serial ports 3 & 4 (SPR 8566) and PPC1-Bug flash ROM 
.\"                  info.  Rewritten to meet new guidelines.
.\" 01h,30apr97,mas  added extended VME, mv360x and mv230x info (SPR 8410).
.\" 01g,02apr97,dat  added VME config info, SPR 8271, fixed model nbr table
.\" 01f,05mar97,mas  changed GET_CPU_SPEED to MEMORY_BUS_SPEED; deleted ref to
.\"		     CPU_SPEED_MHZ; added tftp server required to burn flash
.\"		     (SPR 8114).
.\" 01e,18feb97,mas  clarified use of transition modules and board diagram
.\"                  (SPR 7772, 7811, 7832).
.\" 01d,10jan97,dat  cleaned up flash loading documentation
.\"             mas
.\" 01c,02jan97,wlf  doc: cleanup.
.\" 01b,01jan97,dat  added mod history
.\" 01a,01sep96,mot  written (Motorola Comp. Grp)
.\"
.\"
.TH "mv260x" T "Motorola NexGen" "Rev: 30 Apr 97" "VXWORKS REFERENCE MANUAL"

.SH "NAME"
.aX "Motorola MVME2603, MVME2604"

.SH "INTRODUCTION"
This reference entry provides board-specific information necessary to run
VxWorks.  Before using a board with VxWorks, verify that the board runs in the
factory configuration by using vendor-supplied ROMs and jumper settings and
checking the RS-232 connection.

The Motorola NexGen series of boards consists of three families: MVME230x,
MVME260x, and MVME360x.  This BSP encompasses only the MVME260x family.

The MVME2600 board family consists of single-board computers based on the
PowerPC 603 and 604 microprocessors.  The series part numbers are of the form:

    MVME260p-tcmm

    where
        p   = processor type
            3 = MPC603e
            4 = MPC604ev
        t   = transition module required
            1 = MVME761
            2 = MVME712
        c   = processor clock frequency
            0 = 167MHz
            1 = 200MHz
        mm  = ECC DRAM size
            21 = 16MB
            31 = 32MB
            41 = 64MB
            51 = 128MB
            61 = 256MB
            91 = 96MB

For example, an MVME2604-1131 denotes a PowerPC 604-based board running at
200MHz, having 32MB of ECC DRAM, and requiring an MVME761 transition module.
Standard hardware includes 5MB flash EEPROM (FLASH) and 256KB L2 cache.

The BAT registers are not supported in the current cache management strategy;
therefore, they can best be used for non-cacheable, data-only address regions.

It should be noted that there are two varieties of MVME761 transition module.
The MVME761-001 has a conventional 3-row P2 adapter, whereas the MVME761-011
has a 5-row P2 adapter which requires a 5-row VME backplane.  The 5-row
adapter supports the enhanced P1284 parallel port interface as well as full
synchronous operation on serial ports 3 and 4.

NOTE: The MVME712 module utilizes an AUI Ethernet connector and cannot be used
for 100baseTX communications.

CAUTION: Do not connect an MVME712 module to a board requiring an MVME761 module
or vice versa, as you are likely to damage the boards.

.SS "Boot ROMS"
The MVME2600 boards have two sets of flash EEPROM (FLASH).  One set of two
AMD Am29F040 FLASH is socketed (sockets XU1 and XU2) and contains Motorola's
Open Firmware or, on later revisions, Motorola's PPC1-Bug.  The other set of 
E28f400 FLASH is soldered in.  The VxWorks boot kernel resides in the soldered 
FLASH.  See \f2Hardware Details: ROM Considerations\f1 for information about 
loading and writing the boot kernel image to the soldered FLASH.

These boards have non-volatile RAM; thus, boot parameters are preserved
whenever the system is powered off.

To load VxWorks, and for more information, follow the instructions in the
\f2Tornado User's Guide: Getting Started.\f1

.SS "Jumpers"
The following jumpers are relevant to VxWorks configuration: 

.TS E
expand;
cf3 s s
lf3 lf3 lf3
l l lw(2.6i) .
.ne 6
MVME260x
.sp .5
Jumper	Function	Description
_
J22	System controller	T{
Install the jumper across pins 2 and 3, if you wish to operate in
"automatic" system controller mode (factory configuration).  Install the
jumper across pins 1 and 2, if the board is not to be the system controller
under any circumstances.  And remove the jumper if the board is to be the
system controller in all cases.
T}
J10	ROM controller	T{
Install the jumper across pins 2 and 3 to select the socketed FLASH.
Install the jumper across pins 1 and 2 to select the soldered FLASH
(factory configuration).
T}
J3	Level 2 cache controller	T{
This jumper should always be removed (factory configuration), causing the
L2 cache to operate in write-through mode.
T}
.TE

For details of jumper configuration, see the board diagram at the end of
this entry and in the hardware manual.

Note that ROM controller jumpers should be set to select socketed FLASH until
VxWorks boot code is written to soldered FLASH, after which the jumpers should
be restored to the factory configuration of soldered FLASH.

.SH "FEATURES"
The following subsections list all supported and unsupported features, as well
as any feature interaction.

.SS "Supported Features"
The following features of the MVME2600 board family are supported:

.TS E
expand;
lf3 lf3
lw13 lw(3.7i) .
.ne 6
.sp .5
Feature	Description
_
Processors	T{
MPC603, MPC604; 33 and 66MHz bus clock
T}
L2 Cache	T{
256KB look-aside cache, write-through only
T}
FLASH	T{
4 or 8MB soldered (64-bit wide), 1MB socketed (16-bit wide).
Soldered used for VxWorks boot image.
T}
DRAM	T{
16, 32, 64, 128, 256MB, two-way interleaved; auto-sized or fixed
T}
NVRAM	T{
8KB (MK48T59/559)
8KB
T}
Peripherals	T{
serial ports COM1 and COM2;
two sync/async serial ports;
8/16-bit single-ended fast SCSI-2 interface;
AUI or 10baseT/100baseTX Ethernet interface
T}
ISA Interface	T{
full 64KB memory and I/O space
T}
PCI Interface	T{
32-bit address, 32-bit data; complies with \f2PCI Local Bus Specification\f1,
Revision 2.1
T}
VME Interface	T{
32-bit address, 32-bit data PCI bus interface;
A32/A24/A16, D32/D16/D08 master and slave;
programmable interrupter and interrupt handler;
full system controller function;
two location monitor/signal registers;
Programmable DMA with direct mode support
T}
Miscellaneous	T{
RESET switch
T}
.TE

.SS "Unsupported Features"
The following board features are not supported:

.TS E
expand;
lf3 lf3
lw13 lw(3.7i) .
.ne 6
.sp .5
Feature	Description
_
DRAM	T{
ECC protection
T}
RTC	T{
MK48T59/559; only NVRAM portion is used
T}
Peripherals	T{
PS/2 keyboard port;
PS/2 mouse port;
PS/2 floppy disk port;
IEEE1284/printer parallel port
T}
ISA Interface	T{
ISA RTC and DMA controllers
T}
PCI Interface	T{
64-bit data
T}
VME Interface	T{
D64(MBLT); programmable DMA controller with linked list support
T}
Miscellaneous	T{
ABORT switch, 6 status LEDs
T}
.TE

.SS "Feature Interactions"
None known.

.SH "HARDWARE DETAILS"
This section details device drivers and board hardware elements.

.SS "Devices"
The device drivers and libraries included with this BSP:

.nf
    `i8250Sio' - Intel 8250 UART driver (serial ports 1 and 2)
    `ppcDecTimer' - PowerPC decrementer timer driver (system and timestamp clock)
    `if_dc' - 10baseT/100baseTX DEC 21140 Ethernet driver (primary LAN)
    `byteNvRam' - byte-oriented generic non-volatile RAM driver
    `sl82565IntrCtl' - PIB interrupt controller driver
    `ravenMpic' - Motorola Raven MPIC interrupt controller driver
    `pciConfigLib' - PCI configuration library
    `universe' - Tundra Universe chip VME-to-PCI interface driver
    `z8530Sio' - Zilog Z8530 SCC/Z85230 ESCC driver (serial ports 3 and 4)
    `ppcZ8536Timer' - Zilog Z8536 timer driver (auxiliary clock)
    `ncr810Lib' - NCR 53C825 SCSI controller library
.fi

The `sl82565IntrCtl' module implements the Winbond W83C353 PCI-to-ISA Bridge
(PIB) driver.  The module was developed originally for the Symphonic
Laboratories SL82565 PIB which has been succeeded by the Winbond device.

.SS "Memory Maps"
On-board RAM for these boards always appears at address 0x0 locally.
Its slave address on the VMEbus is set by registers in the Universe ASIC.
Local RAM-to-VMEbus mapping is defined in config.h

Dynamic memory sizing is supported.  By default, LOCAL_MEM_AUTOSIZE is
defined so memory is auto-sized at hardware initialization time.
If auto-sizing is not selected, LOCAL_MEM_SIZE must be set to the actual size
of DRAM memory available on the board to ensure all memory is available
and VME addressing occurs properly.  The default fixed RAM size is set to 16MB
(see LOCAL_MEM_SIZE in config.h).

There are two basic memory mappings. The default for Extended VMEbus access is 
discussed here. The optional pseudo-PReP memory model is discussed under
.I SPECIAL CONSIDERATIONS.

.SS "Extended VME Memory Model:" 1

The following table describes the address mapping created for the Extended VME
A32 model from the CPU point of view:

.TS E
expand;
lf3 lf3 lf3
l l lw(1.8i) .
.ne 6
.sp .5
Start	Size	Access to
_
0x0	LOCAL_MEM_SIZE (16MB min)	DRAM
LOCAL_MEM_SIZE	(0x10000000 - LOCAL_MEM_SIZE)	[not used]
0x10000000	0xEA000000	T{
PCI MEM (max. A32 VME space)
T}
0x10000000	128MB	T{
PCI MEM (default A32 VME space)
T}
0xFA000000	16MB	T{
PCI MEM (A24 VME space)
T}
0xFB000000	64KB	T{
PCI MEM (VME REG. (A32) space)
T}
0xFB010000	0x00FE0000	[not used]
0xFBFF0000	64KB	T{
PCI MEM (A16 VME space)
T}
0xFC000000	256KB	T{
MPIC Reg space
T}
0xFC040000	0x00FC0000	[not used]
0xFD000000	16MB	PCI MEM space
0xFE000000	8MB	PCI I/O space
0xFE800000	0x00780000	[not used]
0xFEF80000	128KB	T{
Falcon/Raven regs.
T}
0xFF000000	16MB	T{
ROM space (No PCI/VME)
T}
.TE

In order to use the optional pseudo-PReP mapping configuration, simply change
the \f3#define\f1 EXTENDED_VME line to read \f3#undef\f1 EXTENDED_VME in
config.h.
Remember to set LOCAL_MEM_SIZE to the actual amount of DRAM on the board if
auto-sizing is not selected.  Failure to do so can cause unpredictable results
for A32 masters and slaves.

In order to modify the Extended VME mapping configuration, make the necessary
changes in config.h and, possibly, sysLib.c.

In config.h, \f3#define\f1 the VME window variables.

In sysLib.c, edit the sysPhysMemDesc[] page table to modify the A32 VME
window if you modify the sysBatDesc[] BAT register table.  The BAT registers
allow mapping of up to 1GB of data address space.  Although the BAT registers
are not supported in the current cache management strategy, you can use them
for non-cacheable, data-only address regions, like the VME A32 address space.

When changing modes -- for example, from standard VxWorks (pseudo-PREP-compliant
mapping) to Extended VME mapping -- all MVME2600 boards should be configured
the same way.  The kernels will not work together in a mixed configuration
unless the memory and VME mappings are compatible for all boards.

.SS "Shared Memory"
On all boards, shared memory across the backplane can also be used as a
network interface.  The name of the shared memory is `sm'.

Shared memory network communications requires a signaling method and a method
of mutually exclusive memory resource access.  Signalling can be done using
software polling or interrupts.  By default, mailbox interrupts are used and
SM_INT_TYPE is set to SM_INT_MAILBOX_1.  To use polling, \f3#define\f1
SM_INT_TYPE as SM_INT_NONE.

There are master and slave windows into VME address space to access the VME
mailbox registers so that each CPU can send and receive shared memory interrupts
using single-byte mailboxes.
The windows map a 4KB region in A32 space at address 0xFB000000 + (0x1000 *
CPU #) into the Universe chip registers.  This configuration allows one
processor to generate a SIG1 interrupt in another processor by accessing the
other processor's mailbox register and setting the SIG1 bit.  Each CPU has a
master window covering the A32 addresses 0xFB000000 through 0xFB00ffff
representing CPU numbers 0 through 15.  Each CPU's slave window maps the
appropriate address for that CPU to the Universe chip's register set.

Shared memory resource mutual exclusion (spin lock) is implemented using
test-and-set (TAS) and clear operations on 32-bit semaphores.
The TAS and clear operations must be atomic operations.
If the \f3#define\f1 SM_TAS_TYPE is set to SM_TAS_SOFT, only a software TAS
routine is used.  Software TAS is usually good enough for shared memory
networking; however, 
if one board uses software TAS, then \f2all\f1 boards on a shared
memory backplane must use it.
VxMP requires the use of hardware TAS.  Enable hardware
TAS by setting SM_TAS_TYPE to SM_TAS_HARD.  Hardware TAS and clear operations
are performed by the sysBusTas() and sysBusTasClear() routines, respectively.

True atomic operations are those which cannot be preempted at the hardware
level and appear on a bus as a single-cycle instruction.  Pseudo-atomic
operations are composed of multiple instruction cycles executed on a
bus that is locked (owned) by the processor executing the instructions.
VMEbus ownership is necessary for two reasons.
First, the Universe I chip has a bug which prevents
proper generation of RMW cycles on the VMEbus.  And second,
boards with the Universe I and early boards with a Universe II have no support
for propagating true atomic VME RMW cycles to local processor memory.
A third kind of atomic operation is the PowerPC atomic access (lwarx/stwcx
sequence) where atomicity is not guaranteed, but the interruption of atomicity
is detected.  Only newer revision boards (rev D or later) can propagate 
a true atomic VME RMW cycle to local processor memory.  

To determine the revision of your board, see "Board Revision Determination"
below.

The type of atomic operation used by a board is defined in tables found in
the headers of sysBusTas() and sysBusTasClear().  Use these tables to assist
in defining the state of the macro ANY_BRDS_IN_CHASSIS_NOT_RMW.

When the sysBusTas() routine performs a true-atomic TAS
operation, it disables interrupts (to prevent deadlocks) 
and performs a VME RMW cycle.
To perform a pseudo-atomic TAS operation,
it disables interrupts (to prevent deadlocks) and 
locks ownership of the VMEbus.
This routine waits up to 10 microseconds to lock the bus.  
If bus ownership has not
been achieved at the end of this period, the routine returns FALSE, the same as
it would if the semaphore had already been set.