syslib.c

VxWorks下 MV2400的BSP源码

/* sysLib.c - Motorola MVME2400 board series system-dependent library */

/* Copyright 1984-2002 Wind River Systems, Inc. */
/* Copyright 1996,1997,1998,1999 Motorola, Inc. All Rights Reserved */

/*
modification history
--------------------
01u,16apr02,dat  Removing warnings for T2.2 release
01t,19nov99,srr  Added error message if VME_A32_MSTR_LOCAL is less than
                 the total DRAM size.
01s,16jul99,rhv  Integrated WRS component-style sysDec21x40End support routines.
                 Moved sysDynEnetFind to sysDec21x40End module and moved network
                 support routines to sysNet.c.
01r,08jul99,rhv  Moving several files to proper location in the WRS file tree.
01q,17jun99,rhv  Incorporated WRS code review changes.
01p,12may99,rhv  Modified to use new WRS PCI symbols. Removed unnecessary
                 dependency between ethernet attach/locating routines and
                 PCI Auto-Configuration. Corrected reference to obsolete
                 PMC Span feature test.
01o,14apr99,rhv  Modified to accomodate MPIC or IBC interrupt controller.
01n,02mar99,rhv  Added auto-config support for Universe and removed Universe I
                 checks.
01m,29jan99,mdp  Added SENS support.
01l,29jan99,rhv  Re-ordered sysHwInit startup sequence to fix a bug in error
                 reporting (bridge wasn't configured yet).
01k,29jan99,rhv  Removed 604 specific code in sysToMonitor.
01j,28jan99,rhv  Changed sysMsgSpit to sysDebugMsg.
01i,27jan99,rhv  Re-formating Bootrom error messages.
01h,27jan99,rhv  Changing name of ROM startup routines to be consistent with
                 WRS naming (Bootrom instead of RomStart) and adding smcShow.c
                 to included files.
01g,24jan99,rhv  Removing sysHawkErrClr (hawkErrClr in hawkPhb.c will be used
                 instead).
01f,22jan99,rhv  Adding ROM startup error reporting.
01e,20jan99,rhv  Moving Hawk setup to hawkPhb.c.
01d,14jan99,dmw  Removed static PCI configuration of LAN and PMC Span if 
                 INCLUDE_PCI_AUTOCONF is defined.
01c,14jan99,dmw  Add pciAutoConfig.
01b,13jan99,rhv  Updated Hawk SMC attribute register symbols, moved sysModel
                 back from sysVpd.c and copyright.
01a,15dec98,mdp  written. (from ver 02h of mv2304 bsp)

*/

/*
DESCRIPTION
This library provides board-specific routines.  The chip drivers included are:

    i8250Sio.c - Intel 8250 UART driver 
    ppcDecTimer.c - PowerPC decrementer timer library (system clock)
    byteNvRam.c - byte-oriented generic non-volatile RAM library
    pciConfigLib.c - PCI configuration library
    universe.c - Tundra Universe chip VME-to-PCI interface library
    HawkAuxClk.c - Hawk timer library (auxiliary clock)

    sl82565IntrCtl.c - interrupt controller driver
         or
    hawkMpic.c - Hawk Mpic / W83C553 PIB/IBC Interrupt Controller

INCLUDE FILES: sysLib.h

SEE ALSO:
.pG "Configuration"
*/

/* includes */

#include "vxWorks.h"
#include "vme.h"
#include "memLib.h"
#include "cacheLib.h"
#include "sysLib.h"
#include "config.h"
#include "string.h"
#include "intLib.h"
#include "esf.h"
#include "excLib.h"
#include "logLib.h"
#include "taskLib.h"
#include "vxLib.h"
#include "tyLib.h"
#include "drv/end/dec21x40End.h"
#include "arch/ppc/archPpc.h"
#include "arch/ppc/mmu603Lib.h"
#include "arch/ppc/vxPpcLib.h"
#include "arch/ppc/excPpcLib.h"
#include "private/vmLibP.h"
#include "drv/pci/pciConfigLib.h"


/* defines */

#define ZERO	0

#define DECREMENTER_PRESCALE	4
#define USECS_PER_SECOND	1000000

#define HAWK_PHB_ADDR( reg ) ( HAWK_PHB_BASE_ADRS + reg )

#ifdef INCLUDE_BPE

#   define HAWK_SMC_ADDR( reg ) ( HAWK_SMC_BASE_ADRS + reg )

#   define _PPC_HID0_DBP _PPC_HID0_ECPC

#endif /* INCLUDE_BPE */

/* globals */

/*
 * sysBatDesc[] is used to initialize the block address translation (BAT)
 * registers within the PowerPC 603/604 MMU.  BAT hits take precedence
 * over Page Table Entry (PTE) hits and are faster.  Overlap of memory
 * coverage by BATs and PTEs is permitted in cases where either the IBATs
 * or the DBATs do not provide the necessary mapping (PTEs apply to both
 * instruction AND data space, without distinction).
 *
 * The primary means of memory control for VxWorks is the MMU PTE support
 * provided by vmLib and cacheLib.  Use of BAT registers will conflict
 * with vmLib support.  User's may use BAT registers for i/o mapping and
 * other purposes but are cautioned that conflicts with cacheing and mapping
 * through vmLib may arise.  Be aware that memory spaces mapped through a BAT
 * are not mapped by a PTE and any vmLib() or cacheLib() operations on such
 * areas will not be effective, nor will they report any error conditions.
 *
 * Note: BAT registers CANNOT be disabled - they are always active.
 * For example, setting them all to zero will yield four identical data
 * and instruction memory spaces starting at local address zero, each 128KB
 * in size, and each set as write-back and cache-enabled.  Hence, the BAT regs
 * MUST be configured carefully.
 *
 * With this in mind, it is recommended that the BAT registers be used
 * to map LARGE memory areas external to the processor if possible.
 * If not possible, map sections of high RAM and/or PROM space where
 * fine grained control of memory access is not needed.  This has the
 * beneficial effects of reducing PTE table size (8 bytes per 4k page)
 * and increasing the speed of access to the largest possible memory space.
 * Use the PTE table only for memory which needs fine grained (4KB pages)
 * control or which is too small to be mapped by the BAT regs.
 *
 * The BAT configuration for 4xx/6xx-based PPC boards is as follows:
 * All BATs point to PROM/FLASH memory so that end customer may configure
 * them as required.
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 */

UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT)] =
    {
    /* I BAT 0 */

    ((ROM_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | (_MMU_UBAT_BL_1M &
    ~(_MMU_UBAT_VS & _MMU_UBAT_VP))),
    ((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT),

    /* I BAT 1 */

    0, 0,

    /* I BAT 2 */

    0, 0,

    /* I BAT 3 */

    0, 0,

    /* D BAT 0 */

    0, 0,

    /* D BAT 1 */

    0, 0,

    /* D BAT 2 */

    0, 0,

    /* D BAT 3 */

    0, 0
    };

/*
 * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array
 * used by the MMU to translate addresses with single page (4k) granularity.
 * PTE memory space should not, in general, overlap BAT memory space but
 * may be allowed if only Data or Instruction access is mapped via BAT.
 *
 * Address translations for local RAM, memory mapped PCI bus, memory mapped
 * VME A16 space and local PROM/FLASH are set here.
 *
 * PTEs are held, strangely enough, in a Page Table.  Page Table sizes are
 * integer powers of two based on amount of memory to be mapped and a
 * minimum size of 64 kbytes.  The MINIMUM recommended Page Table sizes
 * for 32-bit PowerPCs are:
 *
 * Total mapped memory		Page Table size
 * -------------------		---------------
 *        8 Meg			     64 K
 *       16 Meg			    128 K
 *       32 Meg			    256 K
 *       64 Meg			    512 K
 *      128 Meg			      1 Meg
 * 	.				.
 * 	.				.
 * 	.				.
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 *
 * *** EXTENDED_VME configuration ***
 *
 * The user can use TLBs, and/or BATs, to map VME A32 space to the processor.
 * The default is to use TLBs (MMU).  Change the table entry below to use
 * a different method. (See "MODIFY A32 VME WINDOW HERE")
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
    {
    {
    /* Vector Table and Interrupt Stack */

    (void *) LOCAL_MEM_LOCAL_ADRS,
    (void *) LOCAL_MEM_LOCAL_ADRS,
    RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE |
    VM_STATE_MEM_COHERENCY
    },

    {
    /* Local DRAM - Must be second entry in sysPhysMemDesc for Auto Sizing */

    (void *) RAM_LOW_ADRS,
    (void *) RAM_LOW_ADRS,
    LOCAL_MEM_SIZE -  RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE |
    VM_STATE_MEM_COHERENCY
    },

    /* Access to PCI ISA I/O space */

    {
    (void *) ISA_MSTR_IO_LOCAL,
    (void *) ISA_MSTR_IO_LOCAL,
    ISA_MSTR_IO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /* Access to PCI I/O space */

    {
    (void *) PCI_MSTR_IO_LOCAL,
    (void *) PCI_MSTR_IO_LOCAL,
    PCI_MSTR_IO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /*
     * Access to PCI memory space. Note: Guarding should not be required since
     * memory is well-behaved (no side-effects on read or write)
     */

    {
    (void *) PCI_MSTR_MEM_LOCAL,
    (void *) PCI_MSTR_MEM_LOCAL,
    PCI_MSTR_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },

    /* Access to PCI memory I/O space */

    {
    (void *) PCI_MSTR_MEMIO_LOCAL,
    (void *) PCI_MSTR_MEMIO_LOCAL,
    PCI_MSTR_MEMIO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    {
    /* MODIFY A32 VME WINDOW HERE */
    (void *) VME_A32_MSTR_LOCAL,
    (void *) VME_A32_MSTR_LOCAL,
    VME_A32_MSTR_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    {
    (void *) VME_A24_MSTR_LOCAL,
    (void *) VME_A24_MSTR_LOCAL,
    VME_A24_MSTR_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    {
    (void *) VME_A16_MSTR_LOCAL,
    (void *) VME_A16_MSTR_LOCAL,
    VME_A16_MSTR_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    {
    /* Off-board VME LM/SIG/Semaphore Regs */

    (void *) CPU_VME_WINDOW_REG_BASE,
    (void *) CPU_VME_WINDOW_REG_BASE,
    VME_A32_REG_SPACE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    {
    /* MPIC Regs */

    (void *) MPIC_BASE_ADRS,
    (void *) MPIC_BASE_ADRS,
    MPIC_REG_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    {
    (void *) HAWK_SMC_BASE_ADRS,
    (void *) HAWK_SMC_BASE_ADRS,
    HAWK_SMC_REG_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    {
    (void *) HAWK_PHB_BASE_ADRS,
    (void *) HAWK_PHB_BASE_ADRS,
    HAWK_PHB_REG_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    {
    (void *) FLASH_BASE_ADRS,
    (void *) FLASH_BASE_ADRS,
    FLASH_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    }
    };

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);

int    sysBus      = VME_BUS;		/* system bus type */
int    sysCpu      = CPU;		/* system CPU type (MC680x0) */
char * sysBootLine = BOOT_LINE_ADRS;	/* address of boot line */
char * sysExcMsg   = EXC_MSG_ADRS;	/* catastrophic message area */
int    sysProcNum;			/* processor number of this CPU */
int    sysFlags;			/* boot flags */
char   sysBootHost [BOOT_FIELD_LEN];	/* name of host from which we booted */
char   sysBootFile [BOOT_FIELD_LEN];	/* name of file from which we booted */
UINT   sysVectorIRQ0  = INT_VEC_IRQ0;	/* vector for IRQ0 */
BOOL   sysVmeEnable   = FALSE;		/* by default no VME */
static int   hawkPciBusNo;              /* Hawk Config Space BDF address */
static int   hawkPciDevNo;
static int   hawkPciFuncNo;

unsigned char clearWd [1]  = { 0x00 };

#if defined(INCLUDE_PMC_SPAN) && !defined(INCLUDE_PCI_AUTOCONF)
/*
 * PMC Span (DEC21150 PCI-to-PCI Bridge) Configuration Parameter Array
 *
 * This array MUST contain the parameters in the order which they will
 * be set.
 */

PMC_SPAN sysPmcSpanParm [] =
{
  {PCI_CFG_COMMAND, 2,   P2P_PMC_DISABLE},
  {PCI_CFG_STATUS,  2,   P2P_CLR_STATUS >> 16},
  {PCI_CFG_BRIDGE_CONTROL, 2, P2P_SEC_BUS_RESET},
  {PCI_CFG_CACHE_LINE_SIZE, 2, P2P_CACHE_LINE_SIZE | P2P_PRIM_LATENCY},
  {PCI_CFG_PRIMARY_BUS,     1, PCI_PRIMARY_BUS},
  {PCI_CFG_SECONDARY_BUS,   1, PCI_SECONDARY_BUS},
  {PCI_CFG_SUBORDINATE_BUS, 1, PCI_SUBORD_BUS},
  {PCI_CFG_SEC_STATUS, 2,   P2P_CLR_STATUS >> 16},
  {PCI_CFG_IO_BASE, 2,   ((P2P_IO_BASE & 0x0000F000) >> 8) |
                         ((P2P_IO_BASE + P2P_IO_SIZE - 1) & 0x0000F000)},
  {PCI_CFG_MEM_BASE, 2,  ((P2P_NONPREF_MEM_BASE & 0xFFF00000) >> 16)},
  {PCI_CFG_MEM_LIMIT, 2, ((P2P_NONPREF_MEM_BASE + P2P_NONPREF_MEM_SIZE - 1) & \
                          0xFFF00000) >> 16},
  {PCI_CFG_PRE_MEM_BASE, 2, ((P2P_PREF_MEM_BASE & 0xFFF00000) >> 16)},
  {PCI_CFG_PRE_MEM_LIMIT, 2, ((P2P_PREF_MEM_BASE + P2P_PREF_MEM_SIZE - 1) & \
                              0xFFF00000) >> 16},
  {PCI_CFG_PRE_MEM_BASE_U,  4, P2P_PREF_HI32_BASE},  /* only < 4GB space */
  {PCI_CFG_PRE_MEM_LIMIT_U, 4, P2P_PREF_HI32_BASE},
  {PCI_CFG_IO_BASE_U,  2, ((P2P_IO_BASE & 0xFFFF0000) >> 16)},
  {PCI_CFG_IO_LIMIT_U, 2, ((P2P_IO_BASE + P2P_IO_SIZE - 1) & 0xFFFF0000) >> 16},
  {PCI_CFG_BRIDGE_CONTROL, 2, 0},
  {PCI_CFG_DEC21150_SEC_CLK,   2, P2P_CLK_ENABLE},
  {PCI_CFG_DEC21150_SERR_STAT, 1, (P2P_CLR_STATUS >> 16) & 0xFF},
  {PCI_CFG_STATUS,  2,  P2P_CLR_STATUS >> 16},
  {PCI_CFG_COMMAND, 2,  P2P_PMC_ENABLE}
};

#define NUM_PMC_SPAN_PARMS      (sizeof(sysPmcSpanParm) / sizeof(PMC_SPAN))
#endif /* INCLUDE_PMC_SPAN */

/* locals */

LOCAL char sysModelStr[80];
LOCAL char wrongCpuMsg[] = WRONG_CPU_MSG; 

/* forward declarations */

void	sysSpuriousIntHandler (void);
void	sysCpuCheck (void);
char *  sysPhysMemTop (void);
STATUS	sysPciExtHawkInit (int, int, int);
UCHAR	sysNvRead (ULONG);
void	sysNvWrite (ULONG,UCHAR);
void	sysBusTasClear (volatile char *);
#if defined(INCLUDE_PMC_SPAN) && !defined(INCLUDE_PCI_AUTOCONF)
STATUS  sysPmcSpanConfig (int, int, int, PMC_SPAN *);
#endif /* INCLUDE_PMC_SPAN */
STATUS  sysBusProbe (char *, int, int, char *);
IMPORT UINT sysHid1Get (void);
#ifdef ANY_BRDS_IN_CHASSIS_NOT_RMW
    LOCAL BOOL sysVmeVownTas (char *);
#endif
LOCAL	BOOL sysVmeRmwTas (char *);
void	sysConfigBpe (void);
void    reportBootromErrors (void);