rominit.s

VxWorks下 MV2400的BSP源码

 * Software must wait for a refresh to occur after setting the
 * SDRAM Control Registers. To ensure that at least one refresh has
 * completed allow the 32 bit counter to increment at least 100 times.
 */

        addis   r3,r0,0x0000	/* load counter reset value */
        ori     r3,r3,0x0000	/* load counter reset value */
        stw     r3,0x100(r13)	/* reset 32-Bit counter */
        sync
smc_loop2:
        lwz     r3,0x100(r13)   /* Load the counter value */
        cmpwi   r3,100		/* Check counter value less than 100 */
        blt     smc_loop2	/* loop until refresh complete */

        stwu    sp,-40(sp)	    /* create an ABI stack frame */
        addi    r3,sp,8             /* point to register image area */
	or	r14,r3,r3	    /* save register image address */
        bl      sysHawkParamConfig  /* calculate hawk smc parameters */
	or	r18,r3,r3	    /* setup total DRAM size save register */

        lbz     r4,ClkFreq(r14) /* load the Clock Frequency */
        lwz     r5,Ctrl(r14)    /* load the Sdram Speed Attribute */
        lwz     r6,BaseA(r14)   /* load Base Data (Blocks A/B/C/D) */
        lwz     r7,BaseE(r14)   /* load Base Data (Blocks E/F/G/H) */
        lwz     r8,AttrA(r14)   /* load Attributes (Blocks A/B/C/D) */
        lwz     r9,AttrE(r14)   /* load Attributes (Blocks E/F/G/H) */
        addi    sp,sp,40        /* remove ABI stack frame */

/*
 * Software must wait for a refresh to occur prior to setting the
 * SDRAM Control Registers. To ensure that at least one refresh has
 * completed allow the 32 bit counter to increment at least 100 times.
 */

        addis   r3,r0,0x0000	/* load counter reset value */
        ori     r3,r3,0x0000	/* load counter reset value */
        stw     r3,0x100(r13)	/* reset 32-Bit counter */
	sync
smc_loop3:
        lwz     r3,0x100(r13)   /* Load the counter value */
        cmpwi   r3,100		/* Check counter value less than 100 */
        blt     smc_loop3	/* loop until refresh complete */

        addis   r3,r0,0x0000    /* clear the ram enable bits prior to */
        ori     r3,r3,0x0000    /* intializing sdram attributes */
        stw     r3,0x10(r13)    /* SDRAM Attr Register (Blocks A/B/C/D) */
        stw     r3,0xc0(r13)    /* SDRAM Attr Register (Blocks E/F/G/H) */
	eieio
	sync

/*
 * Software must wait for a refresh to occur after setting the
 * SDRAM Control Registers. To ensure that at least one refresh has
 * completed allow the 32 bit counter to increment at least 100 times.
 */

        addis   r3,r0,0x0000	/* load counter reset value */
        ori     r3,r3,0x0000	/* load counter reset value */
        stw     r3,0x100(r13)	/* reset 32-Bit counter */
	sync
smc_loop4:
        lwz     r3,0x100(r13)   /* Load the counter value */
        cmpwi   r3,100		/* Check counter value less than 100 */
        blt     smc_loop4	/* loop until refresh complete */

/*
 * Set the Clock Frequency register and the SDRAM attributes register
 * to the operating values.
 */

        stb     r4,0x20(r13)	/* Clock Frequency register */

        stw     r5,0xd0(r13)    /* SDRAM Speed Attribute Register */

        stw     r6,0x18(r13)    /* SDRAM Base Register (Blocks A/B/C/D) */

        stw     r7,0xc8(r13)    /* SDRAM Base Register (Blocks E/F/G/H) */

        stw     r8,0x10(r13)    /* SDRAM Attr Register (Blocks A/B/C/D) */

        stw     r9,0xc0(r13)    /* SDRAM Attr Register (Blocks E/F/G/H) */
	eieio
	sync

/*
 * Software must wait for a refresh to occur after setting the
 * SDRAM Control Registers. To ensure that at least one refresh has
 * completed allow the 32 bit counter to increment at least 100 times.
 */

        addis   r3,r0,0x0000	/* load counter reset value */
        ori     r3,r3,0x0000	/* load counter reset value */
        stw     r3,0x100(r13)	/* reset 32-Bit counter */
	sync
smc_loop5:
        lwz     r3,0x100(r13)   /* Load the counter value */
        cmpwi   r3,100		/* Check counter value less than 100 */
        blt     smc_loop5	/* loop until refresh complete */

	or	r3,r18,r18      /* restore memory size */

        xor	r0,r0,r0        /* insure r0 is zero */

#ifdef INCLUDE_ECC
/*
 *              The purpose of this section is to enable the ECC of the
 *              DRAM.  To do this, it is first necessary to initialize the
 *              ECC check bits.  The ECC check bits are initialized by
 *              initializing all of DRAM.
 *
 *      input:
 *              r3      = Total DRAM size (in bytes)
 *      notes:
 *              1. must run as a supervisor function
 *              2. interrupts must be masked
 *              3. address translation (MMU) disabled
 *              4. assumes ECC Control register is in a power-up state
 *              5. The scrubber is not enabled (SWEN=0).  This provides
 *                 better performance at the expense of less fault
 *                 tolerance.
 */
.hawk_smc_scrub:

/* setup local variables */

        addi    r15,r0,0                /* load starting addr - always zero */
        or      r16,r3,r3               /* load number of bytes             */
        rlwinm  r16,r16,29,3,31         /* calculate number of doubles      */

/* Make sure FPU is enabled; it's needed for DRAM loads and stores */

        mfmsr   r14                     /* Save current value of MSR in r14 */
        addi    r4,r0,0x2000            /* FP bit definition */
        or      r4,r4,r14
        mtmsr   r4
        isync

/*
 * invalidate/enable the processor data cache, one of the assumptions
 * is that address translation is disabled, the default caching mode
 * is copy-back when address translation is disabled, copy-back mode
 * is the recommended caching mode
 */

        stwu    sp, -64(sp)             /* Create an ABI stack frame */
        bl      dCacheInval
        bl      dCacheOn
        addi    sp,sp,64                /* Remove ABI stack frame */

/*
 * Loop through the entire DRAM array and initialize memory.  This has
 * the side effect of initializing the ECC check bits because they are
 * always updated when the DRAM is written.
 *
 * The data path to DRAM is the size of a cache line (128-bits), this
 * is why the data cache is enabled, the initialization of the ECC check
 * bits are optimized when a cache line write/flush occurs
 */

hawk_smc_scrub_start:
        addi    r17,r15,-8              /* starting address - munged */
        mtspr   9,r16                   /* load number of doubles in counter */
hawk_smc_scrub_iloop:
        lfdu    0,8(r17)
        stfd    0,0(r17)
        bc      16,0,hawk_smc_scrub_iloop /* branch till counter == 0 */

        eieio
        sync
/*
 * Loop through the entire DRAM array again.
 * Looping through the entire DRAM array is not necessary just convenient.
 * What is necessary is flushing the data cache from the previous loop
 * so that the last segment (data cache size) of DRAM is initialized.
 */
        addi    r17,r15,-8              /* starting address - munged */
        mtspr   9,r16                   /* load number of doubles in counter */
hawk_smc_scrub_floop:
        lfdu    0,8(r17)
        bc      16,0,hawk_smc_scrub_floop /* branch till counter == 0 */

        eieio
        sync

/* disable the data cache */

        stwu    sp, -64(sp)             /* Create an ABI stack frame */
        bl      dCacheInval
        bl      dCacheOff
        addi    sp,sp,64                /* Remove ABI stack frame */

/* Restore original value of MSR */

        mtmsr   r14
        isync

/* Clear any possible error conditions that occurred during init */

        lis     r14, HI(HAWK_SMC_BASE_ADRS)
        ori     r14, r14, LO(HAWK_SMC_BASE_ADRS)

        addis   r9,r0,0x8000            /* ELOG=1,ESEN=0,SCOF=1 */
        ori     r9,r9,0x0100
        stw     r9,0x30(r14)            /* Update Error Logger register */
        eieio
        sync

/* Enable ECC and multiple-bit error detection */

        addis   r9,r0,0x0000            /* RWCB=0,DERC=0,xIEN=0,MCKEN=1 */
        ori     r9,r9,0x0001
        stw     r9,0x28(r14)            /* Update ECC Control register */
        eieio
        sync

#endif /* End of ECC Init */

#ifdef EXTENDED_VME
/*
 * Verify that the end of DRAM does not overlap VME_A32_MSTR_LOCAL.
 * If it does, set MSADD0 to the size of DRAM.  A message will be displayed
 * in sysPhysMemTop prompting the user to increase VME_A32_MSTR_LOCAL.
 * 
 * The size of DRAM is saved in r18.
 */
        lis     r3, HI(HAWK_PHB_BASE_ADRS)
        ori     r3, r3, LO(HAWK_PHB_BASE_ADRS)

	lis	r5, HI(VME_A32_MSTR_LOCAL)
	ori	r5, r5, LO(VME_A32_MSTR_LOCAL)

	cmpl	0,0,r18,r5		/* If r18 < VME_A32_MSTR_LOCAL */
	bc	12,0,memMapGood		/* Set MSADD0 to DRAM size */

	ori	r18,r18,CPU2PCI_ADDR0_END	/* MSADD0: */
	stw	r18,HAWK_MPC_MSADD0(r3)	/* write MSADD0 w DRAM size */

	b	doneMSAddr0Calc

memMapGood:
	addis	r4,r0,(VME_A32_MSTR_LOCAL>>16)	/* MSADD0: */
	ori	r4,r4,CPU2PCI_ADDR0_END		/* MSADD0: */
	stw	r4,HAWK_MPC_MSADD0(r3)		/* write MSADD0 */
	
doneMSAddr0Calc:
	eieio					/* synchronize */
	sync					/* synchronize */
#endif

#if	FALSE				/* XXX TPR SDA not supported yet */
        /* initialize r2 and r13 according to EABI standard */

	lis     r2, HI(_SDA2_BASE_)
	ori	r2, r2, LO(_SDA2_BASE_)
	lis     r13, HI(_SDA_BASE_)
	ori	r13, r13, LO(_SDA_BASE_)
#endif

	/* go to C entry point */

	or	r3, r31, r31
	addi	sp, sp, -FRAMEBASESZ	/* get frame stack */

        lis     r6, HI(romStart)
        ori	r6, r6, LO(romStart)

        lis     r7, HI(romInit)
        ori	r7, r7, LO(romInit)

        lis     r8, HI(ROM_TEXT_ADRS)
        ori	r8, r8, LO(ROM_TEXT_ADRS)

	sub	r6, r6, r7
	add	r6, r6, r8 

	mtlr	r6
	blr
		
/******************************************************************************
*
* dCacheOn - Turn Data Cache On
*
* void dCacheOn (void)
*/
_dCacheOn:
dCacheOn:
	/* Get cpu type */

	mfspr	r3,PVR
	rlwinm	r3,r3,16,16,31

        cmpli   0,0,r3,CPU_TYPE_750
        bc	12,2,ccdataon
	bclr	0x14,0x0		/* invalid cpu type */

ccdataon:
	mfspr	r4,HID0		/* Modify HID0 to enable D cache (DCE) */
	ori	r4,r4,_PPC_HID0_DCE
	sync			/* required before changing DCE */
	mtspr	HID0,r4
	bclr	0x14,0x0	/* return to caller */

/******************************************************************************
*
* dCacheOff - Turn Data Cache Off
*
* void dCacheOff (void)
*/
_dCacheOff:
dCacheOff:
	/* Get cpu type */

	mfspr	r3,PVR
	rlwinm	r3,r3,16,16,31

        cmpli   0,0,r3,CPU_TYPE_750
        bc	12,2,ccdataoff
	bclr	0x14,0x0		/* invalid cpu type */

ccdataoff:
	mfspr	r4,HID0		/* Modify HID0 to disable D cache (DCE) */
	rlwinm	r4,r4,0,_PPC_HID0_BIT_DCE+1,_PPC_HID0_BIT_DCE-1	/* clear DCE */
	sync			/* required before changing DCE */
	mtspr	HID0,r4
	bclr	0x14,0x0	/* return to caller */

/******************************************************************************
*
* dCacheInval - Invalidate Data Cache
*
* void dCacheInval (void)
*/
_dCacheInval:
dCacheInval:
	/* Get cpu type */

	mfspr	r3,PVR
	rlwinm	r3,r3,16,16,31

        cmpli   0,0,r3,CPU_TYPE_750
        bc	12,2,ccdatainvl
	bclr	0x14,0x0		/* invalid cpu type */

/*
 * To invalidate the Data Cache on a 750, it's necessary
 * to set the DCFI bit while the Data Cache is enabled (DCE).
 */

ccdatainvl:
	addis	r3,r0,0x0000	/* Setup bit pattern for DCFI + DCE */
	ori	r3,r3,(_PPC_HID0_DCE | _PPC_HID0_DCFI)

	mfspr	r4,HID0		/* Modify HID0 to SET DCFI + DCE bits */
	or	r4,r4,r3
	sync			/* required before changing DCE */
	mtspr	HID0,r4

	andc	r4,r4,r3	/* Modify HID0 to CLEAR DCFI + DCE bits */
	sync			/* required before changing DCE */
	mtspr	HID0,r4
	bclr	0x14,0x0	/* return to caller */

/******************************************************************************
*
* sysHid1Get - read from HID1 register SPR1009.
*
* This routine will read the contents the HID1 (SPR1009)
*
* From a C point of view, the routine is defined as follows:
*
*    UINT sysHid1Get()
*
* RETURNS: value of SPR1009 (in r3)
*/

FUNC_BEGIN(sysHid1Get)
	mfspr r3,HID1
	bclr 20,0
FUNC_END(sysHid1Get)