target.nr

VxWorks下 MV2400的BSP源码

0xFD800000	8MB	PCI MEM
.TE

NOTE: [1] A24 and A32 address ranges must not overlap.

.ne 6

.SS "BSP Configuration"
Most BSP configuration values are taken from on-board Vital Product Data
(VPD) and Serial Presence Detect (SPD) serial EEPROMs. If invalid VPD or SPD
information is suspected or reported, defining NONFATAL_VPD_ERRORS,
BYPASS_VPD_PCO and/or BYPASS_SPD in config.h may permit operation using default
parameters. These defines are intended for use during debug only as they
hard-code non-optimized SDRAM timing and other VPD information. Changing the
state of any of these defines requires the rebuilding the Bootrom image and
re-flashing.

.SS "Bootrom Errors"
Errors encountered during the early stages of the bootrom execution are saved
in the Hawk's general purpose registers as bit flags. Once the system is able to
report these errors, they are logged in the following form:

    Bootrom Error: Group = X, Code = 0xXXXXXXXX


The following errors are defined for this BSP:
.TS E
expand;
lf3 lf3 lf3
c l l .
.ne 4
.sp .5
Group	Bit Pattern	Meaning
_
A	0x80000000	Unable to read bus frequency from VPD.
A	0x40000000	Using default SDRAM Timing.
.TE

NOTE: When multiple errors are present simultaneuously, the error bits are OR'd
together.

.SS "Boot Devices"
The supported boot devices are:

    \f3sm\f1 - shared memory
    \f3dc\f1 - Ethernet (10baseT or 100baseTX)

.SS "Boot Methods"
The boot methods are affected by the boot parameters.  If no password is
specified, RSH (remote shell) protocol is used.  If a password is specified,
FTP protocol is used, or, if the flag is set, TFTP protocol is used.

These protocols are used for both Ethernet and shared memory boot devices.

.SS "ROM Considerations"
Use the following command sequence on the host to re-make the BSP boot ROM:
.CS    
    cd target/config/mv2400
    make clean
    make bootrom_uncmp.bin
    cp bootrom_uncmp.bin /tftpboot/boot.bin
.CE

Power down the board and switch the ROM jumper to select socketed FLASH.
Connect the Ethernet and console serial port cables, then power the board back
up.

.SS "Flashing the Boot ROM Using Motorola PPC4-Bug:" 1
At the PPC4-Bug prompt, start the system clock then set up the network transfer
from a TFTP host using `niot'.  To start the system clock, the \f3set\f1
command must be used.  The format is: set MMDDYYhhmm  where MM is month, DD is
day of month, YY is year, hh is hour (24-hour format), and mm is minutes.  This
command starts the system clock and sets the current date and time.

.CS
   PPC4-Bug>set 1016971302
.CE

Using `niot', the Client IP Address, Server IP Address, and Gateway IP Address
must be set up for the user's specific environment:

.CS
   PPC4-Bug>niot
   Controller LUN =00?
   Device LUN     =00?
   Node Control Memory Address =00FA0000?
   Client IP Address      =123.123.10.100? 123.321.12.123
   Server IP Address      =123.123.18.105? 123.321.21.100
   Subnet IP Address Mask =255.255.255.0?
   Broadcast IP Address   =255.255.255.255?
   Gateway IP Address     =123.123.10.254? 123.321.12.254
   Boot File Name ("NULL" for None)     =? .

   Update Non-Volatile RAM (Y/N)? y
   PPC4-Bug>
.CE

The file is transferred from the TFTP host to the target board using
the `niop' command.  Important: You must have a TFTP server running on your
host's subnet for the `niop' command to succeed.  The file name must be set to
the location of the binary file on the TFTP host.  The binary file must be
stored in the directory identified for TFTP accesses, but the file name is
a relative path and does not include the \f3/tftpboot\f1 directory name:

.CS
   PPC4-Bug>niop
   Controller LUN =00?
   Device LUN     =00?
   Get/Put        =G?
   File Name      =? boot.bin
   Memory Address =00004000?
   Length         =00000000?
   Byte Offset    =00000000?

   PPC4-Bug>
.CE

After the file is loaded onto the target, the `pflash' command is used
to put it into soldered FLASH parts.

.CS
   PPC4-Bug>pflash 4000:fff00 ff000100
.CE

When the command is finished, power down the board and switch the ROM
jumper to select soldered FLASH.  Then power the board back up.

.SH "SPECIAL CONSIDERATIONS"
This section describes miscellaneous information concerning this BSP and its
use.

.SS "Delivered Objects"
The delivered objects are: `bootrom.hex', `vxWorks', `vxWorks.sym', and
`vxWorks.st'.

.SS "Make Targets"
The make targets are listed as the names of object-format files.  Append `.hex'
to each to derive a hex-format file name.

.nf
`bootrom'
`bootrom_uncmp'
`bootrom_res_high'  (`bootrom_res' does not build)
`vxWorks' (with `vxWorks.sym')
`vxWorks_rom'
`vxWorks.st'
`vxWorks.st_rom'
`vxWorks.res_rom_res_low' (`vxWorks.res_rom' does not build)
`vxWorks.res_rom_nosym_res_low' (`vxWorks.res_rom_nosym' does not build)
.fi

.SS "Special Routines"
For these boards, the value of the CPU clock speed is read from the VPD 
information using the macro MEMORY_BUS_SPEED which is defined
in mv2400.h.  For example:

.CS
   clkFreqMhz = MEMORY_BUS_SPEED;
.CE

.SS "VME Interrupt Vectors"
Interrupt vectors chosen to generate normal VME interrupts under program
control must be even numbers.  VME interrupt service routines (ISRs) servicing
VME interrupts received by the Universe chip need only be able to service
even vector numbers.

The Universe chip used on this board can be configured to generate VME bus
interrupts in response to DMA status, PCI bus conditions, and by specific
command from software.  During the VME interrupt acknowledge (IACK) cycle,
the STATUS/ID register of the Universe chip transmits an 8-bit interrupt
vector to the VME bus.  The seven most significant bits are the vector number
(hence the need for even vector numbers) and the least significant bit (LSB) is
set according to how the Universe is configured to respond to the IACK cycle.
If the interrupt was generated by software and the IACK cycle is received, the
Universe can be configured to send an acknowledging interrupt (SW_IACK)
back to the software over the PCI bus.  If the SW_IACK interrupt is enabled,
the LSB is set to 0, otherwise, it is set to 1.

The Universe chip can also be configured to receive VME interrupts.  However,
the Universe is designed to mask out the least significant bit of the vector
number returned by the interrupting device.  Therefore, the ISR servicing
the VME interrupt only receives the seven most significant bits of the
vector number from the Universe chip receiving the interrupt.

Note that, if software specifies an odd number as the interrupt vector to be
transmitted during the IACK cycle, the STATUS/ID register will truncate it to
an even number.  Also, if any interrupting VME device sends an odd vector
number, the vector number returned by the Universe to an ISR is truncated to
an even vector number.  There is no configuration option to compensate for this
feature of the Universe chip.

.SS "Known Problems"
Older generation VME backplanes often do not have slot 1 (the system controller
slot) hard-wired for interrupt acknowledge (IACK) daisy chain operation,
leaving this to be done by a board plugged in to the slot.  New VME backplanes
usually have the left-most slot P1 connector hard-wired so that pin A20 (IACK)
is connected to A21 (IACKIN).  On old VME backplanes, the user must add a
jumper between pins A20 and A21 on the wire wrap pins behind the P1 connector
of slot 1.

.SS "Pseudo-PReP Memory Model"
The following table describes the modified PowerPC Reference Platform (PReP)
address maps created for VME from the CPU point of view.  Tornado-compatible
mapping deviates only slightly from the model.

.TS E
expand;
lf3 lf3 lf3
l l lw(2.5i) .
.ne 6
.sp .5
Start	Size	Access to
_
0x0	LOCAL_MEM_SIZE	DRAM
	(32MB - 256MB)

LOCAL_MEM_SIZE	T{
(0x80000000 - LOCAL_MEM_SIZE)
T}	[Not used]

0x80000000	16KB	Legacy ISA I/O space
0x80001000	4KB	T{
On-board VME mailbox acess (inside ISA Legacy I/O space)
T}
0x80004000	48KB	T{
16-bit PCI I/O space
T}
0x80010000	8MB	T{
32-bit PCI I/O space
T}
0x80810000	0x3F7F0000	[Not Used]
0xC0000000	8MB	T{
PCI MEM I/O space
T}
0xC0800000	16MB	T{
32-bit PCI MEM space
T}
0xC1800000	0x16800000	[Not Used]
0xD8000000	128MB (max)	T{
PCI MEM (A32 VME space)
T}
0xE0000000	16MB	T{
PCI MEM (A24 VME space)
T}
0xE1000000	0x0EFF0000	[Not used]
0xEFFF0000	64KB	T{
PCI MEM (A16 VME space)
T}
0xF0000000	64KB	T{
PCI MEM (VME REG. [A32] space)
T}
0xF0010000	0x0BFF0000	[Not used]
0xFC000000	256KB	MPIC Reg space
0xFC040000	0x02F40000	[Not used]
0xFEF80000	128KB	Hawk's regs.
0xFEFA0000	0x00060000	[Not used]
0xFF000000	16MB	T{
ROM space (No PCI/VME)
T}
.TE

.SS "VME Access in the Pseudo-PReP Memory Model" 1

The pseudo-PReP memory model does not offer much address space for mapping
VME master windows.  Only 128MB of A32 space is available.  The 128MB window
can be mapped anywhere in VME A32 space by setting the macro VME_A32_MSTR_BUS
in config.h.  The full A16 and A24 master window address spaces are mapped into
the system.

The master window address mappings are as follows:

.TS E
expand;
cf3 s s s
lf3 lf3 lf3 lf3
l l l l .
.ne 6
.sp .5
VME Master
Address Space	VME Base Address	Size	Local Base Address
_
A16	0x0000	64KB	0xEFFF0000
A24	0x000000	16MB	0xE0000000
A32	0x08000000	128MB	0xD8000000
A32 (Mailbox)	0x40000000	4KB	0xF0000000
.TE

The slave window address mappings are as follows:

.TS E
expand;
cf3 s s s
lf3 lf3 lf3 lf3
l l l l .
.ne 6
.sp .5
VME Slave
Address Space	VME Base Address	Size	Local Base Address
_
A16 (none)
A24 (none)
A32	0x00000000	128MB	0x00000000
A32 (Mailbox)	0x40000000	4KB	0x00001000 (PCI I/O space)
.TE

.SS "PCI Access in the Pseudo-PReP Memory Model" 1

The default pseudo-PReP mapping from the PCI bus point of view is:

.TS E
expand;
cf3 s s
lf3 lf3 lf3
l l l .
.ne 6
PCI I/O Space Access
.sp .5
Start	Size	Access to
_
0x00000000	16KB	ISA Legacy I/O space
0x00001000	4KB (fixed)	T{
VME mailbox slave space (inside ISA Legacy space)
T}
0x00004000	48KB	16-bit PCI I/O
0x00010000	8MB	32-bit PCI I/O space
.TE

.TS E
expand;
cf3 s s
lf3 lf3 lf3
l l l .
.ne 6
PCI MEM Space Access
.sp .5
Start	Size	Access to
_
0x00000000	8MB	PCI MEM I/O
0x00800000	16MB	PCI MEM
0x18000000	16MB (std)	VME A32 master space
0x20000000	16MB (max)	VME A24 master space
0x2FFF0000	64KB (max)	VME A16 master space
0x30000000	64KB (fixed)	VME mailbox (A32) master space
0x3C000000	256KB (fixed)	MPIC REGS
0x80000000	LOCAL_MEM_SIZE	DRAM space (32MB - 256MB)
.TE

.SH "BOARD LAYOUT"
The diagram below shows flash EEPROM locations and jumpers relevant to VxWorks
configuration:

For the MVME24xx boards, the debug and 10baseT/100baseTX ports appear on the
front panel.

.ne 4i

.bS
______________________________               ______________________________
|             P1             |    MVME24xx   |             P2              |
|                            ----------------                              |
|                             Does not use a                               |
|                            Transition Module                             |
|                                                                          |
|                                                                          |
|                        +----+  +----+                                    |
|                        |    |  |    |                                    |
|                        |    |  |    |                                    |
|                        +----+  +----+ <== PPC4-Bug Firmware              |
|                         XU2     XU1                                      |
|                                                                          |
|                                                                          |
|                                                                          |
|                                                        8-Position  +--+  |
|                                                         Software   |  |  |
|                                                         Readable   |  |  |
|                                                          Header    +--+  |
|                                                                          |
|                                                                          |
|                                                     J7  (SCON)   --> L   |
|                                                     J8  (ROM ctrl) --> D |
|                                                                          |
|                                                                          |
|     Debug   10/100BaseT      PMC 2                   PMC 1               |
|_____-----____-----___.......................__......................_____|
.bE
    Key: 
    X  vertical jumper installed
    :  vertical jumper absent
    -  horizontal jumper installed
    "  horizontal jumper absent
    0  switch off
    1  switch on
    U  three-pin vertical jumper, upper jumper installed
    D  three-pin vertical jumper, lower jumper installed
    L  three-pin horizontal jumper, left jumper installed
    R  three-pin horizontal jumper, right jumper installed

.SH "SEE ALSO"
.tG "Getting Started,"
.pG "Configuration"

.SH "BIBLIOGRAPHY"
.iB "Motorola MVME24xx Series Single Board Computer Programmer's Reference Guide,"
.iB "Motorola PowerPC 750 RISC Microprocessor User's Manual,"
.iB "Motorola PowerPC Microprocessor Family: The Programming Environments,"
.iB "DECchip 21143 PCI Fast Ethernet LAN Controller Hardware Reference Manual,"
.iB "SGS-Thompson MK48T59/559 CMOS 8K x 8 TIMEKEEPER SRAM Data Sheet,"
.iB "Winbond W83C553 Enhanced System I/O Controller with PCI Arbiter Data Book,"
.iB "Tundra Universe User Manual,"
.iB "Tundra Universe Device Errata,"
.iB "ANSI/VITA 1-1994 VME64 Specification,"
.iB "ANSI/IEEE 1014-1987 Versatile Backplane Bus: VMEbus,"
.iB "IEEE P1386 Draft 2.0 - Common Mezzanine Card Specification (CMC),"
.iB "IEEE P1386.1 Draft 2.0 - PCI Mezzanine Card Specification (PMC),"
.iB "IEEE Standard 1284 Bidirectional Parallel Port Interface Specification,"
.iB "Peripheral Component Interconnect (PCI) Local Bus Specification, Rev 2.1,"
.iB "PCI to PCI Bridge Architecture Specification 2.0,"
.iB "ANSI X3.131.1990 Small Computer System Interface-2 (SCSI-2) Draft Document"