target.nr

VxWorks下 MV2400的BSP源码

routine also disables interrupts and locks the VMEbus while accessing the
semaphore.  It waits up to 10 microseconds to gain bus ownership.  But, even if
the bus is not owned after this period, the routine attempts to clear the
semaphore.

If one board uses software TAS, then \f2all\f1 boards on a shared
memory backplane must use it.

When hardware TAS is enabled, special consideration must be given to the
overall system design and board locations in the VME card rack.  If all VME
boards on a backplane use the special hardware TAS methods utilized in this BSP,
there should be no problems.  If boards with differing TAS/RMW capabilities are
used together, then either the first (master) board, which hosts the shared
memory, must use the hardware TAS method utilized in this BSP, or the shared
memory must reside on a separate VME global memory board.

As an example of a hardware TAS system that cannot work, consider using a
Motorola MVME162 as the master board and an MVME2400 as a slave.  The mv162
BSP assumes that support exists for atomic TAS/RMW cycles on to and off of
all boards in the system.  Furthermore, the local 68040 CPU can access and 
alter its memory \f2between\f1 VMEbus cycles.  Therefore, this system
configuration does not work because there is no way to ensure atomic access
to a semaphore by the MVME2400 board.

.SS "Interrupts"
The system interrupt vector table has 256 entries.  Vectors for the various
devices on the buses are assigned hierarchically as follows:

.TS C
center;
lf3 lf3
l lw(2.6i) .
.ne 6
.sp .5
Vector#	Assigned to
_
00 - 0f	ISA IRQ numbers 0 - 15
10 - 1f	All MPIC interrupts
20 - 23	Hawk timers
24 - 27	Hawk interprocessor dispatch
   28  	Hawk detected internal errors
29 - 55	[User defined]
56 - 5f	Universe-specific interrupts
60 - ff	[User defined]
.TE

The specific ISA vector number assignments are:

.TS C
center;
lf3 lf3
l lw(2.6i) .
.ne 6
.sp .5
Vector#	Assigned to
_
   02	[Cascade interrupt from PIC2]
   04	Debug serial port
.TE

Vector numbers not in the table are not used by this BSP.

The standard ISA Intel 8259 Programmable Interrupt Controllers (PICs) assert
their interrupts through the HawkMPIC as an external interrupt.  The external
interrupt vector numbers are:

.TS C
center;
lf3 lf3
l lw(2.6i) .
.ne 14
.sp .5
Vector#	Assigned to
_
   10	ISA PICs
   12	PCI Ethernet
   15	PCI Universe VME INT 0
   16	PCI Universe VME INT 1
   17	PCI Universe VME INT 2
   18	PCI Universe VME INT 3
   19	PCI PMC1/PCIX INTA, PMC2 INTB
   1a	PCI PMC1/PCIX INTB, PMC2 INTC
   1b	PCI PMC1/PCIX INTC, PMC2 INTD
   1c	PCI PMC1/PCIX INTD, PMC2 INTA
   1d	LM/SIG (mailbox) 0
   1e	LM/SIG (mailbox) 1
.TE

Vector numbers not in the table are not used by this BSP.

The Hawk Multi-Processor Interrupt Controller (MPIC) sets system interrupt
priorities and serves as controller of all external interrupts.  Each
of its 16 interrupt control registers, designated IRQ0 through IRQ15, can be
programmed with a relative priority from 15, the highest, to 0, the lowest.  A
priority of zero effectively disables the interrupt.  All but one of the 16
control registers has been hardwired to a particular interrupt source.  The IRQ
number and priority assignments are as follows:

.TS E
expand;
lf3 lf3 lf3
l l lw(2.6i) .
.ne 6
.sp .5
Hawk MPIC IRQ	Priority	IRQ Source
_
IRQ0	8	Winbond PIB [all ISA interrupts]
IRQ1	N/A	[Not Used]
IRQ2	14	Ethernet
IRQ3	N/A	[Not Used]
IRQ4	N/A	[Not Used]
IRQ5	10	Universe LINT0 [all Universe/VME interrupts]
IRQ6	0	Universe LINT1
IRQ7	0	Universe LINT2
IRQ8	0	Universe LINT3
IRQ9	7	PCI PMC1/PCIX INTA, PMC2 INTB
IRQ10	6	PCI PMC1/PICX INTB, PMC2 INTC
IRQ11	5	PCI PMC1/PICX INTC, PMC2 INTD
IRQ12	4	PCI PMC1/PICX INTD, PMC2 INTA
IRQ13	0	LM/SIG Interrupt 0
IRQ14	15	LM/SIG Interrupt 1 (mailbox)
IRQ15	N/A	[Not used]
.TE

For further details, refer to the appropriate board's reference guide.

There are only four PCI bus interrupts: A, B, C, and D.  They are shared among
all PCI bus devices and do not have levels.  PCI bus interrupts are wired
directly to the MPIC and, therefore, have pre-assigned system vector numbers
and interrupt levels.  The user enables one or more PCI interrupts and connects
vectored ISRs to the system by following these steps:

.IP "1)"
Identify the PCI interrupt letter(s) as required by the  application. Based on 
this, identify the associated system interrupt level from the following tables:

            Primary PCI Bus
            ----------------
            A = PMC_INT_LVL1
            B = PMC_INT_LVL2
            C = PMC_INT_LVL3
            D = PMC_INT_LVL4

            Secondary PCI Bus
            -----------------
            A = PMC_INT_LVL4
            B = PMC_INT_LVL3
            C = PMC_INT_LVL2
            D = PMC_INT_LVL1

.IP "2)"
Define the vector for each PCI interrupt as follows:
INT_VEC_IRQ0 + PMC_INT_LVLx where x is 1, 2, 3, or 4, as determined above.
.IP "3)"
In the application code, perform intConnect() for
each vector and its associated ISR.
.IP "4)"
Perform sysIntEnable() for each identified system interrupt level.
.IP "5)"
When the application has finished, perform sysIntDisable() for each identified 
level.

.SS "PCI Auto-Configuration"
To simplify the addition of PCI-based add-in cards, the BSP provides a PCI
auto-configuration library. When INCLUDE_AUTOCONF is defined, the BSP will
automatically locate and configure installed PCI devices. When
INCLUDE_AUTOCONF is not defined, add-in PCI devices will not be located or
configured.

If PCI auto-configuration is selected, the auto-cofiguration library will be
called from sysHwInit to discover and configure the installed PCI devices and
bridges. Device configuration includes the following PCI information:

.IP "Base Address Registers (BARs)"
Space in the address map is dynamically allocated to each valid BAR detected.
Allocation pools are maintained for the following PCI address spaces:


16-Bit PCI I/O
.br
32-Bit PCI I/O
.br
PCI Memory I/O (non-prefetchable memory)
.br
PCI Memory (pre-fetchable)

.IP "Interrupt Routing"
The correct interrupt vector number is placed in the intLine register of the
device's PCI header. To connect to the devices's interrupt, simply call
intConnect with the value read from intLine.

.IP "PCI Header Completion"
The PCI auto-configuration library fills in the remainder of the PCI header as
follows:

Cache Line Size  = _CACHE_ALIGN_SIZE/4
.br
Latency Timer    = PCI_LAT_TIMER
.br
Command Register = I/O enabled, Memory enabled and Bus Master enabled.

.IP "PCI-to-PCI Bridge Configuration"
PCI-to-PCI bridges encountered during PCI auto-configuration will be configured
as necessary and devices detected behind the bridge will be configured as
described above. Bridge configuration consists of the following:

Primary Bus Number, Secondary Bus Number and Subordinate Bus Number are
filled in according to the bridge's position in the system.
.sp
I/O Base and Limit registers are configured as required to forward PCI
transactions to PCI devices detected and configured beyond the bridge.
.sp
Memory Base and Memory Limit registers are configured as required to forward
PCI transactions to PCI devices detected and configured beyond the bridge.
.sp
Command Register = I/O enabled, Memory enabled and Bus Master enabled.
.sp
Cache Line Size         = _CACHE_ALIGN_SIZE/4
.br
Primary Latency Timer   = PCI_LAT_TIMER
.br
Secondary Latency Timer = PCI_LAT_TIMER
.sp
NOTE: Due to a descrepancy in the PCI Auto-Configuration code, pre-fetchable
memory requests below a PCI-to-PCI bridge are not currently honored. The address
space requested by a fre-fetachable Base Address Register will be allocated from
the non-prefetchable pool.

.SS "Serial Configuration"
The single debug port on the MVME24xx board family is implemented in a
TLC16550 UART.  It is an ISA bus device.  The RJ-45 jack is placed on the front
panel of the board and is configured as a DTE connection.

By default, the serial port is configured as asynchronous, 9600 baud, with
1 start bit, 8 data bits, 1 stop bit, no parity, and no hardware or software
handshake.  Hardware handshake using RTS/CTS is a supported option.

.SS "SCSI Configuration"
SCSI is not available on the MVME24xx board family.

.SS "Network Configuration"
All boards have one Ethernet port which is 10baseT and 100baseTX compatible.
The MVME24xx boards have an RJ45 jack on their front panel for connection
to this facility.

The Ethernet driver automatically senses and configures the port as 10baseT or
100baseTX.  The Ethernet driver is compatible with both DEC2104x and DEC2114x
devices (for the 24xx family, a DEC21143 chip is used).

The Media Access Control (Ethernet) address for each port is obtained from a
serial ROM contained in the DEC21143 chip.  If the address is not found in
serial ROM, the driver attempts to read it from NVRAM.

.SS "VME Access"
VMEbus accesses can be classified as either master or slave.  A master access
is one in which the accessing processor has bus mastership (it owns the bus)
and is addressing resources on another VME board (the slave board).  The
master addresses the off-board resources through a memory mapping mechanism
which assigns portions of the local address space to the various VME address
spaces.  These local memory regions are windows onto the VMEbus.  Each
window is individually configured with a set of base addresses -- one for the
local bus, the other for the VMEbus -- and a window size.

A slave access is one in which slave VME processors allow access to
their resources from the various VME address spaces through slave windows.

The normal VxWorks default is to enable the slave access windows only on
CPU 0, as part of the routine sysProcNumSet().  Otherwise, slave accesses
are normally not permitted.

The default configuration maps all local memory onto VME A32.  There are no A24
or A16 slave windows.

There is no support for the A64/D64 VME extensions.

To disable any VME master or slave window, just set the appropriate
VME_Axx_xxx_SIZE macro (in config.h) to 0.  Only the macros in config.h are
considered user options.  Macros in mv2400.h should not be changed by
the user.

There are two addressing models supported: the default Extended VME A32 
and one for the optional pseudo-PReP address model.  For more information 
on the pseudo-PReP model, see 
.I SPECIAL CONSIDERATIONS.

The following lists the window parameters that the user may change in config.h
for both models:

.CS
    #define VME_A32_MSTR_BUS  0x08000000
    #define VME_A32_MSTR_SIZE 0x08000000  /* (128MB) */
    #define VME_A24_MSTR_BUS  0x00000000
    #define VME_A24_MSTR_SIZE 0x01000000  /* (16MB) */
    #define VME_A16_MSTR_SIZE 0x00010000  /* (64KB) */

    #define VME_A32_SLV_LOCAL LOCAL_MEM_LOCAL_ADRS
    #define VME_A32_SLV_BUS   VME_A32_MSTR_BUS
    #define VME_A32_SLV_SIZE  LOCAL_MEM_SIZE
.CE

The Extended VME A32 Memory Model provides extended mapping to VME A32 space.
The A32 window size can extend to address more than 3.5GB on the VMEbus.

.ne 10
The master window address mappings are as follows:

.TS E
expand;
cf3 s s s
lf3 lf3 lf3 lf3
l l l l .
.ne 6
.sp .5
VME Master
Address Space	VME Base Address	Size	Local Base Address
_
A16	0x0000	64KB	0xFBFF0000
A24	0x000000	16MB	0xFA000000
A32	VME_A32_MSTR_LOCAL	128MB	VME_A32_MSTR_LOCAL
A32 (Mailbox)	0xFB000000	4KB	0xFB000000
.TE

The slave window address mappings are as follows:

.TS E
expand;
cf3 s s s
lf3 lf3 lf3 lf3
l l l l .
.ne 6
.sp .5
VME Slave 
Address Space	VME Base Address	Size	Local Base Address
_
A16 (none)
A24 (none)
A32	0x00000000	128MB	0x00000000
A32 (Mailbox)	0xFB000000	4KB	T{
0x00001000
.br
(PCI I/O Space)
T}
.TE

DMA support is implemented as a synchronous "VxWorks driver",
that is, the calling task will be blocked until the DMA transfer has
terminated.  However, the driver itself is a polled driver, and it will
not relinquish the CPU waiting for an interrupt; instead, it will enter
a busy loop periodically sampling the DMA transfer status for termination.
A major intended use of this driver is to transfer TCP/IP packets
(packet size approx. 2K).  In light of its' intended use and to keep this
driver as simple as possible, only direct-mode operations will be
implemented, that is, linked-list mode will not be supported.

This driver is strictly non-sharable; however, it contains no guards
to prevent multiple tasks from calling it simultaneously.  It assumes
that the application layer will provide atomic access to this driver
through the use of a semaphore or similar guards.

As a precaution,
it is recommended by the Tundra User's Manual that the calling
task set up a background timer to prevent an infinite wait
caused by a system problem.  Also, tasks transferring large
blocks of data should lower their priority level to allow other
tasks to run, and tasks transferring small blocks of data
should use bcopy() instead of calling this driver.

.SS "PCI Access"
The 32-bit PCI bus is fully supported under the 
.I PCI Local Bus Specification, Revision 2.1. 
The 64-bit extensions are not supported.  All configuration space accesses 
are made with BDF (bus number, device number, function number) format calls in
the pciConfigLib module.  For more information, refer to the reference entries 
.I mv24xx_pciXxx.

The PCI address mappings are affected by the VME address model selected.  See 
.I SPECIAL CONSIDERATIONS.

The Extended VME A32 address model produces the following PCI address mapping:

.TS E
expand;
cf3 s s
lf3 lf3 lf3
l l l .
.ne 6
PCI I/O Space Access
.sp .5
Start	Size	Access to
_
0x00000000	16KB	ISA Legacy I/O space
0x00001000	4KB (fixed)	T{
On-board VME mailbox (inside ISA Legacy space)
T}
0x00004000	48KB	16-bit PCI I/O
0x00010000	8MB	32-bit PCI I/O space
.TE

.TS E
expand;
cf3 s s
lf3 lf3 lf3
l l l .
.ne 6
PCI MEM Space Access
.sp .5
Start	Size	Access to
_
0x00000000	LOCAL_MEM_SIZE	DRAM space
	(32MB - 512MB)

VME_A32_MSTR_LOCAL	~3.7GB (max)	VME A32 master space
	128MB (std)


0xFA000000	16MB (max)	VME A24 master space [1]
0xFB000000	64KB (fixed)	VME mailbox (A32) space
0xFBFF0000	64KB (max)	VME A16 master space
0xFC000000	256KB (fixed)	MPIC REGS
0xFD000000	8MB	PCI MEM I/O