target.nr

VxWorks下 MV2400的BSP源码

'\" t
.so wrs.an
.\" PowerPlusII/target.nr - Motorola PowerPlusII target-specific documentation
.\"
.\" Copyright 1984-2002 Wind River Systems, Inc.
.\" Copyright 1996,1997,1998,1999 Motorola, Inc. All Rights Reserved
.\"
.\" modification history
.\" --------------------
.\" 01a,16apr02,dat  Update for T2.2, Removed ref to booting via PPCBug (30625)
.\" 01n,21mar02,kab  remove ref to elfToBin (obs in T2.2); 
.\"		     add supported target list.
.\" 01m,27aug01,dgp  change manual pages to reference entries per SPR 23698
.\" 01l,22nov99,srr  Extended VME memory map uses VME_A32_MSTR_LOCAL now.
.\" 01k,01jul99,rhv  Incorporating WRS code review changes.
.\" 01j,19may99,rhv  Added 256MB option and additional updates.
.\" 01i,12may99,rhv  Updated address maps.
.\" 01h,03may99,rhv  Added warning about pre-fetchable memory below bridges.
.\" 01g,14apr99,rhv  Added writeup about PCI Auto-Configuration.
.\" 01f,05feb99,mdp  Cleaned up 2300 refs, SENS info, and DRAM info.
.\" 01f,05feb99,mdp  Added writeup on SENS support.
.\" 01e,28jan99,rhv  Adding a warning to re-flash after changing the state of
.\"                  TOLERATE_CONFIG_ERRORS.
.\" 01d,28jan99,dmw  Added more detailed memory map descriptions.
.\" 01c,27jan99,rhv  Added Bootrom error descriptions.
.\" 01b,14jan99,rhv  Added more 2400 info, removed references to 2300 and
.\"                  updated the copyright.
.\" 01a,15dec98,mdp  Written (from version 01u of mv2304/target.nr).
.\"
.\"
.TH "mv24xx" T "Motorola PowerPlusII" "Rev: 19 May 99" "VXWORKS REFERENCE MANUAL"

.SH "NAME"
.aX "Motorola MVME24xx"

.SH "INTRODUCTION"
This reference entry provides board-specific information necessary to run
VxWorks.  Before using a board with VxWorks, verify that the board runs in the
factory configuration by using vendor-supplied ROMs and jumper settings and
checking the RS-232 connection.

This BSP encompasses only the MVME2400 single-board computer. All MVME2400
boards require no transition module.  The series part numbers are of the form:

    MVME24xy-z

    where
        x = CPU Speed
           0 = 233Mhz 750
           3 = 350MHz 750

        y = ECC SDRAM size
           1 =  32 MB
           2 =  64 MB
           3 = 128 MB
           4 = 256 MB

        z = Front panel
           1 = Scanbe
           3 = IEEE 1101

For example, an MVME2431-3 denotes a 350 MHz PowerPC 750-based board having
32MB of ECC SDRAM with an IEEE 1101 front panel. Note that not all product
combinations are available. Standard equipment includes 9MB FLASH.

The BAT registers are not supported in the current cache management strategy.

.SS "Boot ROMS"
The MVME2400 boards have two sets of flash EEPROM (FLASH).  One set of two
AMD Am29F040 FLASH is socketed (sockets XU1 and XU2) and contains Motorola's
PPC4-Bug.  The other set of E28f400 FLASH is soldered in on the back of the
boards.  The VxWorks boot kernel resides in the soldered FLASH. See
\f2Hardware Details: ROM Considerations\f1 for information about loading and
writing the boot kernel image to the soldered FLASH.

These boards have non-volatile RAM; thus, boot parameters are preserved
whenever the system is powered off.

To load VxWorks, and for more information, follow the instructions in the
\f2Tornado User's Guide: Getting Started.\f1

.SS "Jumpers"
The following jumpers are relevant to VxWorks configuration: 

.TS E
expand;
lf3 lf3 lf3
l l lw(2.6i) .
.ne 28
.sp .5
Jumper	Function	Description
_
J9	System controller	T{
Install the jumper across pins 2 and 3, if you wish to operate in
"automatic" system controller mode [factory configuration].  Install the
jumper across pins 1 and 2, if the board is not to be the system controller
under any circumstances.  And remove the jumper if the board is to be the
system controller in all cases.
T}
J8	ROM controller	T{
Install the jumper across pins 2 and 3 to select the socketed FLASH.
Install the jumper across pins 1 and 2 to select the soldered FLASH
[factory configuration].
T}
.TE

For details of jumper configuration, see the board diagram at the end of
this entry and in the hardware manual.

Note that ROM controller jumpers should be set to select socketed FLASH until
VxWorks boot code is written to soldered FLASH, after which the jumpers should
be restored to the factory configuration of soldered FLASH.

.SH "FEATURES"
The following subsections list all supported and unsupported features, as well
as any feature interaction.

.SS "Supported Features"
The following features of the MVME24xx board family are supported:

.TS E
expand;
lf3 lf3
lw13 lw(3.7i) .
.ne 7
.sp .5
Feature	Description
_
Processors	T{
MPC750; 100MHz bus clock
T}
FLASH	T{
1MB socketed (16-bit wide)
8MB soldered (32-bit wide)
T}
DRAM	T{
32, 64, 128MB SDRAM, two-way interleaved; auto-sized or fixed
T}
NVRAM	T{
8KB (MK48T59/559)
T}
Peripherals	T{
one async serial debug port
10baseT/100baseTX Ethernet interface
T}
ISA Interface	T{
full 64KB memory and I/O space
T}
PCI Interface	T{
32-bit address, 32-bit data; complies with \f2PCI Local Bus Specification\f1,
Revision 2.1
T}
VME Interface	T{
32-bit address, 32-bit data PCI bus interface;
A32/A24/A16, D32/D16/D08 master and slave;
programmable interrupter and interrupt handler;
full system controller function;
two location monitor/signal registers;
DMA controller (in direct mode only).
T}
Miscellaneous	T{
RESET switch
8-Bit Software Readable Header
T}
.TE

.SS "Unsupported Features"
The following features of the MVME24xx board family are not supported:

.TS E
expand;
lf3 lf3
lw13 lw(3.7i) .
.ne 6
.sp .5
Feature	Description
_
Hawk	T{
Watchdog Timers
T}
RTC	T{
MK48T59/559; only NVRAM portion is used
T}
ISA Interface	T{
ISA RTC and DMA controllers
T}
PCI Interface	T{
64-bit data; The hardware will perform 64-bit transfers if requested by an
external PCI-master device, but does not generate 64-bit transactions in
normal operation.
T}
VME Interface	T{
D64(MBLT); DMA controller in linked list mode (only direct mode is supported).
T}
Miscellaneous	T{
ABORT switch, 4 status LEDs
T}
.TE

.SS "Feature Interactions"
None known.

.SH "HARDWARE DETAILS"
This section details device drivers and board hardware elements.

.SS "Devices"
The device drivers and libraries included with this BSP are:

.nf
    `i8250Sio' - Intel 8250 UART driver (debug port)
    `ppcDecTimer' - PowerPC decrementer timer driver (system clock)
    `dec21x4x[End].obj' - 10baseT/100baseTX DEC 21x4x Ethernet driver
    `byteNvRam' - byte-oriented generic non-volatile RAM driver
    `sl82565IntrCtl' - PIB interrupt controller driver
    `hawkAuxClk' - Motorola Hawk auxiliary clock library.
    `hawkI2c' - Motorola Hawk I2C serial EEPROM driver.
    `hawkMpic' - Motorola Hawk MPIC interrupt controller driver
    `pciConfigLib' - PCI configuration library
    `pciAutoConfigLib' - PCI auto-configuration library
    `universe' - Tundra Universe chip VME-to-PCI interface driver
    `sysVpd' - Board-Specific Vital Product Data library
    `vpdUtil' - "Generic" Vital Product Data library
.fi

The `sl82565IntrCtl' module implements the Winbond W83C353 PCI-to-ISA Bridge
(PIB) driver.  The module was developed originally for the Symphonic
Laboratories SL82565 PIB which has been succeeded by the Winbond device.

.SS "SENS support"
This BSP supports SENS (Scalable Enhanced Network Stack).  To build
a SENS kernel and bootrom make sure you have installed the following
in the order presented:

.IP "1)"
Wind River's Tornado 1.0.1.
.IP "2)"
The Motorola MVME2400 BSP.
.IP "3)"
Wind River's SENS support.
.LP
The unmodified BSP builds without SENS support. To configure
the BSP to contain SENS support, make the following adjustments
in the "mv2400" subdirectory and rebuild:

.IP "1)"
In "Makefile" comment out the MACH_EXTRA line which contains "dec21x4x.obj"
and uncomment the MACH_EXTRA line which contains "dec21x4xEnd.obj".

.IP "2)"
In "config.h" change "#undef INCLUDE_END" to "#define INCLUDE_END"

.IP "3)"
From the "mv2400" subdirectory perform:
.CS
  cp ./sens/* .
.CE

.IP "4)"
Rebuild the bootroms and kernel.

.SS "Memory Maps"
On-board RAM for these boards always appears at address 0x0 locally.
Its slave address on the VMEbus is set by registers in the Universe ASIC.
Local RAM-to-VMEbus mapping is defined in config.h

Dynamic memory sizing is supported.  By default, LOCAL_MEM_AUTOSIZE is
defined so memory is auto-sized at hardware initialization time.
If auto-sizing is not selected, LOCAL_MEM_SIZE must be set to the actual size
of DRAM memory available on the board to ensure all memory is available
and VME addressing occurs properly.  The default fixed RAM size is set to 32MB
(see LOCAL_MEM_SIZE in config.h).

There are two basic memory mappings. The default for Extended VMEbus access
is discussed here. Another for the optional pseudo-PReP memory model is
disucssed under 
.I SPECIAL CONSIDERATIONS.

.SS "Extended VME Memory Model:" 1

The following table describes the address mapping created for the Extended VME
A32 model from the CPU point of view:

.TS E
expand;
lf3 lf3 lf3
l l lw(2.5i) .
.ne 6
.sp .5
Start	Size	Access to
_
0x0	LOCAL_MEM_SIZE	SDRAM
	(32MB - 512MB)

LOCAL_MEM_SIZE	T{
(VME_A32_MSTR_LOCAL - LOCAL_MEM_SIZE)
T}	[not used]

VME_A32_MSTR_LOCAL	128MB	T{
PCI MEM (A32 VME space)
T}
	0xEA000000 (max)

0xFA000000	16MB	T{
PCI MEM (A24 VME space)
T}
0xFB000000	64KB	T{
PCI MEM (VME REG. [A32] space)
T}
0xFB010000	0x00FE0000	[not used]
0xFBFF0000	64KB	T{
PCI MEM (A16 VME space)
T}
0xFC000000	256KB	T{
MPIC Reg space
T}
0xFC040000	0x00FC0000	[not used]
0xFD000000	8 MB	T{
PCI MEM I/O space
T}
0xFD800000	8 MB	T{
PCI MEM space
T}
0xFE000000	16KB	Legacy ISA I/O space
0xFE001000	4KB	T{
On-board VME Mailbox (inside ISA Legacy I/O space)
T}
0xFE004000	48KB	T{
16-bit PCI I/O space
T}
0xFE010000	8MB	T{
32-bit PCI I/O space
T}
0xFE810000	0x00770000	[not used]
0xFEF80000	128KB	T{
Hawk regs.
T}
0xFF000000	16MB	T{
ROM space (No PCI/VME)
T}
.TE

Note that the macro VME_A32_MSTR_LOCAL determines the base address for
PCI VME A32 addresses.  This value is 0x10000000 (256MB) by default and needs
to be adjusted by the user if there is more than 256MB of local DRAM in 
config.h.



In order to use the optional pseudo-PReP mapping configuration, simply change
the \f3#define\f1 EXTENDED_VME line to read \f3#undef\f1 EXTENDED_VME in
config.h.
Remember to set LOCAL_MEM_SIZE to the actual amount of DRAM on the board if
auto-sizing is not selected.  Failure to do so can cause unpredictable results
for A32 masters and slaves.

In order to modify the Extended VME mapping configuration, make the necessary
changes in config.h and, possibly, sysLib.c.

In config.h, \f3#define\f1 the VME window variables.

In sysLib.c, edit the sysPhysMemDesc[] page table to modify the A32 VME
window if you modify the sysBatDesc[] BAT register table.  The BAT registers
allow mapping of up to 1GB of data address space.  Although the BAT registers
are not supported in the current cache management strategy, you can use them
for non-cacheable, data-only address regions, like the VME A32 address space.

When changing modes -- for example, from standard VxWorks (pseudo-PREP-compliant
mapping) to Extended VME mapping -- all MVME24xx boards should be configured
the same way.  The kernels will not work together in a mixed configuration
unless the memory and VME mappings are compatible for all boards.

.SS "Shared Memory"
On all boards, shared memory across the backplane can also be used as a
network interface.  The name of the shared memory is `sm'.

Shared memory network communications requires a signaling method and a method
of mutually exclusive memory resource access.  Signalling can be done using
software polling or interrupts.  By default, mailbox interrupts are used and
SM_INT_TYPE is set to SM_INT_MAILBOX_1.  To use polling, \f3#define\f1
SM_INT_TYPE as SM_INT_NONE.

There are master and slave windows into VME address space to access the VME
mailbox registers so that each CPU can send and receive shared memory interrupts
using single-byte mailboxes.
The windows map a 4KB region in A32 space at address 0xFB000000 + (0x1000 *
CPU #) into the Universe chip registers.  This configuration allows one
processor to generate a SIG1 interrupt in another processor by accessing the
other processor's mailbox register and setting the SIG1 bit.  Each CPU has a
master window covering the A32 addresses 0xFB000000 through 0xFB00ffff
representing CPU numbers 0 through 15.  Each CPU's slave window maps the
appropriate address for that CPU to the Universe chip's register set.

Shared memory resource mutual exclusion (spin lock) is implemented using
test-and-set (TAS) and clear operations on byte-sized semaphores.
If the \f3#define\f1 SM_TAS_TYPE is set to SM_TAS_SOFT, only a software TAS
routine is used.  Software TAS is usually good enough for shared memory
networking; however, VxMP requires the use of hardware TAS.  Enable hardware
TAS by setting SM_TAS_TYPE to SM_TAS_HARD.  Hardware TAS and clear operations
are performed by the sysBusTas() and sysBusTasClear() routines, respectively,
and invoke pseudo-atomic operations.

True atomic operations are those which cannot be preempted at the hardware
level and appear on a bus as a single-cycle instruction.  Pseudo-atomic
operations are composed of multiple instruction cycles executed on a
bus that is locked (owned) by the processor executing the instructions.

The routine sysBusTas() performs pseudo-atomic TAS operations by disabling
interrupts (to prevent deadlocks) and locking ownership of the VMEbus.  This
routine waits up to 10 microseconds to lock the bus.  If bus ownership has not
been achieved at the end of this period, the routine returns FALSE, the same as
it would if the semaphore had already been set.

VMEbus ownership is necessary for a number of reasons.  First, there is no
hardware support to propagate PowerPC atomic TAS instructions to the
Universe chip.  Second, the Universe chip (rev 1.0) has a bug which prevents
proper generation of read-modify-write (RMW) cycles on the VMEbus.  Third,
these boards have no support for propagating true atomic VME RMW cycles to
local processor memory.

To ensure proper clearing of the semaphore, use the sysBusTasClear().  This