mv2400.h

VxWorks下 MV2400的BSP源码

/*
 *                      MAP FOR STANDARD vxWorks 
 * This maps: VME RANGE:     (0x40000000 + (0x1000 * ProcNum)) -
 *                           (0x40000fff + (0x1000 * ProcNum))
 *        to: PCI RANGE:     0x00001000 - 0x00001fff - ISA I/O Space
 */
#define VAL_VSI0_TO_VALUE	(0xc0001000 - (sysProcNumGet() * \
                                               VME_A32_REG_SIZE))
#else
/*
 *                      MAP FOR EXTENDED VME vxWorks
 * This maps: VME RANGE:     (0xfb000000 + (0x1000 * ProcNum)) -
 *                           (0xfb000fff + (0x1000 * ProcNum))
 *        to: PCI RANGE:     0x00001000 - 0x00001fff
 */
#define VAL_VSI0_TO_VALUE	(0x05001000 - (sysProcNumGet() * \
                                               VME_A32_REG_SIZE))
#endif

#define VAL_VSI0_BS	(VME_A32_REG_BASE + (sysProcNumGet() * \
                                             VME_A32_REG_SIZE))
#define VAL_VSI0_BD	(VME_A32_REG_BASE + ((sysProcNumGet() + 1) * \
                                             VME_A32_REG_SIZE))
#define VAL_VSI0_TO	(VAL_VSI0_TO_VALUE)
#define VAL_VSI0_CTL	(VSI_CTL_EN       | \
                         VSI_CTL_AM_DATA  | VSI_CTL_AM_PGM  |\
                         VSI_CTL_AM_SUPER | VSI_CTL_AM_USER |\
                         VSI_CTL_VAS_A32  | VSI_CTL_LAS_IO )

/*
 * VME SLAVE WINDOW FOR A32 SPACE
 *
 * Universe VME slave window 1
 *
 * VME bus A32 window to access the master node's local memory.
 * This VME Slave window is only used by the master node.
 *
 *
 *                      MAP FOR STANDARD vxWorks 
 * This maps: VME RANGE:     0x08000000 - (0x08000000 + VME_A32_SLV_SIZE - 1)
 *        to: PCI RANGE:     0x80000000 - 0x80000000 + VME_A32_SLV_SIZE-1
 *        to: MPU RANGE:     0x00000000 - VME_A32_SLV_SIZE-1
 *
 *
 *                      MAP FOR EXTENDED VME vxWorks
 * This maps: VME RANGE:     0x08000000 - (0x08000000 + VME_A32_SLV_SIZE - 1)
 *        to: PCI RANGE:     0x00000000 - VME_A32_SLV_SIZE-1
 *        to: MPU RANGE:     0x00000000 - VME_A32_SLV_SIZE-1
 */

#define VAL_VSI1_BS	(VME_A32_SLV_BUS)

#if	(SM_OFF_BOARD == TRUE)
#  define VAL_VSI1_BD	(VAL_VSI1_BS + VME_A32_SLV_SIZE)
#else
#ifdef	ANY_BRDS_IN_CHASSIS_NOT_RMW
#  define VAL_VSI1_BD	(VAL_VSI1_BS + VME_A32_SLV_SIZE)
#else
#  define VAL_VSI1_BD     (VAL_VSI1_BS + SM_MEM_ADRS)
#endif	/* ANY_BRDS_IN_CHASSIS_NOT_RMW */
#endif	/* SM_OFF_BOARD */

#define VAL_VSI1_TO	(PCI_SLV_MEM_BUS - VAL_VSI1_BS + VME_A32_SLV_LOCAL)
#define VAL_VSI1_CTL	( VSI_CTL_EN       | VSI_CTL_PREN    | \
			  VSI_CTL_AM_DATA  | VSI_CTL_AM_PGM  | \
			  VSI_CTL_AM_SUPER | VSI_CTL_AM_USER | \
			  VSI_CTL_VAS_A32  | VSI_CTL_LAS_MEM | \
			  VSI_CTL_LD64EN )

/*  VSI4 and VSI5 are only applicable to the Universe II */

#define VAL_VSI4_BS	(VAL_VSI1_BS + \
			 SM_MEM_ADRS)
#define VAL_VSI4_BD	(VAL_VSI1_BS + \
			 SM_MEM_ADRS + \
			 SM_MEM_SIZE + \
			 SM_OBJ_MEM_SIZE)
#define VAL_VSI4_TO	(PCI_SLV_MEM_BUS - VAL_VSI1_BS + VME_A32_SLV_LOCAL)
#define VAL_VSI4_CTL	( VSI_CTL_EN       | VSI_CTL_PREN    | \
			  VSI_CTL_AM_DATA  | VSI_CTL_AM_PGM  | \
			  VSI_CTL_AM_SUPER | VSI_CTL_AM_USER | \
			  VSI_CTL_VAS_A32  | VSI_CTL_LAS_MEM | \
			  VSI_CTL_LD64EN   | VSI_CTL_PWEN    | \
			  VSI_CTL_LLRMW )

#define VAL_VSI5_BS	(VAL_VSI1_BS + \
			 SM_MEM_ADRS + \
			 SM_MEM_SIZE + \
			 SM_OBJ_MEM_SIZE)
#define VAL_VSI5_BD	(VAL_VSI1_BS + VME_A32_SLV_SIZE)
#define VAL_VSI5_TO	(PCI_SLV_MEM_BUS - VAL_VSI1_BS + VME_A32_SLV_LOCAL)
#define VAL_VSI5_CTL	( VSI_CTL_EN       | VSI_CTL_PREN    | \
			  VSI_CTL_AM_DATA  | VSI_CTL_AM_PGM  | \
			  VSI_CTL_AM_SUPER | VSI_CTL_AM_USER | \
			  VSI_CTL_VAS_A32  | VSI_CTL_LAS_MEM | \
			  VSI_CTL_LD64EN   | VSI_CTL_PWEN    )

/*
 * VME SLAVE WINDOW FOR A24 SPACE
 *
 * Universe VME A24 Slave window, does not exist.  (Could use window 2.)
 */

#define VME_A24_SLV_BUS         0x0
#define VME_A24_SLV_SIZE        0x0	/* 0, window is disabled */
#define VME_A24_SLV_LOCAL       0x0

/*
 * VME SLAVE WINDOW FOR A16 SPACE
 *
 * Universe VME A16 Slave window, does not exist.  (Could use window 3.)
 */

#define VME_A16_SLV_BUS		0x0
#define VME_A16_SLV_SIZE	0x0	/* 0, window is disabled */
#define VME_A16_SLV_LOCAL	0x0


/* VME Registers as seen from CPU */

#define CPU_VME_HW_REGS_BASE	( ISA_MSTR_IO_LOCAL + 0x1000 )
#define CPU_SIG_LM_CONTROL_REG	( ISA_MSTR_IO_LOCAL + 0x1000 )
#define CPU_SIG_LM_STATUS_REG	( ISA_MSTR_IO_LOCAL + 0x1001 )
#define CPU_VME_LM_UBA		( ISA_MSTR_IO_LOCAL + 0x1002 )
#define CPU_VME_LM_LBA		( ISA_MSTR_IO_LOCAL + 0x1003 )
#define CPU_VME_SEM_REG1	( ISA_MSTR_IO_LOCAL + 0x1004 )
#define CPU_VME_SEM_REG2	( ISA_MSTR_IO_LOCAL + 0x1005 )
#define CPU_VME_GEOG_STAT	( ISA_MSTR_IO_LOCAL + 0x1006 )
#define CPU_VME_HW_REGS_SZ	7

/* Universe Special Cycle Generator values */

#define	VME_SCG_COMPARE_MASK		0xffffffff
#define VME_SCG_COMPARE_TO_SET		0x00000000
#define VME_SCG_SWAP_TO_SET		0x80000000
#define VME_SCG_COMPARE_TO_CLEAR	0x80000000
#define VME_SCG_SWAP_TO_CLEAR		0x00000000

/* INTERRUPT DEFINES */

#define ISA_INTERRUPT_BASE	0x00
#define EXT_INTERRUPT_BASE	0x10
#define TIMER_INTERRUPT_BASE	0x20
#define IPI_INTERRUPT_BASE	0x24
#define ERR_INTERRUPT_BASE	0x28
#define	ESCC_INTERRUPT_BASE	0x00

/* interrupt Level definitions */

#ifdef INCLUDE_MPIC

/* PIB (8259) interrupt connection */

#define PIB_INT_LVL		( 0x00 + EXT_INTERRUPT_BASE )
 
/* ISA interrupt defines (NOTE: these are int. NUMBERS, not levels) */
 
/* programable timer interrup level */
#define PIT_INT_LVL		( 0x00 + ISA_INTERRUPT_BASE )

/* keyboard interrupt level ( currently not supported ) */
#define KBD_INT_LVL		( 0x01 + ISA_INTERRUPT_BASE )

/* com port 2 interrupt level */
#define COM2_INT_LVL		( 0x03 + ISA_INTERRUPT_BASE )

/* com port 1 interrupt level */
#define COM1_INT_LVL		( 0x04 + ISA_INTERRUPT_BASE )

/* floppy interrupt */
#define FD_INT_LVL		( 0x06 + ISA_INTERRUPT_BASE )

/* parallel port interrupt level */
#define PP_INT_LVL		( 0x07 + ISA_INTERRUPT_BASE )

/* z8536 timer interrupt level */
#define Z8536_INT_LVL		( 0x09 + ISA_INTERRUPT_BASE )

/* z85230 ESCC interrupt level (shared with z8536) */
#define Z85230_INT_LVL		( 0x09 + ISA_INTERRUPT_BASE )

/* mouse interrupt ( currently not supported ) */
#define MOUSE_INT_LVL		( 0x0c + ISA_INTERRUPT_BASE )
 
/* Timer interrupt level (IPI0) */
#define TIMER0_INT_LVL          ( 0x00 + TIMER_INTERRUPT_BASE )

/* PCI interrupt levels */
 
/* Hawk SMC ECC error interrupt */
#define ECC_INT_LVL		( 0x01 + EXT_INTERRUPT_BASE )

/* ethernet interrupt level */
#define LN_INT_LVL		( 0x02 + EXT_INTERRUPT_BASE )

/* SCSI interrupt level */
#define SCSI_INT_LVL		( 0x03 + EXT_INTERRUPT_BASE )

/* Graphics interrupt level ( not currently used ) */
#define GRPH_INT_LVL		( 0x04 + EXT_INTERRUPT_BASE )

/* Universe LINT#0 interrupt level ( used for the UNIVERSE chip )*/
#define UNIV_INT_LVL0		( 0x05 + EXT_INTERRUPT_BASE )

/* Universe LINT#1 interrupt level */
#define UNIV_LINT_LVL1		( 0x06 + EXT_INTERRUPT_BASE )

/* Universe LINT#2 interrupt level */
#define UNIV_INT_LVL2		( 0x07 + EXT_INTERRUPT_BASE )

/* Universe LINT#3 interrupt level */
#define UNIV_INT_LVL3		( 0x08 + EXT_INTERRUPT_BASE )

/* PMC1 INTA#, PMC2 INTD# */
#define PMC_INT_LVL1		( 0x09 + EXT_INTERRUPT_BASE )

/* PMC1 INTB#, PMC2 INTC# */
#define PMC_INT_LVL2		( 0x0a + EXT_INTERRUPT_BASE )

/* PMC1 INTC#, PMC2 INTB# */
#define PMC_INT_LVL3		( 0x0b + EXT_INTERRUPT_BASE )

/* PMC1 INTD#, PMC2 INTA# */
#define PMC_INT_LVL4		( 0x0c + EXT_INTERRUPT_BASE )

/* Location Monitor/SIG interrupt 0 */
#define LM_SIG_INT_LVL0		( 0x0d + EXT_INTERRUPT_BASE )

/* Location Monitor/SIG interrupt 1 ( used for the mailbox intr. ) */
#define LM_SIG_INT_LVL1		( 0x0e + EXT_INTERRUPT_BASE )
 
#define LM_SIG_INT_LVL		LM_SIG_INT_LVL1   /* used for mailbox intr */
#define UNIV_INT_LVL		UNIV_INT_LVL0   /* universe int level */

#else

#define PIT_INT_LVL	0x00	/* programable timer interrup level */
#define KBD_INT_LVL	0x01	/* keyboard interrupt level */
#define COM2_INT_LVL	0x03	/* com port 2 interrupt level */
#define COM1_INT_LVL	0x04	/* com port 1 interrupt level */
#define LM_SIG_INT_LVL	0x05	/* used for mailbox intr */
#define FD_INT_LVL	0x06    /* floppy disk interrupt level */
#define PP_INT_LVL	0x07	/* parallel port interrupt level */
#define Z8536_INT_LVL	0x09	/* z8536 timer interrupt level */
#define Z85230_INT_LVL	0x09	/* z85230 ESCC interrupt level */
#define LN_INT_LVL	0x0a	/* ethernet interrupt level */
#define UNIV_INT_LVL	0x0b	/* universe int level */
#define SCSI_INT_LVL	0x0e	/* scsi interrupt level */
#define PMC_INT_LVL1	0x0a	/* PCI INTA */
#define PMC_INT_LVL2	0x0b	/* PCI INTB */
#define PMC_INT_LVL3	0x0e	/* PCI INTC */
#define PMC_INT_LVL4	0x0f	/* PCI INTD */

#endif /* INCLUDE_MPIC */

/* interrupt vector definitions */

#define INT_VEC_IRQ0		0x00	/* vector for IRQ0 */

/* ISA interrupt vectors */

#define PIT_INT_VEC		INT_VEC_IRQ0 + PIT_INT_LVL
#define KBD_INT_VEC		INT_VEC_IRQ0 + KBD_INT_LVL
#define PP_INT_VEC		INT_VEC_IRQ0 + PP_INT_LVL
#define COM1_INT_VEC            INT_VEC_IRQ0 + COM1_INT_LVL
#define COM2_INT_VEC            INT_VEC_IRQ0 + COM2_INT_LVL
#define Z8536_INT_VEC		INT_VEC_IRQ0 + Z8536_INT_LVL
#define Z85230_INT_VEC		INT_VEC_IRQ0 + Z85230_INT_LVL
#define FD_INT_VEC		INT_VEC_IRQ0 + FD_INT_LVL

/* PCI/MPIC interrupt vectors */

#define LN_INT_VEC		INT_VEC_IRQ0 + LN_INT_LVL
#define SCSI_INT_VEC		INT_VEC_IRQ0 + SCSI_INT_LVL
#define UNIV_INT_VEC		INT_VEC_IRQ0 + UNIV_INT_LVL
#define LN2_INT_VEC             INT_VEC_IRQ0 + PMC_INT_LVL2
#define SCSI_INT_VEC2           INT_VEC_IRQ0 + PMC_INT_LVL3
#define PIB_INT_VEC		INT_VEC_IRQ0 + PIB_INT_LVL
#define	PCI_PRI_INTA_VEC	INT_VEC_IRQ0 + PMC_INT_LVL1
#define	PCI_PRI_INTB_VEC	INT_VEC_IRQ0 + PMC_INT_LVL2
#define	PCI_PRI_INTC_VEC	INT_VEC_IRQ0 + PMC_INT_LVL3
#define	PCI_PRI_INTD_VEC	INT_VEC_IRQ0 + PMC_INT_LVL4

/* Timer interrupt vectors */

#define TIMER0_INT_VEC          ( INT_VEC_IRQ0 + TIMER0_INT_LVL )

/* UNIVERSE chip interrupt vector defines */

#define UNIV_DMA_INT_VEC	0x56
#define UNIV_VME_SW_IACK_INT_VEC 0x57
#define UNIV_PCI_SW_INT_VEC	0x58
#define UNIV_VOWN_INT_VEC	0x59
#define UNIV_LERR_INT_VEC	0x5a
#define UNIV_VERR_INT_VEC	0x5c
#define UNIV_SYSFAIL_INT_VEC	0x5d
#define UNIV_ACFAIL_INT_VEC	0x5f

/*
 * Address range definitions for VME and PCI buses.
 *
 * Used with vxMemProbe() hook sysBusProbe().
 */

#define IS_VME_ADDRESS(adrs) (((UINT32)(adrs) >= (UINT32)VME_MSTR_LO_ADRS) && \
((UINT32)(adrs) < (UINT32)VME_MSTR_HI_ADRS))

#define IS_PCI_ADDRESS(adrs) (((UINT32)(adrs) >= (UINT32)PCI_MSTR_LO_ADRS) && \
((UINT32)(adrs) < (UINT32)PCI_MSTR_HI_ADRS))

/* VME Interrupt Bit definitions */

#define SIG1_INTR_SET		0x80
#define SIG0_INTR_SET		0x40
#define LM1_INTR_SET		0x20
#define LM0_INTR_SET		0x10
#define SIG1_INTR_CLEAR		0x08
#define SIG0_INTR_CLEAR		0x04
#define LM1_INTR_CLEAR		0x02
#define LM0_INTR_CLEAR		0x01

#define SIG1_INTR_ENABL		0x80
#define SIG0_INTR_ENABL		0x40
#define LM1_INTR_ENABL		0x20
#define LM0_INTR_ENABL		0x10
#define SIG1_INTR_STATUS	0x08
#define SIG0_INTR_STATUS	0x04
#define LM1_INTR_STATUS		0x02
#define LM0_INTR_STATUS		0x01

#define MV2400_SIOP_HW_REGS    {0,0,0,0,0,1,0,0,0,0,0}

/* PCI bus number for primary PCI bus */

#define PCI_PRIMARY_BUS         0

/* Fixed PMC Span (PCI-to-PCI Bridge) configuration parameters */

#define P2P_CLR_STATUS          0xFFFF0000
#define P2P_SEC_BUS_RESET       (0x0040 << 16)
#define P2P_CLK_ENABLE          0x00       /* enable clocks on all slots */
#define P2P_PMC_DISABLE         0
#define P2P_PMC_ENABLE          7

#ifndef _ASMLANGUAGE

/* PMC Span (DEC21150 PCI-to-PCI Bridge) Configuration Parameter Structure */

typedef struct pmc_span_parm	/* PMC_SPAN */
    {
    UINT16  parmOffset;		/* offset into configuration header */
    UINT16  parmSize;		/* parmValue size (1, 2 or 4 bytes) */
    UINT32  parmValue;		/* parameter value placed at this offset */
    } PMC_SPAN;

#endif  /* _ASMLANGUAGE */

/*
 * Support for determining if we're ROM based or not.  _sysInit
 * saves the startType parameter at location ROM_BASED_FLAG.
 */

#define PCI_AUTOCONFIG_FLAG_OFFSET ( 0x4c00 )
#define PCI_AUTOCONFIG_FLAG ( *(UCHAR *)(LOCAL_MEM_LOCAL_ADRS + \
                                     PCI_AUTOCONFIG_FLAG_OFFSET) )
#define PCI_AUTOCONFIG_DONE ( PCI_AUTOCONFIG_FLAG != 0 )

#ifdef __cplusplus
}
#endif

#endif /* INCmv240xh */