mv2400.h

VxWorks下 MV2400的BSP源码

#define PCI_ID_PRI_LAN          PCI_ID_LN_DEC21143 /* Id for Primary LAN */
#define PCI_ID_BR_DEC21150      0x00221011      /* Id DEC 21150 PCI bridge */

/* PCI Space Definitions  -- For configuring the Hawk */

/* CPU to PCI definitions */

#define CPU2PCI_MSATT_MEM	0x00c2
#define CPU2PCI_MSATT_IO	0x00c0

#ifndef EXTENDED_VME

/* STANDARD ( PREP ) mapping of PCI space */

/* setup address space 0 for PCI MEM space */
#define CPU2PCI_ADDR0_START_VAL	0xfd00
#define CPU2PCI_ADDR0_END_VAL	0xfdff
#define CPU2PCI_OFFSET0_VAL	((0x0-CPU2PCI_ADDR0_START_VAL) & 0xffff)

/* setup address space 1 for PCI I/O space */
#define CPU2PCI_ADDR1_START_VAL	0xfe00
#define CPU2PCI_ADDR1_END_VAL	0xfe7f
#define CPU2PCI_OFFSET1_VAL	((0x0-CPU2PCI_ADDR1_START_VAL) & 0xffff)
#define CPU2PCI_MSATT1_VAL	CPU2PCI_MSATT_IO

/* setup address space 2 for PCI MEM space -- maps VME address space */
#define CPU2PCI_ADDR2_START_VAL	(PCI_MSTR_MEMIO_LOCAL >>16)
#define CPU2PCI_ADDR2_END_VAL	0xfcff
#define CPU2PCI_OFFSET2_VAL	((0x0-CPU2PCI_ADDR2_START_VAL) & 0xffff)

/* setup address space 3 for PCI I/O space */
#define CPU2PCI_ADDR3_START_VAL	(ISA_MSTR_IO_LOCAL >>16)
#define CPU2PCI_ADDR3_END_VAL	0xbf7f
#define CPU2PCI_OFFSET3_VAL	((0x0-CPU2PCI_ADDR3_START_VAL) & 0xffff)

#else

/* EXTENDED VME PCI mapping */

/* setup address space 0 for PCI MEM space -- maps VME address space */
#define CPU2PCI_ADDR0_START_VAL	(VME_A32_MSTR_LOCAL>>16)
#define CPU2PCI_ADDR0_END_VAL	0xfbff
#define CPU2PCI_OFFSET0_VAL	0x0

/* setup address space 1 for PCI MEM, for MPIC regs */
#define CPU2PCI_ADDR1_START_VAL	(MPIC_BASE_ADRS >>16)
#define CPU2PCI_ADDR1_END_VAL	(((MPIC_BASE_ADRS + 0x00ffffff) \
                                  >> 16) & 0x0000ffff)
#define CPU2PCI_OFFSET1_VAL	0x0
#define CPU2PCI_MSATT1_VAL	CPU2PCI_MSATT_MEM

/* setup address space 2 for PCI MEM -- maps reg. space */
#define CPU2PCI_ADDR2_START_VAL	(PCI_MSTR_MEMIO_LOCAL >>16)
#define CPU2PCI_ADDR2_END_VAL	(((PCI_MSTR_MEM_LOCAL+PCI_MSTR_MEM_SIZE-1)\
                                   >> 16) & 0x0000ffff)
#define CPU2PCI_OFFSET2_VAL	0x0

/* setup address space 3 for PCI I/O */
#define CPU2PCI_ADDR3_START_VAL	(ISA_MSTR_IO_LOCAL >>16)
#define CPU2PCI_ADDR3_END_VAL	(((PCI_MSTR_IO_LOCAL + PCI_MSTR_IO_SIZE-1) \
                                   >> 16) & 0x0000ffff)
#define CPU2PCI_OFFSET3_VAL	((0x0-CPU2PCI_ADDR3_START_VAL) & 0xffff)

#endif

/* defines that are used in hawkPhb.c */

#define CPU2PCI_ADDR0_START	CPU2PCI_ADDR0_START_VAL
#define CPU2PCI_ADDR0_END	CPU2PCI_ADDR0_END_VAL
#define CPU2PCI_OFFSET0		CPU2PCI_OFFSET0_VAL
#define CPU2PCI_MSATT0		CPU2PCI_MSATT_MEM
#define CPU2PCI_ADDR1_START	CPU2PCI_ADDR1_START_VAL
#define CPU2PCI_ADDR1_END	CPU2PCI_ADDR1_END_VAL
#define CPU2PCI_OFFSET1		CPU2PCI_OFFSET1_VAL
#define CPU2PCI_MSATT1		CPU2PCI_MSATT1_VAL
#define CPU2PCI_ADDR2_START	CPU2PCI_ADDR2_START_VAL
#define CPU2PCI_ADDR2_END	CPU2PCI_ADDR2_END_VAL
#define CPU2PCI_OFFSET2		CPU2PCI_OFFSET2_VAL
#define CPU2PCI_MSATT2		CPU2PCI_MSATT_MEM
#define CPU2PCI_ADDR3_START	CPU2PCI_ADDR3_START_VAL
#define CPU2PCI_ADDR3_END	CPU2PCI_ADDR3_END_VAL
#define CPU2PCI_OFFSET3		CPU2PCI_OFFSET3_VAL
#define CPU2PCI_MSATT3		CPU2PCI_MSATT_IO

/* PCI to CPU definitions */

#ifdef LOCAL_MEM_AUTOSIZE
# define DRAM_SIZE		((ULONG)sysPhysMemTop() - LOCAL_MEM_LOCAL_ADRS)
#else
# define DRAM_SIZE		(LOCAL_MEM_SIZE - LOCAL_MEM_LOCAL_ADRS)
#endif

/* Hawk Slave Window Attributes */

#define HAWK_PCI_SLV_ATTR_REN_BIT   7	/* allow reads from PCI bus */
#define HAWK_PCI_SLV_ATTR_WEN_BIT   6	/* allow writes from PCI bus */
#define HAWK_PCI_SLV_ATTR_WPEN_BIT  5	/* enable write posting */
#define HAWK_PCI_SLV_ATTR_RAEN_BIT  4	/* enable read-ahead */
#define HAWK_PCI_SLV_ATTR_GBL_BIT   1	/* mark read and write cycles global */
#define HAWK_PCI_SLV_ATTR_INV_BIT   0	/* enable invalidate transactions */

#define HAWK_PCI_SLV_ATTR_REN_MASK	(1<<HAWK_PCI_SLV_ATTR_REN_BIT)
#define HAWK_PCI_SLV_ATTR_WEN_MASK	(1<<HAWK_PCI_SLV_ATTR_WEN_BIT)
#define HAWK_PCI_SLV_ATTR_WPEN_MASK	(1<<HAWK_PCI_SLV_ATTR_WPEN_BIT)
#define HAWK_PCI_SLV_ATTR_RAEN_MASK	(1<<HAWK_PCI_SLV_ATTR_RAEN_BIT)
#define HAWK_PCI_SLV_ATTR_GBL_MASK	(1<<HAWK_PCI_SLV_ATTR_GBL_BIT)
#define HAWK_PCI_SLV_ATTR_INV_MASK	(1<<HAWK_PCI_SLV_ATTR_INV_BIT)

/* Hawk PCI Slave Window definitions */

#define PCI2CPU_ADDR0_START     (PCI_SLV_MEM_BUS & 0xffff0000)
#define PCI2CPU_ADDR0_END       ((PCI_SLV_MEM_BUS + DRAM_SIZE - 1) >> 16)
#define PCI2CPU_ADDR0_RANGE     (PCI2CPU_ADDR0_START | PCI2CPU_ADDR0_END)
#define PCI2CPU_OFFSET0         (((0x0-PCI_SLV_MEM_BUS)>>16) & 0x0000ffff)
#define PCI2CPU_ATT0            (HAWK_PCI_SLV_ATTR_REN_MASK  | \
				 HAWK_PCI_SLV_ATTR_WEN_MASK  | \
				 HAWK_PCI_SLV_ATTR_WPEN_MASK | \
				 HAWK_PCI_SLV_ATTR_RAEN_MASK | \
				 HAWK_PCI_SLV_ATTR_GBL_MASK  | \
				 HAWK_PCI_SLV_ATTR_INV_MASK)

/*
 * Address decoders 1, 2 and 3 are not currently used, so they are
 * set to point to an address that is not used on the PCI bus
 */
#define PCI2CPU_ADDR1_RANGE     0xfff0fff0
#define PCI2CPU_OFFSET1         0x0
#define PCI2CPU_ATT1            0x0
#define PCI2CPU_ADDR2_RANGE     0xfff0fff0
#define PCI2CPU_OFFSET2         0x0
#define PCI2CPU_ATT2            0x0
#define PCI2CPU_ADDR3_RANGE     0xfff0fff0
#define PCI2CPU_OFFSET3         0x0
#define PCI2CPU_ATT3            0x0

/*
 * Allocate PCI Memory and I/O Space Offsets for PCI devices
 *
 * All devices on the primary and secondary busses are allocated 64 kb spaces.
 * The PMC Span can control up to four PMCs.
 */

#define SCSI_DEV_SPACE		0x10000
#define LAN_DEV_SPACE		0x20000
#define VGA_DEV_SPACE		0x30000
#define PMC_DEV_SPACE		0x40000
#define VME_DEV_SPACE		0x50000
#define LAN2_DEV_SPACE		0x60000
#define SCSI_DEV_SPACE2		0x70000
#define	SPAN_IO_DEV_SPACE	0x80000
#define	SPAN_IO_DEV_SIZE	0x40000
#define SPAN_MEM_DEV_SPACE	0x02000000
#define SPAN_MEM_DEV_SIZE	0x01000000
#define SPAN_PREF_DEV_SPACE	0x01000000
#define SPAN_PREF_DEV_SIZE	0x01000000

/* PCI view of PCI I/O Space for PCI devices */

#define PCI_IO_SCSI_ADRS	(PCI_MSTR_IO_BUS + SCSI_DEV_SPACE)	/* 53C825 */
#define PCI_IO_LN_ADRS		(PCI_MSTR_IO_BUS + LAN_DEV_SPACE)	/* PCnet */
#define PCI_IO_VGA_ADRS		(PCI_MSTR_IO_BUS + VGA_DEV_SPACE)	/* GD5434 */
#define PCI_IO_PMC_ADRS		(PCI_MSTR_IO_BUS + PMC_DEV_SPACE)	/* extra */
#define PCI_IO_LN2_ADRS		(PCI_MSTR_IO_BUS + LAN2_DEV_SPACE)  /* 21040   */
#define PCI_IO_SCSI_ADRS2	(PCI_MSTR_IO_BUS + SCSI_DEV_SPACE2) /* 53C825A */

/* PCI view of PCI Memory Space for PCI devices */

#define PCI_MEM_UNIVERSE_ADRS    (PCI_MSTR_MEM_BUS + VME_DEV_SPACE)	/* UNIVERSE */

/* Allocated base address of HW devices as seen from CPU */

#define SCSI_BASE_ADRS		( PCI_MSTR_IO_LOCAL + SCSI_DEV_SPACE )
#define LAN_BASE_ADRS		( PCI_MSTR_IO_LOCAL + LAN_DEV_SPACE )
#define UNIVERSE_BASE_ADRS	( PCI_MSTR_MEM_LOCAL + VME_DEV_SPACE )
#define LAN2_BASE_ADRS		( PCI_MSTR_IO_LOCAL + LAN2_DEV_SPACE )
#define SCSI_BASE_ADRS2		( PCI_MSTR_IO_LOCAL + SCSI_DEV_SPACE2 )

/* z8536 aux timer and I/O chip */

#define z8536_PORTC_DATA        (ISA_MSTR_IO_LOCAL + 0x0844)
#define z8536_PORTB_DATA        (ISA_MSTR_IO_LOCAL + 0x0845)
#define z8536_PORTA_DATA        (ISA_MSTR_IO_LOCAL + 0x0846)
#define z8536_PORT_CTRL         (ISA_MSTR_IO_LOCAL + 0x0847)
#define ZCIO_CNTRL_ADRS         (UINT8 *)(ISA_MSTR_IO_LOCAL + 0x847)
#define ZCIO_IACK_ADRS          (UINT8 *)(ISA_MSTR_IO_LOCAL + 0x84F)

/* m48TXX non volatile ram, RTC and watchdog timer */

#define m48TXX_LSB_REG		(ISA_MSTR_IO_LOCAL + 0x0074)
#define	m48TXX_MSB_REG		(ISA_MSTR_IO_LOCAL + 0x0075)
#define m48TXX_DAT_REG		(ISA_MSTR_IO_LOCAL + 0x0077)

/* CPU type */

#define CPU_TYPE                ((vxPvrGet() >> 16) & 0xffff)
#define CPU_TYPE_601		0x01	/* PPC 601 CPU */
#define CPU_TYPE_602		0x02	/* PPC 602 CPU */
#define CPU_TYPE_603		0x03	/* PPC 603 CPU */
#define CPU_TYPE_603E           0x06    /* PPC 603e CPU */
#define CPU_TYPE_603P           0x07    /* PPC 603p CPU */
#define CPU_TYPE_750            0x08    /* PPC 750 CPU */
#define CPU_TYPE_604		0x04	/* PPC 604 CPU */
#define CPU_TYPE_604E		0x09	/* PPC 604e CPU */
#define CPU_TYPE_604R		0x0A	/* PPC 604r CPU */
#define CPU_TYPE_MAX            0x0C    /* PPC MAX CPU */

/* Vital Product Data Support */

#ifdef MV2400
#define SPD_EEPROM_ADRS 0xa8        /* i2c address of first SPD EEPROM */
#define VPD_BRD_EEPROM_ADRS 0xa0    /* i2c address of board's SROM */
#define VPD_BRD_OFFSET      0   /* offset into board's eeprom for vpd data */
#define VPD_PKT_LIMIT       25  /* Max number of packets expected */

#define DEFAULT_PCI_CLOCK	33333333
#define DEFAULT_BUS_CLOCK	100000000
#define DEFAULT_INTERNAL_CLOCK	350000000
#define DEFAULT_PRODUCT_ID	"Unknown"
#endif

/* Product Configuration Options (PCO) */

#define PCO_PCI0_CONN1		0
#define PCO_PCI0_CONN2		1
#define PCO_PCI0_CONN3		2
#define PCO_PCI0_CONN4		3

#define PCO_PCI1_CONN1		4
#define PCO_PCI1_CONN2		5
#define PCO_PCI1_CONN3		6
#define PCO_PCI1_CONN4		7

#define PCO_ISA_CONN1		8
#define PCO_ISA_CONN2		9
#define PCO_ISA_CONN3		10
#define PCO_ISA_CONN4		11

#define PCO_EIDE1_CONN1		12
#define PCO_EIDE1_CONN2		13
#define PCO_EIDE2_CONN1		14
#define PCO_EIDE2_CONN2		15

#define PCO_ENET1_CONN		16
#define PCO_ENET2_CONN		17
#define PCO_ENET3_CONN		18
#define PCO_ENET4_CONN		19

#define PCO_SCSI1_CONN		20
#define PCO_SCSI2_CONN		21
#define PCO_SCSI3_CONN		22
#define PCO_SCSI4_CONN		23

#define PCO_SERIAL1_CONN	24
#define PCO_SERIAL2_CONN	25
#define PCO_SERIAL3_CONN	26
#define PCO_SERIAL4_CONN	27

#define PCO_FLOPPY_CONN1	28
#define PCO_FLOPPY_CONN2	29
#define PCO_PARALLEL1_CONN	30
#define PCO_PARALLEL2_CONN	31

#define PCO_PMC1_IO_CONN	32
#define PCO_PMC2_IO_CONN	33
#define PCO_USB0_CONN		34
#define PCO_USB1_CONN		35

#define PCO_KEYBOARD_CONN	36
#define PCO_MOUSE_CONN		37
#define PCO_VGA1_CONN		38
#define PCO_SPEAKER_CONN	39

#define PCO_VME_CONN		40
#define PCO_CPCI_CONN		41
#define PCO_ABORT_SWITCH	42
#define PCO_BDFAIL_LIGHT	43

#define PCO_SWREAD_HEADER	44
#define PCO_MEMMEZ_CONN		45
#define PCO_PCI0EXP_CONN	46

/* BSP configuration error policy */

#define CONTINUE_EXECUTION	0       /* Tolerate VPD/Configuration errors */
#define EXIT_TO_SYSTEM_MONITOR	1       /* Transfer to System Monitor */

#ifdef VPD_ERRORS_NONFATAL
#    define     DEFAULT_BSP_ERROR_BEHAVIOR  CONTINUE_EXECUTION
#else
#    define     DEFAULT_BSP_ERROR_BEHAVIOR  EXIT_TO_SYSTEM_MONITOR
#endif

/* z8536 I/O port bit mapping */

#define z8536_PORTA_BRDFAIL     0x40
#define z8536_PORTB_ABORT       0x80

/*
 * Hawk Extensions to Standard PCI Header
 *
 * Type declarations for the PCI Header and the macros in regards to the
 * PCI BUS.  These definitions have been made with respect to PCI LOCAL
 * BUS SPECIFICATION REVISION 2.1.  Every device on the PCI BUS has to
 * support 256 bytes of configuration space of which the first 64 bytes
 * are a predefined header portion defined by the PCI commitee.  Bytes
 * 64 to 255 are dedicated to the device specific registers.
 *
 * Note: the PCI bus is inherently little endian. 
 */

#define PCI_CFG_HAWK_PSADD0	0x80
#define PCI_CFG_HAWK_PSATT0	0x84
#define PCI_CFG_HAWK_PSOFF0	0x86
#define PCI_CFG_HAWK_PSADD1	0x88
#define PCI_CFG_HAWK_PSATT1	0x8c
#define PCI_CFG_HAWK_PSOFF1	0x8e
#define PCI_CFG_HAWK_PSADD2	0x90
#define PCI_CFG_HAWK_PSATT2	0x94
#define PCI_CFG_HAWK_PSOFF2	0x96
#define PCI_CFG_HAWK_PSADD3	0x98
#define PCI_CFG_HAWK_PSATT3	0x9c
#define PCI_CFG_HAWK_PSOFF3	0x9e

/* Hawk MPC registers */

#define HAWK_MPC_VENID		0x00
#define HAWK_MPC_DEVID		0x02
#define HAWK_MPC_REVID		0x05
#define HAWK_MPC_GCSR		0x08
#define HAWK_MPC_FEAT		0x0a
#define HAWK_MPC_MARB		0x0c
#define HAWK_MPC_PADJ		0x13
#define HAWK_MPC_MEREN		0x22
#define HAWK_MPC_MERST		0x27
#define HAWK_MPC_MERAD		0x28
#define HAWK_MPC_MERAT		0x2e
#define HAWK_MPC_PIACK		0x30
#define HAWK_MPC_MSADD0	0x40
#define HAWK_MPC_MSOFF0	0x44
#define HAWK_MPC_MSATT0	0x47
#define HAWK_MPC_MSADD1	0x48
#define HAWK_MPC_MSOFF1	0x4c
#define HAWK_MPC_MSATT1	0x4f
#define HAWK_MPC_MSADD2	0x50
#define HAWK_MPC_MSOFF2	0x54
#define HAWK_MPC_MSATT2	0x57
#define HAWK_MPC_MSADD3	0x58
#define HAWK_MPC_MSOFF3	0x5c
#define HAWK_MPC_MSATT3	0x5f
#define HAWK_MPC_WDT1CNTL      0x60
#define HAWK_MPC_WDT2CNTL      0x68
#define HAWK_MPC_GPREG0_U	0x70
#define HAWK_MPC_GPREG0_L	0x74
#define HAWK_MPC_GPREG1_U	0x78
#define HAWK_MPC_GPREG1_L	0x7c

/*
 * Bootrom error bits.
 * These bits are set during ROM startup before error annunciation is available
 * to save error conditions for later reporting.
 */

/* bits in Group A (Hawk GPREG0_U [0x0070]) */

#define BOOTROM_NO_VPD_BUS_SPEED       0x80000000     /* Couldn't read VPD */
#define BOOTROM_DEFAULT_SMC_TIMING     0x40000000     /* Couldn't read SPD */

/*
 * Hawk MPC General Status and Configuration bits
 */

#define HAWK_MPC_GCSR_OPIC_ENA	0x0020