mv2400.h

VxWorks下 MV2400的BSP源码

/* mv2400.h - Motorola PowerPlus board header */

/* Copyright 1984-2001 Wind River Systems, Inc. */
/* Copyright 1996,1997,1998,1999 Motorola, Inc. All Rights Reserved */

/*
modification history
--------------------
01v,05nov01,dat  Remove extra ';'s, Diab was choking
01u,16sep01,dat  Use of WRS_ASM macro
01t,19nov99,srr  Removed VME_A32_MSTR_LOCAL, moved to config.h
01s,16jul99,rhv  Correcting error in PCI_CLINE_SZ definition.
01r,09jul99,rhv  Added #defines for Hawk configurations constants.
01q,01jul99,rhv  Incorporating WRS code review changes.
01p,19may99,rhv  Fixing an error in file history and correcting some comment
                 errors.
01o,14may99,rhv  Set INV bit in Hawk PCI slave attributes to correct a live-lock
                 problem related to Universe II RMW cycles and the use of the
                 PCI LOCK# signal.
01n,12may99,rhv  Changing PCI2DRAM_BASE_ADRS to PCI_SLV_MEM_BUS as part of
                 WRS PCI symbol update.
01m,12may99,rhv  Modified to use WRS PCI symbols.
01l,27jan99,mdp  Added 21143 doze bit for SENS support.
01k,27jan99,rhv  Changing name of ROM startup errors to be consistent with
                 WRS naming (Bootrom instead of RomStart).
01j,22jan99,rhv  Adding ROM startup error reporting.
01i,22jan99,mdp  Moved MPC750 CCR defines to sysCache.h.
01h,21jan99,dmw  Add masks for addressing extened vs. non-extended ranges.
01g,21jan99,rhv  Adding processor bus parity support.
01f,20jan99,rhv  Adjusting value of CPU2PCI_ADDR0_START_VAL to eliminate 2603
                 work-around.
01e,19jan99,rhv  Removing obsolete definitions.
01d,14jan99,mdp  Fix for Hawk Aux Clock.
01c,14jan99,dmw  Add PCI_ID_IDE for device exclusion. 
01b,13jan99,rhv  Added SPD EEPROM address, new Hawk register definitions
                 and updated copyright.
01a,15dec98,mdp  written. (from ver 02h, mv2600.h)

*/

/*
This file contains I/O addresses and related constants for the
Motorola PowerPlus VME board. 
*/

#ifndef	INCmv240xh
#define	INCmv240xh

#ifdef __cplusplus
extern "C" {
#endif

#define INCLUDE_PCI		/* always include pci */

/* Boot Line parameters are stored in the 2nd 256 byte block */

#undef	NV_BOOT_OFFSET
#define NV_BOOT_OFFSET		256 /* skip 1st 256 bytes */
#define NV_RAM_SIZE    		BBRAM_SIZE		
#define NV_RAM_ADRS    		((char *) BBRAM_ADRS)
#define NV_RAM_INTRVL           1

/* PMC-Span setup values */

#define P2P_IO_SPACE_BASE_ADRS  ((P2P_IO_BASE & 0x0000F000) >> 8)
#define P2P_IO_SPACE_LIMIT_ADRS ((P2P_IO_BASE + P2P_IO_SIZE - 1) & 0x0000F000)
#define	P2P_IO_HI16_BASE_ADRS   ((P2P_IO_BASE & 0xFFFF0000) >> 16)
#define	P2P_IO_HI16_LIMIT_ADRS  ((P2P_IO_BASE + P2P_IO_SIZE - 1) & 0xFFFF0000)
#define P2P_NPMEM_SPACE_BASE_ADRS ((P2P_NONPREF_MEM_BASE & 0xFFFF0000) >> 16)
#define P2P_NPMEM_SPACE_LIMIT_ADRS ((P2P_NONPREF_MEM_BASE + \
                                     P2P_NONPREF_MEM_SIZE - 1) & 0xFFFF0000)
#define P2P_PREF_MEM_BASE_ADRS  ((P2P_PREF_MEM_BASE & 0xFFFF0000) >> 16)
#define P2P_PREF_MEM_LIMIT_ADRS ((P2P_PREF_MEM_BASE + P2P_PREF_MEM_SIZE - 1) & \
                                 0xFFFF0000)

/* PCI I/O function defines */

#define INT_NUM_IRQ0            INT_VEC_IRQ0

#ifndef _ASMLANGUAGE

extern  UINT sysGetBusSpd (void);

#ifndef PCI_IN_BYTE
#define PCI_IN_BYTE(x)          sysPciInByte (x)
IMPORT  UINT8                   sysPciInByte  (UINT32 address);
#endif
#ifndef PCI_IN_WORD
#define PCI_IN_WORD(x)          sysPciInWord (x)
IMPORT  UINT16                  sysPciInWord  (UINT32 address);
#endif
#ifndef PCI_IN_LONG
#define PCI_IN_LONG(x)          sysPciInLong (x)
IMPORT  UINT32                  sysPciInLong  (UINT32 address);
#endif
#ifndef PCI_OUT_BYTE
#define PCI_OUT_BYTE(x,y)       sysPciOutByte (x,y)
IMPORT  void                    sysPciOutByte (UINT32 address, UINT8  data);
#endif
#ifndef PCI_OUT_WORD
#define PCI_OUT_WORD(x,y)       sysPciOutWord (x,y)
IMPORT  void                    sysPciOutWord (UINT32 address, UINT16 data);
#endif
#ifndef PCI_OUT_LONG
#define PCI_OUT_LONG(x,y)       sysPciOutLong (x,y)
IMPORT  void                    sysPciOutLong (UINT32 address, UINT32 data);
#endif

#endif  /* _ASMLANGUAGE */

/* Cache Line Size - 8 32-bit value = 32 bytes */

#define PCI_CLINE_SZ		(_CACHE_ALIGN_SIZE/4)

/* Latency Timer value - 255 PCI clocks */

#define PCI_LAT_TIMER		0xff

/* clock rates */

/* Calculate Memory Bus Rate in Hertz */

#define MEMORY_BUS_SPEED                ( sysGetBusSpd() )

/* System clock (decrementer counter) frequency determination */

#define DEC_CLOCK_FREQ          ( sysGetBusSpd() )

/*
 * The PowerPC Decrementer is used as the system clock.
 * It is always included in this BSP.  The following defines
 * are used by the system clock library.
 */

#define SYS_CLK_RATE_MIN  	10		/* minimum system clock rate */
#define SYS_CLK_RATE_MAX  	5000		/* maximum system clock rate */

/*
 * This macro returns the positive difference between two signed ints.
 * Useful for determining delta between two successive decrementer reads.
 */

#define DELTA(a,b)	( abs((int)a - (int)b) )

/*
 * Auxiliary Clock support is an optional feature that is not supported
 * by all BSPs.  The following defines are used by the aux clock library.
 */

#define AUX_CLK_RATE_MIN  	40		/* min auxiliary clock */
#define AUX_CLK_RATE_MAX	5000		/* max auxiliary clock rate */

/*
 * Shared Memory Interrupt Type.
 * Interrupt this target with a 1-byte write mailbox.
 * VME_A32 space, address based on procNum, value is SIG1_INTR_SET.
 */

#define SM_INT_ARG1 	VME_AM_EXT_SUP_DATA
#define SM_INT_ARG2 	(VME_A32_REG_BASE +(sysProcNumGet() * VME_A32_REG_SIZE))
#define SM_INT_ARG3	SIG1_INTR_SET

/*
 * Semaphore Test-and-Set Register as seen from a slave
 * Only used with a special version of sysBusTas().
 */

#define OFFBRD_VME_SEM_REG1	(CPU_VME_WINDOW_REG_BASE + \
				 (CPU_VME_SEM_REG1 - CPU_VME_HW_REGS_BASE)) 

/* Common I/O synchronizing instructions */

#ifndef EIEIO_SYNC
# define EIEIO_SYNC  WRS_ASM (" eieio; sync")
#endif  /* EIEIO_SYNC */
#ifndef EIEIO
# define EIEIO    WRS_ASM (" eieio")
#endif  /* EIEIO */

/* Translation macro */

#define TRANSLATE(x,y,z)\
        ((UINT)(x) - (UINT)(y) + (UINT)(z))

/*
 * Legacy ISA space size. Reserved for kybd, com1, com2,...
 */

#define ISA_LEGACY_SIZE 0x00004000

#ifndef EXTENDED_VME

/* Pseudo PREP memory map (maximizes available PCI addressing space) */

/* ISA I/O space within PCI I/O space (includes ISA legacy space) */

#define ISA_MSTR_IO_LOCAL	0x80000000
#define ISA_MSTR_IO_BUS		0x00000000	/* must be zero */
#define ISA_MSTR_IO_SIZE	0x00010000	/* 64 kbytes */

/*
 * PCI I/O space (above ISA I/O space)
 *
 * NOTE: (PCI_MSTR_IO_LOCAL+PCI_MSTR_IO_SIZE) must be less than
 *       PCI_MSTR_MEMIO_LOCAL to prevent overlap. PCI_MSTR_IO_SIZE
 *       is defined in config.h
 */

#define PCI_MSTR_IO_LOCAL   (ISA_MSTR_IO_LOCAL+ISA_MSTR_IO_SIZE)
#define PCI_MSTR_IO_BUS     (TRANSLATE(PCI_MSTR_IO_LOCAL,\
                                       ISA_MSTR_IO_LOCAL,\
                                       ISA_MSTR_IO_BUS))

/*
 * PCI Memory I/O (non-prefetchable)
 *
 * NOTE: PCI_MSTR_MEMIO_SIZE is defined in config.h
 */

#define PCI_MSTR_MEMIO_LOCAL	0xc0000000      /* base of ISA mem space */
#define PCI_MSTR_MEMIO_BUS	0x00000000	/* must be zero */

/*
 * PCI (pre-fetchable) Memory space (above PCI I/O Memory space)
 *
 * NOTE: (PCI_MSTR_MEM_LOCAL+PCI_MSTR_MEM_SIZE) must be less than
 *        VME_A32_MSTR_LOCAL to prevent overlap. PCI_MSTR_MEM_SIZE is
 *        defined in config.h
 */

#define PCI_MSTR_MEM_LOCAL	(PCI_MSTR_MEMIO_LOCAL+PCI_MSTR_MEMIO_SIZE)
#define PCI_MSTR_MEM_BUS	(TRANSLATE(PCI_MSTR_MEM_LOCAL,\
                                           PCI_MSTR_MEMIO_LOCAL,\
                                           PCI_MSTR_MEMIO_BUS))

#else

/* Extended VME memory map (maximizes VME A32 space) */

/* ISA I/O space within PCI I/O space (includes ISA legacy space) */

#define ISA_MSTR_IO_LOCAL	0xfe000000  /* base of ISA I/O space */
#define ISA_MSTR_IO_BUS		0x00000000  /* must be zero */
#define ISA_MSTR_IO_SIZE	0x00010000  /* 64 kbytes (includes legacy) */

/*
 * PCI I/O space (above ISA I/O space)
 *
 * NOTE: (PCI_MSTR_IO_LOCAL+PCI_MSTR_IO_SIZE) must be less than
 *       HAWK_SMC_BASE_ADRS to prevent overlap. PCI_MSTR_IO_SIZE
 *       is defined in config.h
 */

#define PCI_MSTR_IO_LOCAL	(ISA_MSTR_IO_LOCAL+ISA_MSTR_IO_SIZE)
#define PCI_MSTR_IO_BUS         (TRANSLATE(PCI_MSTR_IO_LOCAL,\
                                           ISA_MSTR_IO_LOCAL,\
                                           ISA_MSTR_IO_BUS))

/*
 * PCI Memory I/O (non-prefetchable)
 *
 * NOTE: PCI_MSTR_MEMIO_SIZE is defined in config.h
 */

#define PCI_MSTR_MEMIO_LOCAL	0xfd000000      /* base of ISA mem space */
#define PCI_MSTR_MEMIO_BUS	PCI_MSTR_MEMIO_LOCAL	/* 1-1 mapping */

/*
 * PCI (pre-fetchable) Memory space (above PCI I/O Memory space)
 *
 * NOTE: (PCI_MSTR_MEM_LOCAL+PCI_MSTR_MEM_SIZE) must be less than
 *        ISA_MSTR_IO_LOCAL to prevent overlap. PCI_MSTR_MEM_SIZE is
 *        defined in config.h
 */

#define PCI_MSTR_MEM_LOCAL	(PCI_MSTR_MEMIO_LOCAL+PCI_MSTR_MEMIO_SIZE)
#define PCI_MSTR_MEM_BUS	(TRANSLATE(PCI_MSTR_MEM_LOCAL,\
                                           PCI_MSTR_MEMIO_LOCAL,\
                                           PCI_MSTR_MEMIO_BUS))
#endif

/*
 * PCI MASTER MEMORY WINDOW LIMITS
 *
 * These values are strictly defined by the base memory addresses and window
 * sizes of the spaces defined above.  These values must be correct for the
 * sysBusProbe() memory range checks for the PCI bus to work properly.
 */

#ifndef EXTENDED_VME
#  define PCI_MSTR_LO_ADRS      (ISA_MSTR_IO_LOCAL)
#  define PCI_MSTR_HI_ADRS      (PCI_MSTR_MEM_LOCAL + PCI_MSTR_MEM_SIZE)
#else
#  define PCI_MSTR_LO_ADRS      (PCI_MSTR_MEMIO_LOCAL)
#  define PCI_MSTR_HI_ADRS      (PCI_MSTR_IO_LOCAL + PCI_MSTR_IO_SIZE)
#endif  /* EXTENDED_VME */

#ifndef INCLUDE_MPIC

#define MPIC_ADDR(reg)		(MPIC_BASE_ADRS + reg)
#define MPIC_GLOBAL_CONFIG_REG	0x01020
#define RESET_CNTRLR		0x80000000

#endif  /* INCLUDE_MPIC */

/*
 * Base address of HW devices as seen from CPU.
 *
 * Note: The HAWK ASIC is a combined FALCON/RAVEN. So the HAWK SMC
 * (System Memory Contoller) is equivalent to the FALCON and the
 * HAWK PHB (PCI Host Bridge) is equivalent to the RAVEN.
 */

#define HAWK_SMC_BASE_ADRS	0xfef80000
#define	HAWK_SMC_REG_SIZE	0x00010000
#define HAWK_SMC_BASE_UPPER_ADRS	(HAWK_SMC_BASE_ADRS>>16)
#define HAWK_SMC_SDRAM_ATTR_AD	0xfef80010
#define HAWK_SMC_SDRAM_BASE_AD	0xfef80018
#define HAWK_SMC_CLOCK_FREQ	0xfef80020
#define HAWK_SMC_SDRAM_ATTR_EH	0xfef800c0
#define HAWK_SMC_SDRAM_BASE_EH	0xfef800c8
#define HAWK_SMC_SDRAM_CNTRL	0xfef800d0

#define HAWK_PHB_BASE_ADRS	0xfeff0000
#define	HAWK_PHB_REG_SIZE	0x00010000
#define	FLASH_BASE_ADRS		0xFF000000
#define	FLASH_MEM_SIZE		0x01000000

/* MPIC configuration defines */

#define MPIC_BASE_ADRS		0xfc000000
#define MPIC_REG_SIZE		0x00040000
#ifndef EXTENDED_VME 
#  define MPIC_PCI_BASE_ADRS	(TRANSLATE(MPIC_BASE_ADRS,\
                                           PCI_MSTR_MEMIO_LOCAL,\
                                           PCI_MSTR_MEMIO_BUS))
#else
#  define MPIC_PCI_BASE_ADRS	MPIC_BASE_ADRS
#endif /* Extended VME config */

/* memory map as seen on the PCI bus */

#define PCI_SLV_MEM_LOCAL	LOCAL_MEM_LOCAL_ADRS

#ifndef EXTENDED_VME
#  define PCI_SLV_MEM_BUS	0x80000000      /* memory seen from PCI bus */
#else
#  define PCI_SLV_MEM_BUS	0x00000000      /* memory seen from PCI bus */
#endif /* Extended VME config */

#define PCI_SLV_MEM_SIZE	DRAM_SIZE

#define PCI2DRAM_BASE_ADRS	PCI_SLV_MEM_BUS

/*
 * Primary PCI bus configuration space address and data register addresses
 * as seen by the CPU on the local bus.
 */

#define PCI_PRIMARY_CAR	(ISA_MSTR_IO_LOCAL+0xcf8)
#define PCI_PRIMARY_CDR (ISA_MSTR_IO_LOCAL+0xcfc)

/* Special dec21143 configuration device driver area register */

#define PCI_CFG_21143_DA        0x40

/* PCI Device/Vendor IDs */

#define PCI_ID_HAWK             0x48031057      /* Id for HAWK PHB */
#define PCI_ID_IBC              0x056510ad      /* Id for W83C553 PIB */
#define PCI_ID_IDE              0x010510ad      /* Id for IDE */
#define PCI_ID_UNIVERSE         0x000010e3      /* Id for Universe VME chip */
#define PCI_ID_LN_DEC21143      0x00191011      /* Id DEC chip 21143 */