tc.inc

ATMELurl通用应用一例,可在不同开发中用

;-----------------------------------------------------------------------------
;-		ATMEL Microcontroller Software Support  -	ROUSSET -
;-----------------------------------------------------------------------------
;- File Name			:	tc.inc
;- Object				:	Timer Counter Definition File.
;-
;- 1.0 19/08/97 JCZ	: Creation
;- 1.1 16/06/98 JCZ	: Update register names same as header file
;-----------------------------------------------------------------------------

; Timer Counter Structure
;------------------------

				^	0
TC_CCR		#	4
TC_CMR		#	4
				#	4
				#	4
TC_CV			#	4
TC_RA			#	4
TC_RB			#	4
TC_RC			#	4
TC_SR			#	4
TC_IER		#	4
TC_IDR		#	4
TC_IMR		#	4
				#	4
				#	4
				#	4
				#	4
TC_SIZE		#	0


; Timer Counter Block Structure
;------------------------------
				^	0
TC0			#	TC_SIZE
TC1			#	TC_SIZE
TC2			#	TC_SIZE
TC_BCR		#	4
TC_BMR		#	4

;- Base Address
;--------------
TCBBase		EQU		0xFFFE0000


;-------------------------------------------------
;- Timer Counter Control Register Bits Definition 
;-------------------------------------------------
CLKEN			EQU	(1:SHL:0)
CLKDIS		EQU	(1:SHL:1)
SWTRG			EQU	(1:SHL:2)

;----------------------------------------------
;- Timer Counter Mode Register Bits Definition 
;----------------------------------------------

;- Clock Selection 
TCCLKS			EQU	(&7:SHL:0)
TC_MCK2			EQU	(&0:SHL:0)
TC_MCK8			EQU	(&1:SHL:0)
TC_MCK32			EQU	(&2:SHL:0)
TC_MCK128		EQU	(&3:SHL:0)
TC_MCK1024		EQU	(&4:SHL:0)
TC_XC0			EQU	(&5:SHL:0)
TC_XC1			EQU	(&6:SHL:0)
TC_XC2			EQU	(&7:SHL:0)

;- Clock Inversion 
CLKI				EQU	&08

;- Burst Signal Selection 
BURST				EQU	(&3:SHL:4)
BURST_XC0		EQU	(&1:SHL:4)
BURST_XC1		EQU	(&2:SHL:4)
BURST_XC2		EQU	(&3:SHL:4)


;- Capture Mode : Counter Clock Stopped with RB Loading 
LDBSTOP			EQU	&40

;- Waveform Mode : Counter Clock Stopped with RC Compare 
CPCSTOP			EQU	&40

;- Capture Mode : Counter Clock Disabled with RB Loading 
LDBDIS			EQU	&80

;- Waveform Mode : Counter Clock Disabled with RC Compare 
CPCDIS			EQU	&80

;- Capture Mode : External Trigger Edge Selection 
ETRGEDG			EQU	(&3:SHL:8)

;- Waveform Mode : External Event Edge Selection 
EEVTEDG			EQU	(&3:SHL:8)

;- Capture Mode : TIOA or TIOB External Trigger Selection 
ABETRG			EQU	&400

;- Waveform Mode : External Event Selection 
EEVT				EQU	(&3:SHL:10)
EEVT_XC0			EQU	(&1:SHL:10)
EEVT_XC1			EQU	(&2:SHL:10)
EEVT_XC2			EQU	(&3:SHL:10)


;- Waveform Mode : Enable Trigger on External Event 
ENETRG			EQU	&1000

;- RC Compare Enable Trigger Enable 
CPCTRG			EQU	&4000

;- Mode Selection 
WAVE				EQU	&8000

;- Capture Mode : RA Loading Selection 
LDRA				EQU	(&3:SHL:16)

;- Waveform Mode : RA Compare Effect on TIOA 
ACPA				EQU	(&3:SHL:16)
ACPA_SET			EQU	(&1:SHL:16)
ACPA_CLEAR		EQU	(&2:SHL:16)


;- Capture Mode : RB Loading Selection 
LDRB				EQU	(&3:SHL:18)

;- Waveform Mode : RC Compare Effect on TIOA 
ACPC				EQU	(&3:SHL:18)
ACPC_SET			EQU	(&1:SHL:18)
ACPC_CLEAR		EQU	(&2:SHL:18)

;- Waveform Mode : External Event Effect on TIOA 
AEEVT				EQU	(&3:SHL:20)

;- Waveform Mode : Software Trigger Effect on TIOA 
ASWTRG			EQU	(&3:SHL:22)
ASWTRG_SET		EQU	(&1:SHL:22)
ASWTRG_CLEAR	EQU	(&2:SHL:22)

;- Waveform Mode : RB Compare Effect on TIOB 
BCPB				EQU	(&3:SHL:24)

;- Waveform Mode : RC Compare Effect on TIOB 
BCPC				EQU	(&3:SHL:26)
BCPC_SET			EQU	(&1:SHL:26)
BCPC_CLEAR		EQU	(&2:SHL:26)


;- Waveform Mode : External Event Effect on TIOB 
BEEVT				EQU	(&3:SHL:28)

;- Waveform Mode : Software Trigger Effect on TIOB 
BSWTRG			EQU	(&3:SHL:30)
BSWTRG_SET		EQU	(&1:SHL:30)
BSWTRG_CLEAR	EQU	(&2:SHL:30)


;- Timer Counter Status Register Bits Definition 
;------------------------------------------------
;- Counter Overflow Status 
COVFS				EQU	&01
;- Load Overrun Status 
LOVRS				EQU	&02
;- RA Compare Status 
CPAS				EQU	&04
;- RB Compare Status 
CPBS				EQU	&08
;- RC Compare Status 
CPCS				EQU	&10
;- RA Loading Status 
LDRAS				EQU	&20
;- RB Loading Status 
LDRBS				EQU	&40
;- External Trigger Status 
ETRGS				EQU	&80
;- Clock Status 
CLKSTA			EQU	&10000
;- TIOA Mirror 
MTIOA				EQU	&20000
;- TIOB Status 
MTIOB				EQU	&40000

;- Timer Counter Block Control Register Bits Definition 
;-------------------------------------------------------
;- Synchronisation Trigger 
TCSYNC			EQU	&1

;- Timer Counter Block Mode Register Bits Definition 
;----------------------------------------------------
;- External Clock Signal 0 Selection
TC0XC0S			EQU	(&3:SHL:0)
XC0_TCLK0		EQU	(&0:SHL:0)
XC0_TIOA1		EQU	(&2:SHL:0)
XC0_TIOA2		EQU	(&3:SHL:0)

;- External Clock Signal 1 Selection
TC1XC1S			EQU	(&3:SHL:2)
XC1_TCLK1		EQU	(&0:SHL:2)
XC1_TIOA0		EQU	(&2:SHL:2)
XC1_TIOA2		EQU	(&3:SHL:2)

;- External Clock Signal 2 Selection
TC2XC2S			EQU	(&3:SHL:4)
XC2_TCLK2		EQU	(&0:SHL:4)
XC2_TIOA1		EQU	(&2:SHL:4)
XC2_TIOA2		EQU	(&3:SHL:4)

				END