shubio.h

该文件是rt_linux

 * Description:  There are 9 instances of this register, one per        *
 * actual widget in this implementation of SHub and Crossbow.        *
 * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
 * refers to Crossbow's internal space.                                 *
 * This register contains the state elements per widget that are        *
 * necessary to manage the PIO flow control on Crosstalk and on the     *
 * Router Network. See the PIO Flow Control chapter for a complete      *
 * description of this register                                         *
 * The SPUR_WR bit requires some explanation. When this register is     *
 * written, the new value of the C field is captured in an internal     *
 * register so the hardware can remember what the programmer wrote      *
 * into the credit counter. The SPUR_WR bit sets whenever the C field   *
 * increments above this stored value, which indicates that there       *
 * have been more responses received than requests sent. The SPUR_WR    *
 * bit cannot be cleared until a value is written to the IPRBx          *
 * register; the write will correct the C field and capture its new     *
 * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
 * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
 *                                                                      *
 *                                                                      *
 ************************************************************************/

typedef union ii_iprba_u {
	shubreg_t	ii_iprba_regval;
	struct  {
		shubreg_t	i_c                       :	 8;
		shubreg_t	i_na			  :	14;
		shubreg_t       i_rsvd_2                  :      2;
		shubreg_t	i_nb			  :	14;
		shubreg_t	i_rsvd_1		  :	 2;
		shubreg_t	i_m			  :	 2;
		shubreg_t	i_f			  :	 1;
		shubreg_t	i_of_cnt		  :	 5;
		shubreg_t	i_error			  :	 1;
		shubreg_t	i_rd_to			  :	 1;
		shubreg_t	i_spur_wr		  :	 1;
		shubreg_t	i_spur_rd		  :	 1;
		shubreg_t	i_rsvd			  :	11;
		shubreg_t	i_mult_err		  :	 1;
	} ii_iprba_fld_s;
} ii_iprba_u_t;


/************************************************************************
 *                                                                      *
 * Description:  There are 9 instances of this register, one per        *
 * actual widget in this implementation of SHub and Crossbow.           *
 * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
 * refers to Crossbow's internal space.                                 *
 * This register contains the state elements per widget that are        *
 * necessary to manage the PIO flow control on Crosstalk and on the     *
 * Router Network. See the PIO Flow Control chapter for a complete      *
 * description of this register                                         *
 * The SPUR_WR bit requires some explanation. When this register is     *
 * written, the new value of the C field is captured in an internal     *
 * register so the hardware can remember what the programmer wrote      *
 * into the credit counter. The SPUR_WR bit sets whenever the C field   *
 * increments above this stored value, which indicates that there       *
 * have been more responses received than requests sent. The SPUR_WR    *
 * bit cannot be cleared until a value is written to the IPRBx          *
 * register; the write will correct the C field and capture its new     *
 * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
 * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
 * .                                                                    *
 *                                                                      *
 ************************************************************************/

typedef union ii_iprbb_u {
	shubreg_t	ii_iprbb_regval;
	struct	{
		shubreg_t	i_c			  :	 8;
		shubreg_t	i_na			  :	14;
		shubreg_t	i_rsvd_2		  :	 2;
		shubreg_t	i_nb			  :	14;
		shubreg_t	i_rsvd_1		  :	 2;
		shubreg_t	i_m			  :	 2;
		shubreg_t	i_f			  :	 1;
		shubreg_t	i_of_cnt		  :	 5;
		shubreg_t	i_error			  :	 1;
		shubreg_t	i_rd_to			  :	 1;
		shubreg_t	i_spur_wr		  :	 1;
		shubreg_t	i_spur_rd		  :	 1;
		shubreg_t	i_rsvd			  :	11;
		shubreg_t	i_mult_err		  :	 1;
	} ii_iprbb_fld_s;
} ii_iprbb_u_t;


/************************************************************************
 *                                                                      *
 * Description:  There are 9 instances of this register, one per        *
 * actual widget in this implementation of SHub and Crossbow.           *
 * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
 * refers to Crossbow's internal space.                                 *
 * This register contains the state elements per widget that are        *
 * necessary to manage the PIO flow control on Crosstalk and on the     *
 * Router Network. See the PIO Flow Control chapter for a complete      *
 * description of this register                                         *
 * The SPUR_WR bit requires some explanation. When this register is     *
 * written, the new value of the C field is captured in an internal     *
 * register so the hardware can remember what the programmer wrote      *
 * into the credit counter. The SPUR_WR bit sets whenever the C field   *
 * increments above this stored value, which indicates that there       *
 * have been more responses received than requests sent. The SPUR_WR    *
 * bit cannot be cleared until a value is written to the IPRBx          *
 * register; the write will correct the C field and capture its new     *
 * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
 * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
 * .                                                                    *
 *                                                                      *
 ************************************************************************/

typedef union ii_iprbc_u {
	shubreg_t	ii_iprbc_regval;
	struct	{
		shubreg_t	i_c			  :	 8;
		shubreg_t	i_na			  :	14;
		shubreg_t	i_rsvd_2		  :	 2;
		shubreg_t	i_nb			  :	14;
		shubreg_t	i_rsvd_1		  :	 2;
		shubreg_t	i_m			  :	 2;
		shubreg_t	i_f			  :	 1;
		shubreg_t	i_of_cnt		  :	 5;
		shubreg_t	i_error			  :	 1;
		shubreg_t	i_rd_to			  :	 1;
		shubreg_t	i_spur_wr		  :	 1;
		shubreg_t	i_spur_rd		  :	 1;
		shubreg_t	i_rsvd			  :	11;
		shubreg_t	i_mult_err		  :	 1;
	} ii_iprbc_fld_s;
} ii_iprbc_u_t;


/************************************************************************
 *                                                                      *
 * Description:  There are 9 instances of this register, one per        *
 * actual widget in this implementation of SHub and Crossbow.           *
 * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
 * refers to Crossbow's internal space.                                 *
 * This register contains the state elements per widget that are        *
 * necessary to manage the PIO flow control on Crosstalk and on the     *
 * Router Network. See the PIO Flow Control chapter for a complete      *
 * description of this register                                         *
 * The SPUR_WR bit requires some explanation. When this register is     *
 * written, the new value of the C field is captured in an internal     *
 * register so the hardware can remember what the programmer wrote      *
 * into the credit counter. The SPUR_WR bit sets whenever the C field   *
 * increments above this stored value, which indicates that there       *
 * have been more responses received than requests sent. The SPUR_WR    *
 * bit cannot be cleared until a value is written to the IPRBx          *
 * register; the write will correct the C field and capture its new     *
 * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
 * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
 * .                                                                    *
 *                                                                      *
 ************************************************************************/

typedef union ii_iprbd_u {
	shubreg_t	ii_iprbd_regval;
	struct	{
		shubreg_t	i_c			  :	 8;
		shubreg_t	i_na			  :	14;
		shubreg_t	i_rsvd_2		  :	 2;
		shubreg_t	i_nb			  :	14;
		shubreg_t	i_rsvd_1		  :	 2;
		shubreg_t	i_m			  :	 2;
		shubreg_t	i_f			  :	 1;
		shubreg_t	i_of_cnt		  :	 5;
		shubreg_t	i_error			  :	 1;
		shubreg_t	i_rd_to			  :	 1;
		shubreg_t	i_spur_wr		  :	 1;
		shubreg_t	i_spur_rd		  :	 1;
		shubreg_t	i_rsvd			  :	11;
		shubreg_t	i_mult_err		  :	 1;
	} ii_iprbd_fld_s;
} ii_iprbd_u_t;


/************************************************************************
 *                                                                      *
 * Description:  There are 9 instances of this register, one per        *
 * actual widget in this implementation of SHub and Crossbow.           *
 * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
 * refers to Crossbow's internal space.                                 *
 * This register contains the state elements per widget that are        *
 * necessary to manage the PIO flow control on Crosstalk and on the     *
 * Router Network. See the PIO Flow Control chapter for a complete      *
 * description of this register                                         *
 * The SPUR_WR bit requires some explanation. When this register is     *
 * written, the new value of the C field is captured in an internal     *
 * register so the hardware can remember what the programmer wrote      *
 * into the credit counter. The SPUR_WR bit sets whenever the C field   *
 * increments above this stored value, which indicates that there       *
 * have been more responses received than requests sent. The SPUR_WR    *
 * bit cannot be cleared until a value is written to the IPRBx          *
 * register; the write will correct the C field and capture its new     *
 * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
 * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
 * .                                                                    *
 *                                                                      *
 ************************************************************************/

typedef union ii_iprbe_u {
	shubreg_t	ii_iprbe_regval;
	struct	{
		shubreg_t	i_c			  :	 8;
		shubreg_t	i_na			  :	14;
		shubreg_t	i_rsvd_2		  :	 2;
		shubreg_t	i_nb			  :	14;
		shubreg_t	i_rsvd_1		  :	 2;
		shubreg_t	i_m			  :	 2;
		shubreg_t	i_f			  :	 1;
		shubreg_t	i_of_cnt		  :	 5;
		shubreg_t	i_error			  :	 1;
		shubreg_t	i_rd_to			  :	 1;
		shubreg_t	i_spur_wr		  :	 1;
		shubreg_t	i_spur_rd		  :	 1;
		shubreg_t	i_rsvd			  :	11;
		shubreg_t	i_mult_err		  :	 1;
	} ii_iprbe_fld_s;
} ii_iprbe_u_t;


/************************************************************************
 *                                                                      *
 * Description:  There are 9 instances of this register, one per        *
 * actual widget in this implementation of Shub and Crossbow.           *
 * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
 * refers to Crossbow's internal space.                                 *
 * This register contains the state elements per widget that are        *
 * necessary to manage the PIO flow control on Crosstalk and on the     *
 * Router Network. See the PIO Flow Control chapter for a complete      *
 * description of this register                                         *
 * The SPUR_WR bit requires some explanation. When this register is     *
 * written, the new value of the C field is captured in an internal     *
 * register so the hardware can remember what the programmer wrote      *
 * into the credit counter. The SPUR_WR bit sets whenever the C field   *
 * increments above this stored value, which indicates that there       *
 * have been more responses received than requests sent. The SPUR_WR    *
 * bit cannot be cleared until a value is written to the IPRBx          *
 * register; the write will correct the C field and capture its new     *
 * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
 * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
 * .