shubio.h

该文件是rt_linux

 * number) are used to select one of these 7 registers. The Widget      *
 * number field is then derived from the W_NUM field for synthesizing   *
 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
 * are padded with zeros. Although the maximum Crosstalk space          *
 * addressable by the Shub is thus the lower 16 GBytes per widget       *
 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
 * space can be accessed.                                               *
 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
 * Window number) are used to select one of these 7 registers. The      *
 * Widget number field is then derived from the W_NUM field for         *
 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
 * field is used as Crosstalk[47], and remainder of the Crosstalk       *
 * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
 * Crosstalk space addressable by the Shub is thus the lower            *
 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
 * of this space can be accessed.                                       *
 *                                                                      *
 ************************************************************************/

typedef union ii_itte5_u {
	shubreg_t	ii_itte5_regval;
	struct  {
		shubreg_t	i_offset                  :	 5;
		shubreg_t       i_rsvd_1                  :      3;
		shubreg_t       i_w_num                   :      4;
		shubreg_t       i_iosp                    :      1;
		shubreg_t       i_rsvd                    :     51;
	} ii_itte5_fld_s;
} ii_itte5_u_t;


/************************************************************************
 *                                                                      *
 * Description:  There are seven instances of translation table entry   *
 * registers. Each register maps a Shub Big Window to a 48-bit          *
 * address on Crosstalk.                                                *
 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
 * number) are used to select one of these 7 registers. The Widget      *
 * number field is then derived from the W_NUM field for synthesizing   *
 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
 * are padded with zeros. Although the maximum Crosstalk space          *
 * addressable by the Shub is thus the lower 16 GBytes per widget       *
 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
 * space can be accessed.                                               *
 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
 * Window number) are used to select one of these 7 registers. The      *
 * Widget number field is then derived from the W_NUM field for         *
 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
 * field is used as Crosstalk[47], and remainder of the Crosstalk       *
 * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
 * Crosstalk space addressable by the Shub is thus the lower            *
 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
 * of this space can be accessed.                                       *
 *                                                                      *
 ************************************************************************/

typedef union ii_itte6_u {
	shubreg_t	ii_itte6_regval;
	struct  {
		shubreg_t	i_offset                  :	 5;
		shubreg_t       i_rsvd_1                  :      3;
		shubreg_t       i_w_num                   :      4;
		shubreg_t       i_iosp                    :      1;
		shubreg_t       i_rsvd                    :     51;
	} ii_itte6_fld_s;
} ii_itte6_u_t;


/************************************************************************
 *                                                                      *
 * Description:  There are seven instances of translation table entry   *
 * registers. Each register maps a Shub Big Window to a 48-bit          *
 * address on Crosstalk.                                                *
 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
 * number) are used to select one of these 7 registers. The Widget      *
 * number field is then derived from the W_NUM field for synthesizing   *
 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
 * are padded with zeros. Although the maximum Crosstalk space          *
 * addressable by the Shub is thus the lower 16 GBytes per widget       *
 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
 * space can be accessed.                                               *
 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
 * Window number) are used to select one of these 7 registers. The      *
 * Widget number field is then derived from the W_NUM field for         *
 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
 * field is used as Crosstalk[47], and remainder of the Crosstalk       *
 * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
 * Crosstalk space addressable by the SHub is thus the lower            *
 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
 * of this space can be accessed.                                       *
 *                                                                      *
 ************************************************************************/

typedef union ii_itte7_u {
	shubreg_t	ii_itte7_regval;
	struct  {
		shubreg_t	i_offset                  :	 5;
		shubreg_t	i_rsvd_1		  :	 3;
		shubreg_t       i_w_num                   :      4;
		shubreg_t       i_iosp                    :      1;
		shubreg_t       i_rsvd                    :     51;
	} ii_itte7_fld_s;
} ii_itte7_u_t;


/************************************************************************
 *                                                                      *
 * Description:  There are 9 instances of this register, one per        *
 * actual widget in this implementation of SHub and Crossbow.           *
 * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
 * refers to Crossbow's internal space.                                 *
 * This register contains the state elements per widget that are        *
 * necessary to manage the PIO flow control on Crosstalk and on the     *
 * Router Network. See the PIO Flow Control chapter for a complete      *
 * description of this register                                         *
 * The SPUR_WR bit requires some explanation. When this register is     *
 * written, the new value of the C field is captured in an internal     *
 * register so the hardware can remember what the programmer wrote      *
 * into the credit counter. The SPUR_WR bit sets whenever the C field   *
 * increments above this stored value, which indicates that there       *
 * have been more responses received than requests sent. The SPUR_WR    *
 * bit cannot be cleared until a value is written to the IPRBx          *
 * register; the write will correct the C field and capture its new     *
 * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
 * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
 * .                                                                    *
 *                                                                      *
 ************************************************************************/

typedef union ii_iprb0_u {
	shubreg_t	ii_iprb0_regval;
	struct  {
		shubreg_t	i_c                       :	 8;
		shubreg_t	i_na			  :	14;
		shubreg_t       i_rsvd_2                  :      2;
		shubreg_t	i_nb			  :	14;
		shubreg_t	i_rsvd_1		  :	 2;
		shubreg_t	i_m			  :	 2;
		shubreg_t	i_f			  :	 1;
		shubreg_t	i_of_cnt		  :	 5;
		shubreg_t	i_error			  :	 1;
		shubreg_t	i_rd_to			  :	 1;
		shubreg_t	i_spur_wr		  :	 1;
		shubreg_t	i_spur_rd		  :	 1;
		shubreg_t	i_rsvd			  :	11;
		shubreg_t	i_mult_err		  :	 1;
	} ii_iprb0_fld_s;
} ii_iprb0_u_t;


/************************************************************************
 *                                                                      *
 * Description:  There are 9 instances of this register, one per        *
 * actual widget in this implementation of SHub and Crossbow.           *
 * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
 * refers to Crossbow's internal space.                                 *
 * This register contains the state elements per widget that are        *
 * necessary to manage the PIO flow control on Crosstalk and on the     *
 * Router Network. See the PIO Flow Control chapter for a complete      *
 * description of this register                                         *
 * The SPUR_WR bit requires some explanation. When this register is     *
 * written, the new value of the C field is captured in an internal     *
 * register so the hardware can remember what the programmer wrote      *
 * into the credit counter. The SPUR_WR bit sets whenever the C field   *
 * increments above this stored value, which indicates that there       *
 * have been more responses received than requests sent. The SPUR_WR    *
 * bit cannot be cleared until a value is written to the IPRBx          *
 * register; the write will correct the C field and capture its new     *
 * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
 * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
 * .                                                                    *
 *                                                                      *
 ************************************************************************/

typedef union ii_iprb8_u {
	shubreg_t	ii_iprb8_regval;
	struct  {
		shubreg_t	i_c                       :	 8;
		shubreg_t	i_na			  :	14;
		shubreg_t       i_rsvd_2                  :      2;
		shubreg_t	i_nb			  :	14;
		shubreg_t       i_rsvd_1                  :      2;
		shubreg_t       i_m                       :      2;
		shubreg_t       i_f                       :      1;
		shubreg_t       i_of_cnt                  :      5;
		shubreg_t       i_error                   :      1;
		shubreg_t       i_rd_to                   :      1;
		shubreg_t       i_spur_wr                 :      1;
		shubreg_t	i_spur_rd		  :	 1;
		shubreg_t       i_rsvd                    :     11;
		shubreg_t	i_mult_err		  :	 1;
	} ii_iprb8_fld_s;
} ii_iprb8_u_t;


/************************************************************************
 *                                                                      *
 * Description:  There are 9 instances of this register, one per        *
 * actual widget in this implementation of SHub and Crossbow.           *
 * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
 * refers to Crossbow's internal space.                                 *
 * This register contains the state elements per widget that are        *
 * necessary to manage the PIO flow control on Crosstalk and on the     *
 * Router Network. See the PIO Flow Control chapter for a complete      *
 * description of this register                                         *
 * The SPUR_WR bit requires some explanation. When this register is     *
 * written, the new value of the C field is captured in an internal     *
 * register so the hardware can remember what the programmer wrote      *
 * into the credit counter. The SPUR_WR bit sets whenever the C field   *
 * increments above this stored value, which indicates that there       *
 * have been more responses received than requests sent. The SPUR_WR    *
 * bit cannot be cleared until a value is written to the IPRBx          *
 * register; the write will correct the C field and capture its new     *
 * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
 * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
 * .                                                                    *
 *                                                                      *
 ************************************************************************/

typedef union ii_iprb9_u {
	shubreg_t	ii_iprb9_regval;
	struct	{
		shubreg_t	i_c			  :	 8;
		shubreg_t	i_na			  :	14;
		shubreg_t	i_rsvd_2		  :	 2;
		shubreg_t	i_nb			  :	14;
		shubreg_t	i_rsvd_1		  :	 2;
		shubreg_t	i_m			  :	 2;
		shubreg_t	i_f			  :	 1;
		shubreg_t	i_of_cnt		  :	 5;
		shubreg_t	i_error			  :	 1;
		shubreg_t	i_rd_to			  :	 1;
		shubreg_t	i_spur_wr		  :	 1;
		shubreg_t	i_spur_rd		  :	 1;
		shubreg_t	i_rsvd			  :	11;
		shubreg_t	i_mult_err		  :	 1;
	} ii_iprb9_fld_s;
} ii_iprb9_u_t;


/************************************************************************
 *                                                                      *