init.c

该文件是rt_linux

                    *((USHORT *)(Addr)) = PhysicalAdrOtherPage;

                    /* Read data */
                    Addr = FBAddr + (BankNumHigh) * 64 * 1024 + PhysicalAdrHigh;
                    data = *((USHORT *)(Addr));
                    if(data == PhysicalAdrHigh) Done = 1;
                 }  /* if struct */
            }  /* for loop (k) */
         }  /* if struct */
      }  /* for loop (j) */
   }  /* for loop (i) */
}

USHORT
SiS_ChkBUSWidth_300(SiS_Private *SiS_Pr, ULONG FBAddress)
{
   PULONG  pVideoMemory;

   pVideoMemory = (PULONG)FBAddress;

   pVideoMemory[0] = 0x01234567L;
   pVideoMemory[1] = 0x456789ABL;
   pVideoMemory[2] = 0x89ABCDEFL;
   pVideoMemory[3] = 0xCDEF0123L;
   if (pVideoMemory[3]==0xCDEF0123L) {  /* Channel A 128bit */
     return(4);
   }
   if (pVideoMemory[1]==0x456789ABL) {  /* Channel B 64bit */
     return(2);
   }
   return(1);
}
#endif
/* ===============  SiS 300 dram sizing end    =============== */

/* ============  SiS 310/325 dram sizing begin  ============== */
#ifdef SIS315H

/* TW: Moved Get310DRAMType further down */

void
SiS_Delay15us(SiS_Private *SiS_Pr, ULONG ulMicrsoSec)
{
}

void
SiS_SDR_MRS(SiS_Private *SiS_Pr, )
{
   USHORT  data;

   data = SiS_GetReg1(SiS_Pr->SiS_P3c4,0x16);
   data &= 0x3F;          		        /* SR16 D7=0, D6=0 */
   SiS_SetReg1(SiS_Pr->SiS_P3c4,0x16,data);   	/* enable mode register set(MRS) low */
   SiS_Delay15us(SiS_Pr, 0x100);
   data |= 0x80;          		        /* SR16 D7=1, D6=0 */
   SiS_SetReg1(SiS_Pr->SiS_P3c4,0x16,data);   	/* enable mode register set(MRS) high */
   SiS_Delay15us(SiS_Pr, 0x100);
}

void
SiS_DDR_MRS(SiS_Private *SiS_Pr)
{
   USHORT  data;

   /* SR16 <- 1F,DF,2F,AF */

   /* enable DLL of DDR SD/SGRAM , SR16 D4=1 */
   data=SiS_GetReg1(SiS_Pr->SiS_P3c4,0x16);
   data &= 0x0F;
   data |= 0x10;
   SiS_SetReg1(SiS_Pr->SiS_P3c4,0x16,data);

   if (!(SiS_Pr->SiS_SR15[1][SiS_Pr->SiS_RAMType] & 0x10))
     data &= 0x0F;

   /* SR16 D7=1,D6=1 */
   data |= 0xC0;
   SiS_SetReg1(SiS_Pr->SiS_P3c4,0x16,data);
   
   /* SR16 D7=1,D6=0,D5=1,D4=0 */
   data &= 0x0F;
   data |= 0x20;
   SiS_SetReg1(SiS_Pr->SiS_P3c4,0x16,data);
   if (!(SiS_Pr->SiS_SR15[1][SiS_Pr->SiS_RAMType] & 0x10))
     data &= 0x0F;

   /* SR16 D7=1 */
   data |= 0x80;
   SiS_SetReg1(SiS_Pr->SiS_P3c4,0x16,data);
}

void
SiS_SetDRAMModeRegister(SiS_Private *SiS_Pr, UCHAR *ROMAddr, PSIS_HW_DEVICE_INFO HwDeviceExtension)
{
    if (SiS_Get310DRAMType(ROMAddr,HwDeviceExtension) < 2)
        SiS_SDR_MRS(SiS_Pr);
    else
        /* SR16 <- 0F,CF,0F,8F */
        SiS_DDR_MRS(SiS_Pr);
}

void
SiS_DisableRefresh(SiS_Private *SiS_Pr)
{
   SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x17,0xF8);
   SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x19,0x03);
}

void
SiS_EnableRefresh(SiS_Private *SiS_Pr, UCHAR *ROMAddr)
{
   SiS_SetReg1(SiS_Pr->SiS_P3c4,0x17,SiS_Pr->SiS_SR15[2][SiS_Pr->SiS_RAMType]);
   SiS_SetReg1(SiS_Pr->SiS_P3c4,0x19,SiS_Pr->SiS_SR15[4][SiS_Pr->SiS_RAMType]);
}

void
SiS_DisableChannelInterleaving(SiS_Private *SiS_Pr, int index,
                               USHORT SiS_DDRDRAM_TYPE[][5])
{
   USHORT  data;

   data=SiS_GetReg1(SiS_Pr->SiS_P3c4,0x15);
   data &= 0x1F;
   switch (SiS_DDRDRAM_TYPE[index][3])
   {
     case 64: data |= 0; 	break;
     case 32: data |= 0x20;	break;
     case 16: data |= 0x40;     break;
     case 4:  data |= 0x60;     break;
   }
   SiS_SetReg1(SiS_Pr->SiS_P3c4,0x15,data);
}

void
SiS_SetDRAMSizingType(SiS_Private *SiS_Pr, int index, USHORT DRAMTYPE_TABLE[][5])
{
   SiS_SetReg1(SiS_Pr->SiS_P3c4,0x13,DRAMTYPE_TABLE[index][4]);
   /* should delay 50 ns */
}

void
SiS_CheckBusWidth_310(SiS_Private *SiS_Pr, UCHAR *ROMAddress,ULONG FBAddress,
                      PSIS_HW_DEVICE_INFO HwDeviceExtension)
{
   USHORT  data;
   PULONG volatile pVideoMemory;

   pVideoMemory = (PULONG)FBAddress;
   if(SiS_Get310DRAMType(ROMAddress,HwDeviceExtension) < 2) {

     SiS_SetReg1(SiS_Pr->SiS_P3c4,0x13,0x00);
     SiS_SetReg1(SiS_Pr->SiS_P3c4,0x14,0x12);
     /* should delay */
     SiS_SDR_MRS(SiS_Pr);

     SiS_Pr->SiS_ChannelAB = 0;
     SiS_Pr->SiS_DataBusWidth = 128;
     pVideoMemory[0] = 0x01234567L;
     pVideoMemory[1] = 0x456789ABL;
     pVideoMemory[2] = 0x89ABCDEFL;
     pVideoMemory[3] = 0xCDEF0123L;
     pVideoMemory[4] = 0x55555555L;
     pVideoMemory[5] = 0x55555555L;
     pVideoMemory[6] = 0xFFFFFFFFL;
     pVideoMemory[7] = 0xFFFFFFFFL;
     if ((pVideoMemory[3]!=0xCDEF0123L) || (pVideoMemory[2] != 0x89ABCDEFL)) {
       /*Channel A 64Bit */
       SiS_Pr->SiS_DataBusWidth = 64;
       SiS_Pr->SiS_ChannelAB = 0;
       data=SiS_GetReg1(SiS_Pr->SiS_P3c4,0x14);
       SiS_SetReg1(SiS_Pr->SiS_P3c4,0x14,(USHORT)(data & 0xFD));
     }

     if ((pVideoMemory[1]!=0x456789ABL) || (pVideoMemory[0] != 0x01234567L)) {
       /*Channel B 64Bit */
       SiS_Pr->SiS_DataBusWidth = 64;
       SiS_Pr->SiS_ChannelAB = 1;
       data=SiS_GetReg1(SiS_Pr->SiS_P3c4,0x14);
       SiS_SetReg1(SiS_Pr->SiS_P3c4,0x14,(USHORT)((data&0xFD)|0x01));
     }
     return;

   } else {
     /* DDR Dual channel */
     SiS_SetReg1(SiS_Pr->SiS_P3c4,0x13,0x00);
     SiS_SetReg1(SiS_Pr->SiS_P3c4,0x14,0x02); /* Channel A, 64bit */
     /* should delay */
     SiS_DDR_MRS(SiS_Pr);

     SiS_Pr->SiS_ChannelAB = 0;
     SiS_Pr->SiS_DataBusWidth = 64;
     pVideoMemory[0] = 0x01234567L;
     pVideoMemory[1] = 0x456789ABL;
     pVideoMemory[2] = 0x89ABCDEFL;
     pVideoMemory[3] = 0xCDEF0123L;
     pVideoMemory[4] = 0x55555555L;
     pVideoMemory[5] = 0x55555555L;
     pVideoMemory[6] = 0xAAAAAAAAL;
     pVideoMemory[7] = 0xAAAAAAAAL;

     if (pVideoMemory[1] == 0x456789ABL) {
       if (pVideoMemory[0] == 0x01234567L) {
         /* Channel A 64bit */
         return;
       }
     } else {
       if (pVideoMemory[0] == 0x01234567L) {
         /* Channel A 32bit */
         SiS_Pr->SiS_DataBusWidth = 32;
         SiS_SetReg1(SiS_Pr->SiS_P3c4,0x14,0x00);
         return;
       }
     }

     SiS_SetReg1(SiS_Pr->SiS_P3c4,0x14,0x03); /* Channel B, 64bit */
     SiS_DDR_MRS(SiS_Pr);

     SiS_Pr->SiS_ChannelAB = 1;
     SiS_Pr->SiS_DataBusWidth = 64;
     pVideoMemory[0] = 0x01234567L;
     pVideoMemory[1] = 0x456789ABL;
     pVideoMemory[2] = 0x89ABCDEFL;
     pVideoMemory[3] = 0xCDEF0123L;
     pVideoMemory[4] = 0x55555555L;
     pVideoMemory[5] = 0x55555555L;
     pVideoMemory[6] = 0xAAAAAAAAL;
     pVideoMemory[7] = 0xAAAAAAAAL;
     if (pVideoMemory[1] == 0x456789ABL) {
       /* Channel B 64 */
       if (pVideoMemory[0] == 0x01234567L) {
         /* Channel B 64bit */
         return;
       } else {
         /* error */
       }
     } else {
       if (pVideoMemory[0] == 0x01234567L) {
         /* Channel B 32 */
         SiS_Pr->SiS_DataBusWidth = 32;
         SiS_SetReg1(SiS_Pr->SiS_P3c4,0x14,0x01);
       } else {
         /* error */
       }
     }
   }
}

int
SiS_SetRank(SiS_Private *SiS_Pr, int index,UCHAR RankNo,USHORT DRAMTYPE_TABLE[][5])
{
  USHORT  data;
  int RankSize;

  if ((RankNo==2)&&(DRAMTYPE_TABLE[index][0]==2))
         return 0;

  RankSize = DRAMTYPE_TABLE[index][3]/2 * SiS_Pr->SiS_DataBusWidth / 32;

  if (RankNo * RankSize <= 128) {
    data = 0;
    while((RankSize >>= 1) > 0) {
      data += 0x10;
    }
    data |= (RankNo - 1) << 2;
    data |= (SiS_Pr->SiS_DataBusWidth / 64) & 2;
    data |= SiS_Pr->SiS_ChannelAB;
    SiS_SetReg1(SiS_Pr->SiS_P3c4,0x14,data);
    /* should delay */
    SiS_SDR_MRS(SiS_Pr);
    return 1;
  } else
    return 0;
}

int
SiS_SetDDRChannel(SiS_Private *SiS_Pr, int index,UCHAR ChannelNo,
                  USHORT DRAMTYPE_TABLE[][5])
{
  USHORT  data;
  int RankSize;

  RankSize = DRAMTYPE_TABLE[index][3]/2 * SiS_Pr->SiS_DataBusWidth / 32;
  /* RankSize = DRAMTYPE_TABLE[index][3]; */
  if (ChannelNo * RankSize <= 128) {
    data = 0;
    while((RankSize >>= 1) > 0) {
      data += 0x10;
    }
    if(ChannelNo == 2) data |= 0x0C;
    data |= (SiS_Pr->SiS_DataBusWidth / 32) & 2;
    data |= SiS_Pr->SiS_ChannelAB;
    SiS_SetReg1(SiS_Pr->SiS_P3c4,0x14,data);
    /* should delay */
    SiS_DDR_MRS(SiS_Pr);
    return 1;
  } else
    return 0;
}

int
SiS_CheckColumn(SiS_Private *SiS_Pr, int