pci.c

该文件是rt_linux

	GT_REG_READ(PCI_0I_O_HIGH_DECODE_ADDRESS, &top);
	top = (top << 21);
	size = ((top - base) & 0xfffffff);
	size = size | 0x1fffff;
	return (size + 1);
}

/********************************************************************
* pci0GetMemory0Base - Return PCI0 Memory 0 Base Address.
* Inputs: N/A
* Returns: PCI0 Memory 0 Base Address.
*********************************************************************/

unsigned int pci0GetMemory0Base()
{
	unsigned int base;
	GT_REG_READ(PCI_0MEMORY0_LOW_DECODE_ADDRESS, &base);
	base = base << 21;
	return base;
}

/********************************************************************
* pci0GetMemory0Size - Return PCI0 Memory 0 Bar Size.
* Inputs: N/A
* Returns: PCI0 Memory 0 Bar Size.
*********************************************************************/

unsigned int pci0GetMemory0Size()
{
	unsigned int top, base, size;
	GT_REG_READ(PCI_0MEMORY0_LOW_DECODE_ADDRESS, &base);
	base = base << 21;
	GT_REG_READ(PCI_0MEMORY0_HIGH_DECODE_ADDRESS, &top);
	top = (top << 21);
	size = ((top - base) & 0xfffffff);
	size = size | 0x1fffff;
	return (size + 1);
}

/********************************************************************
* pci0GetMemory1Base - Return PCI0 Memory 1 Base Address.
* Inputs: N/A
* Returns: PCI0 Memory 1 Base Address.
*********************************************************************/

unsigned int pci0GetMemory1Base()
{
	unsigned int base;
	GT_REG_READ(PCI_0MEMORY1_LOW_DECODE_ADDRESS, &base);
	base = base << 21;
	return base;
}

/********************************************************************
* pci0GetMemory1Size - Return PCI0 Memory 1 Bar Size.
* Inputs: N/A
* Returns: PCI0 Memory 1 Bar Size.
*********************************************************************/

unsigned int pci0GetMemory1Size()
{
	unsigned int top, base, size;
	GT_REG_READ(PCI_0MEMORY1_LOW_DECODE_ADDRESS, &base);
	base = base << 21;
	GT_REG_READ(PCI_0MEMORY1_HIGH_DECODE_ADDRESS, &top);
	top = (top << 21);
	size = ((top - base) & 0xfffffff);
	size = size | 0x1fffff;
	return (size + 1);
}

/********************************************************************
* pci1GetIOspaceBase - Return PCI1 IO Base Address.
* Inputs: N/A
* Returns: PCI1 IO Base Address.
*********************************************************************/

unsigned int pci1GetIOspaceBase()
{
	unsigned int base;
	GT_REG_READ(PCI_1I_O_LOW_DECODE_ADDRESS, &base);
	base = base << 21;
	return base;
}

/********************************************************************
* pci1GetIOspaceSize - Return PCI1 IO Bar Size.
* Inputs: N/A
* Returns: PCI1 IO Bar Size.
*********************************************************************/

unsigned int pci1GetIOspaceSize()
{
	unsigned int top, base, size;
	GT_REG_READ(PCI_1I_O_LOW_DECODE_ADDRESS, &base);
	base = base << 21;
	GT_REG_READ(PCI_1I_O_HIGH_DECODE_ADDRESS, &top);
	top = (top << 21);
	size = ((top - base) & 0xfffffff);
	size = size | 0x1fffff;
	return (size + 1);
}

/********************************************************************
* pci1GetMemory0Base - Return PCI1 Memory 0 Base Address.
* Inputs: N/A
* Returns: PCI1 Memory 0 Base Address.
*********************************************************************/

unsigned int pci1GetMemory0Base()
{
	unsigned int base;
	GT_REG_READ(PCI_1MEMORY0_LOW_DECODE_ADDRESS, &base);
	base = base << 21;
	return base;
}

/********************************************************************
* pci1GetMemory0Size - Return PCI1 Memory 0 Bar Size.
* Inputs: N/A
* Returns: PCI1 Memory 0 Bar Size.
*********************************************************************/

unsigned int pci1GetMemory0Size()
{
	unsigned int top, base, size;
	GT_REG_READ(PCI_1MEMORY1_LOW_DECODE_ADDRESS, &base);
	base = base << 21;
	GT_REG_READ(PCI_1MEMORY1_HIGH_DECODE_ADDRESS, &top);
	top = (top << 21);
	size = ((top - base) & 0xfffffff);
	size = size | 0x1fffff;
	return (size + 1);
}

/********************************************************************
* pci1GetMemory1Base - Return PCI1 Memory 1 Base Address.
* Inputs: N/A
* Returns: PCI1 Memory 1 Base Address.
*********************************************************************/

unsigned int pci1GetMemory1Base()
{
	unsigned int base;
	GT_REG_READ(PCI_1MEMORY1_LOW_DECODE_ADDRESS, &base);
	base = base << 21;
	return base;
}

/********************************************************************
* pci1GetMemory1Size - Return PCI1 Memory 1 Bar Size.
* Inputs: N/A
* Returns: PCI1 Memory 1 Bar Size.
*********************************************************************/

unsigned int pci1GetMemory1Size()
{
	unsigned int top, base, size;
	GT_REG_READ(PCI_1MEMORY1_LOW_DECODE_ADDRESS, &base);
	base = base << 21;
	GT_REG_READ(PCI_1MEMORY1_HIGH_DECODE_ADDRESS, &top);
	top = (top << 21);
	size = ((top - base) & 0xfffffff);
	size = size | 0x1fffff;
	return (size + 1);
}

/********************************************************************
* pci0MapInternalRegSpace - Maps the internal registers memory space for the
*                           slave.
*                           Stays the same for all GT devices Disco include
* Inputs: base of pci0 internal register
*********************************************************************/

void pci0MapInternalRegSpace(unsigned int pci0InternalBase)
{
	pci0InternalBase = pci0InternalBase & 0xfffff000;
	pci0InternalBase =
	    pci0InternalBase |
	    (pci0ReadConfigReg
	     (PCI_0INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
	      SELF) & 0x00000fff);
	pci0WriteConfigReg
	    (PCI_0INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, SELF,
	     pci0InternalBase);
}

/********************************************************************
* pci1MapInternalRegSpace - Maps the internal registers memory space for the
*                           slave.
*                           Stays the same for all GT devices Disco include
* Inputs: base of pci1 internal register
*********************************************************************/

void pci1MapInternalRegSpace(unsigned int pci1InternalBase)
{
	pci1InternalBase = pci1InternalBase & 0xfffff000;
	pci1InternalBase =
	    pci1InternalBase |
	    (pci1ReadConfigReg
	     (PCI_0INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
	      SELF) & 0x00000fff);
	pci1WriteConfigReg
	    (PCI_0INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, SELF,
	     pci1InternalBase);
}

/********************************************************************
* pci0MapInternalRegIOSpace - Maps the internal registers IO space for the
*                             slave.
*                             Stays the same for all GT devices Disco include
* Inputs: base of pci0 internal io register
*********************************************************************/

void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase)
{
	pci0InternalBase = pci0InternalBase & 0xfffff000;
	pci0InternalBase =
	    pci0InternalBase |
	    (pci0ReadConfigReg
	     (PCI_0INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS,
	      0) & 0x00000fff);
	pci0WriteConfigReg(PCI_0INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS,
			   SELF, pci0InternalBase);
}

/********************************************************************
* pci0MapInternalRegIOSpace - Maps the internal registers IO space for the
*                             slave.
*                             Stays the same for all GT devices Disco include
* Inputs: base of pci1 internal io register
*********************************************************************/

void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase)
{
	pci1InternalBase = pci1InternalBase & 0xfffff000;
	pci1InternalBase =
	    pci1InternalBase |
	    (pci1ReadConfigReg
	     (PCI_0INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS,
	      SELF) & 0x00000fff);
	pci1WriteConfigReg(PCI_0INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS,
			   SELF, pci1InternalBase);
}

/********************************************************************
* pci0MapMemoryBanks0_1 - Maps PCI0 memory banks 0 and 1 for the slave.
*                         for Discovery we need two function: SCS0 & SCS1
*                         (instead of SCS[1:0])
* Inputs: base and size of pci0 dram
*********************************************************************/


void pci0MapMemoryBanks0_1(unsigned int pci0Dram0_1Base,
			   unsigned int pci0Dram0_1Size)
{
	pci0Dram0_1Base = pci0Dram0_1Base & 0xfffff000;
	pci0Dram0_1Base =
	    pci0Dram0_1Base |
	    (pci0ReadConfigReg(PCI_0SCS_1_0_BASE_ADDRESS, SELF) &
	     0x00000fff);
	pci0WriteConfigReg(PCI_0SCS_1_0_BASE_ADDRESS, SELF,
			   pci0Dram0_1Base);
	/* swapped Bar */
	pci0WriteConfigReg(PCI_0SWAPPED_SCS_1_0_BASE_ADDRESS, SELF,
			   pci0Dram0_1Base);
	if (pci0Dram0_1Size == 0)
		pci0Dram0_1Size++;
	GT_REG_WRITE(PCI_0SCS_1_0_BANK_SIZE, pci0Dram0_1Size - 1);
}

/********************************************************************
* pci1MapMemoryBanks0_1 - Maps PCI1 memory banks 0 and 1 for the slave.
*                         for Discovery we need two function: SCS0 & SCS1
*                         (instead of SCS[1:0])
* Inputs: base and size of pci1 dram
*********************************************************************/

void pci1MapMemoryBanks0_1(unsigned int pci1Dram0_1Base,
			   unsigned int pci1Dram0_1Size)
{
	pci1Dram0_1Base = pci1Dram0_1Base & 0xfffff000;
	pci1Dram0_1Base =
	    pci1Dram0_1Base |
	    (pci1ReadConfigReg(PCI_0SCS_1_0_BASE_ADDRESS, SELF) &
	     0x00000fff);
	pci1WriteConfigReg(PCI_0SCS_1_0_BASE_ADDRESS, SELF,
			   pci1Dram0_1Base);
	/* swapped Bar */
	pci1WriteConfigReg(PCI_0SWAPPED_SCS_1_0_BASE_ADDRESS, SELF,
			   pci1Dram0_1Base);
	if (pci1Dram0_1Size == 0)
		pci1Dram0_1Size++;
	GT_REG_WRITE(PCI_1SCS_1_0_BANK_SIZE, pci1Dram0_1Size - 1);
}

/********************************************************************
* pci0MapMemoryBanks2_3 - Maps PCI0 memory banks 2 and 3 for the slave.
*                         for Discovery we need two function: SCS2 & SCS3
*                         (instead of SCS[3:2])
* Inputs: base and size of pci0 dram
*********************************************************************/

void pci0MapMemoryBanks2_3(unsigned int pci0Dram2_3Base,
			   unsigned int pci0Dram2_3Size)
{
	pci0Dram2_3Base = pci0Dram2_3Base & 0xfffff000;
	pci0Dram2_3Base =
	    pci0Dram2_3Base |
	    (pci0ReadConfigReg(PCI_0SCS_3_2_BASE_ADDRESS, SELF) &
	     0x00000fff);
	pci0WriteConfigReg(PCI_0SCS_3_2_BASE_ADDRESS, SELF,
			   pci0Dram2_3Base);
	/* swapped Bar */
	pci0WriteConfigReg(PCI_0SWAPPED_SCS_3_2_BASE_ADDRESS, SELF,
			   pci0Dram2_3Base);
	if (pci0Dram2_3Size == 0)
		pci0Dram2_3Size++;
	GT_REG_WRITE(PCI_0SCS_3_2_BANK_SIZE, pci0Dram2_3Size - 1);
}

/********************************************************************
* pci1MapMemoryBanks2_3 - Maps PCI1 memory banks 2 and 3 for the slave.
*                         for Discovery we need two function: SCS2 & SCS3
*                         (instead of SCS[3:2])
* Inputs: base and size of pci1 dram
*********************************************************************/

void pci1MapMemoryBanks2_3(unsigned int pci1Dram2_3Base,
			   unsigned int pci1Dram2_3Size)
{
	pci1Dram2_3Base = pci1Dram2_3Base & 0xfffff000;
	pci1Dram2_3Base =
	    pci1Dram2_3Base |
	    (pci1ReadConfigReg(PCI_0SCS_3_2_BASE_ADDRESS, SELF) &
	     0x00000fff);
	pci1WriteConfigReg(PCI_0SCS_3_2_BASE_ADDRESS, SELF,
			   pci1Dram2_3Base);
	/* swapped Bar */
	pci1WriteConfigReg(PCI_0SWAPPED_SCS_3_2_BASE_ADDRESS, SELF,
			   pci1Dram2_3Base);
	if (pci1Dram2_3Size == 0)
		pci1Dram2_3Size++;
	GT_REG_WRITE(PCI_1SCS_3_2_BANK_SIZE, pci1Dram2_3Size - 1);
}

/********************************************************************
* pci0MapDevices0_1and2MemorySpace - Maps PCI0 devices 0,1 and 2 memory spaces
*                                    for the slave.
*                                    For the Discovery there are 3 separate
*                                    fucnction's
* Inputs: base and lengthof pci0 devises012
*********************************************************************/


void pci0MapDevices0_1and2MemorySpace(unsigned int pci0Dev012Base,
				      unsigned int pci0Dev012Length)
{
	pci0Dev012Base = pci0Dev012Base & 0xfffff000;
	pci0Dev012Base =
	    pci0Dev012Base |
	    (pci0ReadConfigReg(PCI_0CS_2_0_BASE_ADDRESS, SELF) &
	     0x00000fff);
	pci0WriteConfigReg(PCI_0CS_2_0_BASE_ADDRESS, SELF, pci0Dev012Base);
	if (pci0Dev012Length == 0)
		pci0Dev012Length++;
	GT_REG_WRITE(PCI_0CS_2_0_BANK_SIZE, pci0Dev012Length - 1);
}

/********************************************************************
* pci1MapDevices0_1and2MemorySpace - Maps PCI1 devices 0,1 and 2 memory spaces
*                                    for the slave.
*                                    For the Discovery there are 3 separate
*                                    fucnction's
* Inputs: base and lengthof pci1 devises012
*********************************************************************/

void pci1MapDevices0_1and2MemorySpace(unsigned int pci1Dev012Base,
				      unsigned int pci1Dev012Length)
{
	pci1Dev012Base = pci1Dev012Base & 0xfffff000;
	pci1Dev012Base =
	    pci1Dev012Base |
	    (pci1ReadConfigReg(PCI_0CS_2_0_BASE_ADDRESS, SELF) &
	     0x00000fff);
	pci1WriteConfigReg(PCI_0CS_2_0_BASE_ADDRESS, SELF, pci1Dev012Base);
	if (pci1Dev012Length == 0)
		pci1Dev012Length++;
	GT_REG_WRITE(PCI_1CS_2_0_BANK_SIZE, pci1Dev012Length - 1);
}

/********************************************************************
* pci0MapDevices3andBootMemorySpace - Maps PCI0 devices 3 and boot memory
*                                     spaces for the slave.
*                                     For the Discovery there are 2 separate
*                                     fucnction's
* Inputs: base and length of pci0 device3/ boot
*********************************************************************/

void pci0MapDevices3andBootMemorySpace(unsigned int pci0Dev3andBootBase,
				       unsigned int pci0Dev3andBootLength)
{
	pci0Dev3andBootBase = pci0Dev3andBootBase & 0xfffff000;
	pci0Dev3andBootBase =
	    pci0Dev3andBootBase |
	    (pci0ReadConfigReg(PCI_0CS_3_BOOTCS_BASE_ADDRESS, SELF) &
	     0x00000fff);
	pci0WriteConfigReg(PCI_0CS_3_BOOTCS_BASE_ADDRESS, SELF,
			   pci0Dev3andBootBase);
	/* swapped Bar */
	pci0WriteConfigReg(PCI_0SWAPPED_CS_3_BOOTCS_BASE_ADDRESS, SELF,
			   pci0Dev3andBootBase);
	if (pci0Dev3andBootLength == 0)
		pci0Dev3andBootLength++;
	GT_REG_WRITE(PCI_0CS_3_BOOTCS_BANK_SIZE,
		     pci0Dev3andBootLength - 1);
}

/********************************************************************
* pci1MapDevices3andBootMemorySpace - Maps PCI1 devices 3 and boot memory
*                                     spaces for the slave.
*                                     For the Discovery there are 2 separate
*                                     fucnction's
* Inputs: base and length of pci1 device3/ boot
*********************************************************************/

void pci1MapDevices3andBootMemorySpace(unsigned int pci1Dev3andBootBase,
				       unsigned int pci1Dev3andBootLength)
{
	pci1Dev3andBootBase = pci1Dev3andBootBase & 0xfffff000;
	pci1Dev3andBootBase =
	    pci1Dev3andBootBase |
	    (pci1ReadConfigReg(PCI_0CS_3_BOOTCS_BASE_ADDRESS, SELF) &
	     0x00000fff);
	pci1WriteConfigReg(PCI_0CS_3_BOOTCS_BASE_ADDRESS, SELF,
			   pci1Dev3andBootBase);
	/* swapped Bar */
	pci1WriteConfigReg(PCI_0SWAPPED_CS_3_BOOTCS_BASE_ADDRESS, SELF,
			   pci1Dev3andBootBase);
	if (pci1Dev3andBootLength == 0)
		pci1Dev3andBootLength++;
	GT_REG_WRITE(PCI_1CS_3_BOOTCS_BANK_SIZE,
		     pci1Dev3andBootLength - 1);
}