pci.c

该文件是rt_linux

			} else {
				if (pci1ArrayPointer->bar4Type == 0)	/* memory space */
					memSize =
					    ~(memSize & 0xfffffff0) + 1;
				else	/* IO space */
					memSize =
					    ~(memSize & 0xfffffffc) + 1;
				pci1ArrayPointer->bar4Size = memSize;
			}
			pci1WriteConfigReg(BAR4, device, memBaseAddress);
			/* BAR5 parameters */
			memBaseAddress = pci1ReadConfigReg(BAR5, device);
			pci1ArrayPointer->bar5Type = memBaseAddress & 1;
			pci1ArrayPointer->bar5Base =
			    memBaseAddress & 0xfffff000;
			pci1WriteConfigReg(BAR5, device, 0xffffffff);
			memSize = pci1ReadConfigReg(BAR5, device);
			if (memSize == 0) {	/* case of an empty BAR */
				pci1ArrayPointer->bar5Size = 0;
			} else {
				if (pci1ArrayPointer->bar5Type == 0)	/* memory space */
					memSize =
					    ~(memSize & 0xfffffff0) + 1;
				else	/* IO space */
					memSize =
					    ~(memSize & 0xfffffffc) + 1;
				pci1ArrayPointer->bar5Size = memSize;
			}
			pci1WriteConfigReg(BAR5, device, memBaseAddress);
			/* End of BARs Detection. */

			classCode = ((classCode & 0xff000000) >> 24);
			switch (classCode) {
			case 0x0:
				strcpy(pci1ArrayPointer->type,
				       "Old generation device");
				break;
			case 0x1:
				strcpy(pci1ArrayPointer->type,
				       "Mass storage controller");
				break;
			case 0x2:
				strcpy(pci1ArrayPointer->type,
				       "Network controller");
				break;
			case 0x3:
				strcpy(pci1ArrayPointer->type,
				       "Display controller");
				break;
			case 0x4:
				strcpy(pci1ArrayPointer->type,
				       "Multimedia device");
				break;
			case 0x5:
				strcpy(pci1ArrayPointer->type,
				       "Memory controller");
				break;
			case 0x6:
				strcpy(pci1ArrayPointer->type,
				       "Bridge Device");
				break;
			case 0x7:
				strcpy(pci1ArrayPointer->type,
				       "Simple Communication controllers");
				break;
			case 0x8:
				strcpy(pci1ArrayPointer->type,
				       "Base system peripherals");
				break;
			case 0x9:
				strcpy(pci1ArrayPointer->type,
				       "Input Devices");
				break;
			case 0xa:
				strcpy(pci1ArrayPointer->type,
				       "Docking stations");
				break;
			case 0xb:
				strcpy(pci1ArrayPointer->type,
				       "Processors");
				break;
			case 0xc:
				strcpy(pci1ArrayPointer->type,
				       "Serial bus controllers");
				break;
			case 0xd:
				strcpy(pci1ArrayPointer->type,
				       "Wireless controllers");
				break;
			case 0xe:
				strcpy(pci1ArrayPointer->type,
				       "Intelligent I/O controllers");
				break;
			case 0xf:
				strcpy(pci1ArrayPointer->type,
				       "Satellite communication controllers");
				break;
			case 0x10:
				strcpy(pci1ArrayPointer->type,
				       "Encryption/Decryption controllers");
				break;
			case 0x11:
				strcpy(pci1ArrayPointer->type,
				       "Data acquisition and signal processing controllers");
				break;
			}
			arrayCounter++;	/* point to the next element in the Array. */
			if (arrayCounter == numberOfElment)
				return;	/* When the Array is fully used, return. */
			/* Else, points to next free Element. */
			pci1ArrayPointer = &pci1Detect[arrayCounter];
		}
	}
	pci1ArrayPointer->deviceNum = 0;	/* 0 => End of List */
}

/********************************************************************
* pci0WriteConfigReg - Write to a PCI configuration register
*                    - Make sure the GT is configured as a master before
*                      writingto another device on the PCI.
*                    - The function takes care of Big/Little endian conversion.
* Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec
*                   (or any other PCI device spec)
*           pciDevNum: The device number needs to be addressed.
*
*  Configuration Address 0xCF8:
*
*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
*  |congif|Reserved|  Bus |Device|Function|Register|00|
*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
*
*********************************************************************/

void pci0WriteConfigReg(unsigned int regOffset, unsigned int pciDevNum,
			unsigned int data)
{
	unsigned int DataForRegCf8;
	unsigned int functionNum;

	functionNum = regOffset & 0x00000700;
	pciDevNum = pciDevNum << 11;
	regOffset = regOffset & 0x0fffffff;
	DataForRegCf8 = (regOffset | pciDevNum | functionNum) | BIT31;
	GT_REG_WRITE(PCI_0CONFIGURATION_ADDRESS, DataForRegCf8);
	if (pciDevNum == SELF) {	/* This board */
		GT_REG_WRITE(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
			     data);
	} else {		/* configuration Transaction over the pci. */

		/* The PCI is working in LE Mode So it swap the Data. */
		GT_REG_WRITE(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
			     WORDSWAP(data));
	}
}

/********************************************************************
* pci1WriteConfigReg - Write to a PCI configuration register
*                   - Make sure the GT is configured as a master before writing
*                     to another device on the PCI.
*                   - The function takes care of Big/Little endian conversion.
* Inputs:   unsigned int regOffset: The register offset as it apears in the
*           GT spec (or any other PCI device spec)
*           pciDevNum: The device number needs to be addressed.
*
*  Configuration Address 0xCF8:
*
*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
*  |congif|Reserved|  Bus |Device|Function|Register|00|
*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
*
*********************************************************************/

void pci1WriteConfigReg(unsigned int regOffset, unsigned int pciDevNum,
			unsigned int data)
{
	unsigned int DataForRegCf8;
	unsigned int functionNum;

	functionNum = regOffset & 0x00000700;
	pciDevNum = pciDevNum << 11;
	regOffset = regOffset & 0x0fffffff;
	if (pciDevNum == SELF) {	/* This board */
		/* when configurating our own PCI 1 L-unit the access is through
		   the PCI 0 interface with reg number = reg number + 0x80 */
		DataForRegCf8 =
		    (regOffset | pciDevNum | functionNum | 0x80) | BIT31;
		GT_REG_WRITE(PCI_0CONFIGURATION_ADDRESS, DataForRegCf8);
	} else {
		DataForRegCf8 =
		    (regOffset | pciDevNum | functionNum) | BIT31;
		GT_REG_WRITE(PCI_1CONFIGURATION_ADDRESS, DataForRegCf8);
	}
	if (pciDevNum == SELF) {	/* This board */
		GT_REG_WRITE(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
			     data);
	} else {
		GT_REG_WRITE(PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER,
			     WORDSWAP(data));
	}
}

/********************************************************************
* pci0ReadConfigReg  - Read from a PCI0 configuration register
*                    - Make sure the GT is configured as a master before
*                      reading from another device on the PCI.
*                   - The function takes care of Big/Little endian conversion.
* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
*                        spec)
*           pciDevNum: The device number needs to be addressed.
* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
*                 cause register to make sure the data is valid
*
*  Configuration Address 0xCF8:
*
*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
*  |congif|Reserved|  Bus |Device|Function|Register|00|
*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
*
*********************************************************************/

unsigned int pci0ReadConfigReg(unsigned int regOffset,
			       unsigned int pciDevNum)
{
	unsigned int DataForRegCf8;
	unsigned int data;
	unsigned int functionNum;

	functionNum = regOffset & 0x00000700;
	pciDevNum = pciDevNum << 11;
	regOffset = regOffset & 0x0fffffff;
	DataForRegCf8 = (regOffset | pciDevNum | functionNum) | BIT31;
	GT_REG_WRITE(PCI_0CONFIGURATION_ADDRESS, DataForRegCf8);
	if (pciDevNum == SELF) {	/* This board */
		GT_REG_READ(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
			    &data);
		return data;
	} else {		/* The PCI is working in LE Mode So it swap the Data. */

		GT_REG_READ(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
			    &data);
		return WORDSWAP(data);
	}
}

/********************************************************************
* pci1ReadConfigReg  - Read from a PCI1 configuration register
*                    - Make sure the GT is configured as a master before
*                      reading from another device on the PCI.
*                   - The function takes care of Big/Little endian conversion.
* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
*                        spec)
*           pciDevNum: The device number needs to be addressed.
* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
*                 cause register to make sure the data is valid
*
*  Configuration Address 0xCF8:
*
*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
*  |congif|Reserved|  Bus |Device|Function|Register|00|
*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
*
*********************************************************************/

unsigned int pci1ReadConfigReg(unsigned int regOffset,
			       unsigned int pciDevNum)
{
	unsigned int DataForRegCf8;
	unsigned int data;
	unsigned int functionNum;

	functionNum = regOffset & 0x00000700;
	pciDevNum = pciDevNum << 11;
	regOffset = regOffset & 0x0fffffff;
	if (pciDevNum == SELF) {	/* This board */
		/* when configurating our own PCI 1 L-unit the access is through
		   the PCI 0 interface with reg number = reg number + 0x80 */
		DataForRegCf8 =
		    (regOffset | pciDevNum | functionNum | 0x80) | BIT31;
		GT_REG_WRITE(PCI_0CONFIGURATION_ADDRESS, DataForRegCf8);
	} else {
		DataForRegCf8 =
		    (regOffset | pciDevNum | functionNum) | BIT31;
		GT_REG_WRITE(PCI_1CONFIGURATION_ADDRESS, DataForRegCf8);
	}
	if (pciDevNum == SELF) {	/* This board */
		GT_REG_READ(PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
			    &data);
		return data;
	} else {
		GT_REG_READ(PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER,
			    &data);
		return WORDSWAP(data);
	}
}

/********************************************************************
* pci0MapIOspace - Maps PCI0 IO space for the master.
* Inputs: base and length of pci0Io
*********************************************************************/

void pci0MapIOspace(unsigned int pci0IoBase, unsigned int pci0IoLength)
{
	unsigned int pci0IoTop =
	    (unsigned int) (pci0IoBase + pci0IoLength);

	if (pci0IoLength == 0)
		pci0IoTop++;

	pci0IoBase = (unsigned int) (pci0IoBase >> 21);
	pci0IoTop = (unsigned int) (((pci0IoTop - 1) & 0x0fffffff) >> 21);
	GT_REG_WRITE(PCI_0I_O_LOW_DECODE_ADDRESS, pci0IoBase);
	GT_REG_WRITE(PCI_0I_O_HIGH_DECODE_ADDRESS, pci0IoTop);
}

/********************************************************************
* pci1MapIOspace - Maps PCI1 IO space for the master.
* Inputs: base and length of pci1Io
*********************************************************************/

void pci1MapIOspace(unsigned int pci1IoBase, unsigned int pci1IoLength)
{
	unsigned int pci1IoTop =
	    (unsigned int) (pci1IoBase + pci1IoLength);

	if (pci1IoLength == 0)
		pci1IoTop++;

	pci1IoBase = (unsigned int) (pci1IoBase >> 21);
	pci1IoTop = (unsigned int) (((pci1IoTop - 1) & 0x0fffffff) >> 21);
	GT_REG_WRITE(PCI_1I_O_LOW_DECODE_ADDRESS, pci1IoBase);
	GT_REG_WRITE(PCI_1I_O_HIGH_DECODE_ADDRESS, pci1IoTop);
}

/********************************************************************
* pci0MapMemory0space - Maps PCI0 memory0 space for the master.
* Inputs: base and length of pci0Mem0
*********************************************************************/


void pci0MapMemory0space(unsigned int pci0Mem0Base,
			 unsigned int pci0Mem0Length)
{
	unsigned int pci0Mem0Top = pci0Mem0Base + pci0Mem0Length;

	if (pci0Mem0Length == 0)
		pci0Mem0Top++;

	pci0Mem0Base = pci0Mem0Base >> 21;
	pci0Mem0Top = ((pci0Mem0Top - 1) & 0x0fffffff) >> 21;
	GT_REG_WRITE(PCI_0MEMORY0_LOW_DECODE_ADDRESS, pci0Mem0Base);
	GT_REG_WRITE(PCI_0MEMORY0_HIGH_DECODE_ADDRESS, pci0Mem0Top);
}

/********************************************************************
* pci1MapMemory0space - Maps PCI1 memory0 space for the master.
* Inputs: base and length of pci1Mem0
*********************************************************************/

void pci1MapMemory0space(unsigned int pci1Mem0Base,
			 unsigned int pci1Mem0Length)
{
	unsigned int pci1Mem0Top = pci1Mem0Base + pci1Mem0Length;

	if (pci1Mem0Length == 0)
		pci1Mem0Top++;

	pci1Mem0Base = pci1Mem0Base >> 21;
	pci1Mem0Top = ((pci1Mem0Top - 1) & 0x0fffffff) >> 21;
	GT_REG_WRITE(PCI_1MEMORY0_LOW_DECODE_ADDRESS, pci1Mem0Base);
	GT_REG_WRITE(PCI_1MEMORY0_HIGH_DECODE_ADDRESS, pci1Mem0Top);
}

/********************************************************************
* pci0MapMemory1space - Maps PCI0 memory1 space for the master.
* Inputs: base and length of pci0Mem1
*********************************************************************/

void pci0MapMemory1space(unsigned int pci0Mem1Base,
			 unsigned int pci0Mem1Length)
{
	unsigned int pci0Mem1Top = pci0Mem1Base + pci0Mem1Length;

	if (pci0Mem1Length == 0)
		pci0Mem1Top++;

	pci0Mem1Base = pci0Mem1Base >> 21;
	pci0Mem1Top = ((pci0Mem1Top - 1) & 0x0fffffff) >> 21;
	GT_REG_WRITE(PCI_0MEMORY1_LOW_DECODE_ADDRESS, pci0Mem1Base);
	GT_REG_WRITE(PCI_0MEMORY1_HIGH_DECODE_ADDRESS, pci0Mem1Top);
#ifndef PROM
	DBG(KERN_INFO "pci0Mem1Base %x\n", pci0Mem1Base);
	DBG(KERN_INFO "pci0Mem1Top %x\n", pci0Mem1Top);
	GT_REG_READ(PCI_0MEMORY0_ADDRESS_REMAP, &pci0Mem1Base);
	DBG(KERN_INFO "Mem 0/0 remap %x\n", pci0Mem1Base);
	GT_REG_READ(PCI_0MEMORY1_ADDRESS_REMAP, &pci0Mem1Base);
	DBG(KERN_INFO "Mem 0/1 remap %x\n", pci0Mem1Base);
	GT_REG_WRITE(PCI_0MEMORY1_ADDRESS_REMAP, 0x500);
	GT_REG_READ(PCI_0MEMORY1_ADDRESS_REMAP, &pci0Mem1Base);
	DBG(KERN_INFO "Mem 0/1 remapped %x\n", pci0Mem1Base);
#endif
}

/********************************************************************
* pci1MapMemory1space - Maps PCI1 memory1 space for the master.
* Inputs: base and length of pci1Mem1
*********************************************************************/

void pci1MapMemory1space(unsigned int pci1Mem1Base,
			 unsigned int pci1Mem1Length)
{
	unsigned int pci1Mem1Top = pci1Mem1Base + pci1Mem1Length;

	if (pci1Mem1Length == 0)
		pci1Mem1Top++;

	pci1Mem1Base = pci1Mem1Base >> 21;
	pci1Mem1Top = ((pci1Mem1Top - 1) & 0x0fffffff) >> 21;
	GT_REG_WRITE(PCI_1MEMORY1_LOW_DECODE_ADDRESS, pci1Mem1Base);
	GT_REG_WRITE(PCI_1MEMORY1_HIGH_DECODE_ADDRESS, pci1Mem1Top);
}

/********************************************************************
* pci0GetIOspaceBase - Return PCI0 IO Base Address.
* Inputs: N/A
* Returns: PCI0 IO Base Address.
*********************************************************************/

unsigned int pci0GetIOspaceBase()
{
	unsigned int base;
	GT_REG_READ(PCI_0I_O_LOW_DECODE_ADDRESS, &base);
	base = base << 21;
	return base;
}

/********************************************************************
* pci0GetIOspaceSize - Return PCI0 IO Bar Size.
* Inputs: N/A
* Returns: PCI0 IO Bar Size.
*********************************************************************/

unsigned int pci0GetIOspaceSize()
{
	unsigned int top, base, size;
	GT_REG_READ(PCI_0I_O_LOW_DECODE_ADDRESS, &base);
	base = base << 21;