pci.c

该文件是rt_linux

/* PCI.c - PCI functions */

/* Copyright - Galileo technology. */

#ifdef __linux__
#include <asm/galileo-boards/evb64120A/core.h>
#include <asm/galileo-boards/evb64120A/pci.h>
#ifndef PROM
#include <linux/kernel.h>
#endif

#undef PCI_DEBUG

#ifdef PCI_DEBUG
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif

#else
#include "core.h"
#include "pci.h"
#include <string.h>
#endif

/********************************************************************
* pci0ScanDevices   - This function scan PCI0 bus, if found any device on
*                     this bus it interrogate the Device for the information
*                     it can discover.
*                     The fields with all information are the following:
*    char            type[20];
*    unsigned int    deviceNum;
*    unsigned int    venID;
*    unsigned int    deviceID;
*    unsigned int    bar0Base;
*    unsigned int    bar0Size;
*    unsigned int    bar1Base;
*    unsigned int    bar1Size;
*    unsigned int    bar2Base;
*    unsigned int    bar2Size;
*    unsigned int    bar3Base;
*    unsigned int    bar3Size;
*    unsigned int    bar4Base;
*    unsigned int    bar4Size;
*    unsigned int    bar5Base;
*    unsigned int    bar5Size;
*
* Inputs:   PCI0_DEVICE* pci0Detect - Pointer to an array of STRUCT PCI0_DEVICE.
*           unsigned int numberOfElment - The PCI0_DEVICE Array length.
* Output:   None.
*********************************************************************/

void pci0ScanDevices(PCI_DEVICE * pci0Detect, unsigned int numberOfElment)
{
	PCI_DEVICE *pci0ArrayPointer = pci0Detect;
	unsigned int id;	/* PCI Configuration register 0x0. */
	unsigned int device;	/* device`s Counter. */
	unsigned int classCode;	/* PCI Configuration register 0x8 */
	unsigned int arrayCounter = 0;
	unsigned int memBaseAddress;
	unsigned int memSize;
	unsigned int c18RegValue;

	PCI0_MASTER_ENABLE(SELF);
	/* According to PCI REV 2.1 MAX agents on the bus are -21- */
	for (device = 6; device < 8; device++) {
		id = pci0ReadConfigReg(PCI_0DEVICE_AND_VENDOR_ID, device);
		GT_REG_READ(INTERRUPT_CAUSE_REGISTER, &c18RegValue);
		/* Clearing bit 18 of in the Cause Register 0xc18 by writting 0. */
		GT_REG_WRITE(INTERRUPT_CAUSE_REGISTER,
			     c18RegValue & 0xfffbffff);
		if ((id != 0xffffffff) && !(c18RegValue & 0x40000)) {
			classCode =
			    pci0ReadConfigReg
			    (PCI_0CLASS_CODE_AND_REVISION_ID, device);
			pci0ArrayPointer->deviceNum = device;
			pci0ArrayPointer->venID = (id & 0xffff);
			pci0ArrayPointer->deviceID =
			    ((id & 0xffff0000) >> 16);
			DBG("\nrr: venID %x devID %x\n",
			    pci0ArrayPointer->venID,
			    pci0ArrayPointer->deviceID);
			DBG("rr: device found %x\n",
			    pci0ArrayPointer->deviceNum);
			/* BAR0 parameters */
			memBaseAddress = pci0ReadConfigReg(BAR0, device);
			pci0ArrayPointer->bar0Type = memBaseAddress & 1;
			pci0ArrayPointer->bar0Base =
			    memBaseAddress & 0xfffff000;
			pci0WriteConfigReg(BAR0, device, 0xffffffff);
			memSize = pci0ReadConfigReg(BAR0, device);
			if (memSize == 0) {	/* case of an empty BAR */
				pci0ArrayPointer->bar0Size = 0;
			} else {
				if (pci0ArrayPointer->bar0Type == 0)	/* memory space */
					memSize =
					    ~(memSize & 0xfffffff0) + 1;
				else	/* IO space */
					memSize =
					    ~(memSize & 0xfffffffc) + 1;
				pci0ArrayPointer->bar0Size = memSize;
			}
			DBG("rr: device BAR0 size %x\n", memSize);
			DBG("rr: device BAR0 address %x\n",
			    memBaseAddress);
			pci0WriteConfigReg(BAR0, device, memBaseAddress);
			/* BAR1 parameters */
			memBaseAddress = pci0ReadConfigReg(BAR1, device);
			pci0ArrayPointer->bar1Type = memBaseAddress & 1;
			pci0ArrayPointer->bar1Base =
			    memBaseAddress & 0xfffff000;
			pci0WriteConfigReg(BAR1, device, 0xffffffff);
			memSize = pci0ReadConfigReg(BAR1, device);
			if (memSize == 0) {	/* case of an empty BAR */
				pci0ArrayPointer->bar1Size = 0;
			} else {
				if (pci0ArrayPointer->bar1Type == 0)	/* memory space */
					memSize =
					    ~(memSize & 0xfffffff0) + 1;
				else	/* IO space */
					memSize =
					    ~(memSize & 0xfffffffc) + 1;
				pci0ArrayPointer->bar1Size = memSize;
			}
			DBG("rr: device BAR1 size %x\n", memSize);
			DBG("rr: device BAR1 address %x\n",
			    memBaseAddress);
			pci0WriteConfigReg(BAR1, device, memBaseAddress);
			/* BAR2 parameters */
			memBaseAddress = pci0ReadConfigReg(BAR2, device);
			pci0ArrayPointer->bar2Type = memBaseAddress & 1;
			pci0ArrayPointer->bar2Base =
			    memBaseAddress & 0xfffff000;
			pci0WriteConfigReg(BAR2, device, 0xffffffff);
			memSize = pci0ReadConfigReg(BAR2, device);
			if (memSize == 0) {	/* case of an empty BAR */
				pci0ArrayPointer->bar2Size = 0;
			} else {
				if (pci0ArrayPointer->bar2Type == 0)	/* memory space */
					memSize =
					    ~(memSize & 0xfffffff0) + 1;
				else	/* IO space */
					memSize =
					    ~(memSize & 0xfffffffc) + 1;
				pci0ArrayPointer->bar2Size = memSize;
			}
			DBG("rr: device BAR2 size %x\n", memSize);
			DBG("rr: device BAR2 address %x\n",
			    memBaseAddress);
			pci0WriteConfigReg(BAR2, device, memBaseAddress);
			/* BAR3 parameters */
			memBaseAddress = pci0ReadConfigReg(BAR3, device);
			pci0ArrayPointer->bar3Type = memBaseAddress & 1;
			pci0ArrayPointer->bar3Base =
			    memBaseAddress & 0xfffff000;
			pci0WriteConfigReg(BAR3, device, 0xffffffff);
			memSize = pci0ReadConfigReg(BAR3, device);
			if (memSize == 0) {	/* case of an empty BAR */
				pci0ArrayPointer->bar3Size = 0;
			} else {
				if (pci0ArrayPointer->bar3Type == 0)	/* memory space */
					memSize =
					    ~(memSize & 0xfffffff0) + 1;
				else	/* IO space */
					memSize =
					    ~(memSize & 0xfffffffc) + 1;
				pci0ArrayPointer->bar3Size = memSize;
			}
			DBG("rr: device BAR3 size %x\n", memSize);
			DBG("rr: device BAR3 address %x\n",
			    memBaseAddress);
			pci0WriteConfigReg(BAR3, device, memBaseAddress);
			/* BAR4 parameters */
			memBaseAddress = pci0ReadConfigReg(BAR4, device);
			pci0ArrayPointer->bar4Type = memBaseAddress & 1;
			pci0ArrayPointer->bar4Base =
			    memBaseAddress & 0xfffff000;
			pci0WriteConfigReg(BAR4, device, 0xffffffff);
			memSize = pci0ReadConfigReg(BAR4, device);
			if (memSize == 0) {	/* case of an empty BAR */
				pci0ArrayPointer->bar4Size = 0;
			} else {
				if (pci0ArrayPointer->bar4Type == 0)	/* memory space */
					memSize =
					    ~(memSize & 0xfffffff0) + 1;
				else	/* IO space */
					memSize =
					    ~(memSize & 0xfffffffc) + 1;
				pci0ArrayPointer->bar4Size = memSize;
			}
			DBG("rr: device BAR4 size %x\n", memSize);
			DBG("rr: device BAR4 address %x\n",
			    memBaseAddress);
			pci0WriteConfigReg(BAR4, device, memBaseAddress);
			/* BAR5 parameters */
			memBaseAddress = pci0ReadConfigReg(BAR5, device);
			pci0ArrayPointer->bar5Type = memBaseAddress & 1;
			pci0ArrayPointer->bar5Base =
			    memBaseAddress & 0xfffff000;
			pci0WriteConfigReg(BAR5, device, 0xffffffff);
			memSize = pci0ReadConfigReg(BAR5, device);
			if (memSize == 0) {	/* case of an empty BAR */
				pci0ArrayPointer->bar5Size = 0;
			} else {
				if (pci0ArrayPointer->bar5Type == 1)	/* memory space */
					memSize =
					    ~(memSize & 0xfffffff0) + 1;
				else	/* IO space */
					memSize =
					    ~(memSize & 0xfffffffc) + 1;
				pci0ArrayPointer->bar5Size = memSize;
			}
			DBG("rr: device BAR5 size %x\n", memSize);
			DBG("rr: device BAR5 address %x\n",
			    memBaseAddress);
			pci0WriteConfigReg(BAR5, device, memBaseAddress);
			/* End of BARs Detection. */

			classCode = ((classCode & 0xff000000) >> 24);
			switch (classCode) {
			case 0x0:
				strcpy(pci0ArrayPointer->type,
				       "Old generation device");
				break;
			case 0x1:
				strcpy(pci0ArrayPointer->type,
				       "Mass storage controller");
				break;
			case 0x2:
				strcpy(pci0ArrayPointer->type,
				       "Network controller");
				break;
			case 0x3:
				strcpy(pci0ArrayPointer->type,
				       "Display controller");
				break;
			case 0x4:
				strcpy(pci0ArrayPointer->type,
				       "Multimedia device");
				break;
			case 0x5:
				strcpy(pci0ArrayPointer->type,
				       "Memory controller");
				break;
			case 0x6:
				strcpy(pci0ArrayPointer->type,
				       "Bridge Device");
				break;
			case 0x7:
				strcpy(pci0ArrayPointer->type,
				       "Simple Communication controllers");
				break;
			case 0x8:
				strcpy(pci0ArrayPointer->type,
				       "Base system peripherals");
				break;
			case 0x9:
				strcpy(pci0ArrayPointer->type,
				       "Input Devices");
				break;
			case 0xa:
				strcpy(pci0ArrayPointer->type,
				       "Docking stations");
				break;
			case 0xb:
				strcpy(pci0ArrayPointer->type,
				       "Processors");
				break;
			case 0xc:
				strcpy(pci0ArrayPointer->type,
				       "Serial bus controllers");
				break;
			case 0xd:
				strcpy(pci0ArrayPointer->type,
				       "Wireless controllers");
				break;
			case 0xe:
				strcpy(pci0ArrayPointer->type,
				       "Intelligent I/O controllers");
				break;
			case 0xf:
				strcpy(pci0ArrayPointer->type,
				       "Satellite communication controllers");
				break;
			case 0x10:
				strcpy(pci0ArrayPointer->type,
				       "Encryption/Decryption controllers");
				break;
			case 0x11:
				strcpy(pci0ArrayPointer->type,
				       "Data acquisition and signal processing controllers");
				break;
			default:
				break;

			}
			arrayCounter++;	/* point to the next element in the Array. */
			if (arrayCounter == numberOfElment)
				return;	/* When the Array is fully used, return. */
			/* Else, points to next free Element. */
			pci0ArrayPointer = &pci0Detect[arrayCounter];
		}
	}
	pci0ArrayPointer->deviceNum = 0;	/* 0 => End of List */
}


/********************************************************************
* pci1ScanDevices   - This function scan PCI1 bus, if found any device on
*                     this bus it interrogate the Device for the information
*                     it can discover.
*                     The fields with all information are the following:
*    char            type[20];
*    unsigned int    deviceNum;
*    unsigned int    venID;
*    unsigned int    deviceID;
*    unsigned int    bar0Base;
*    unsigned int    bar0Size;
*    unsigned int    bar1Base;
*    unsigned int    bar1Size;
*    unsigned int    bar2Base;
*    unsigned int    bar2Size;
*    unsigned int    bar3Base;
*    unsigned int    bar3Size;
*    unsigned int    bar4Base;
*    unsigned int    bar4Size;
*    unsigned int    bar5Base;
*    unsigned int    bar5Size;
*
* Inputs:   Pointer to an array of STRUCT PCI1_DEVICE.
* Output:   None.
*********************************************************************/

void pci1ScanDevices(PCI_DEVICE * pci1Detect, unsigned int numberOfElment)
{
	PCI_DEVICE *pci1ArrayPointer = pci1Detect;
	unsigned int id;	/* PCI Configuration register 0x0. */
	unsigned int device;	/* device`s Counter. */
	unsigned int classCode;	/* PCI Configuration register 0x8 */
	unsigned int arrayCounter = 0;
	unsigned int memBaseAddress;
	unsigned int memSize;
	unsigned int c98RegValue;

	PCI1_MASTER_ENABLE(SELF);
	/* According to PCI REV 2.1 MAX agents on the bus are -21- */
	for (device = 1; device < 22; device++) {
		id = pci1ReadConfigReg(PCI_0DEVICE_AND_VENDOR_ID, device);
		GT_REG_READ(HIGH_INTERRUPT_CAUSE_REGISTER, &c98RegValue);
		/* Clearing bit 18 of in the High Cause Register 0xc98 */
		GT_REG_WRITE(HIGH_INTERRUPT_CAUSE_REGISTER,
			     c98RegValue & 0xfffbffff);
		if ((id != 0xffffffff) && !(c98RegValue & 0x40000)) {
			classCode =
			    pci1ReadConfigReg
			    (PCI_0CLASS_CODE_AND_REVISION_ID, device);
			pci1ArrayPointer->deviceNum = device;
			pci1ArrayPointer->venID = (id & 0xffff);
			pci1ArrayPointer->deviceID =
			    ((id & 0xffff0000) >> 16);

			/* BAR0 parameters */
			memBaseAddress = pci1ReadConfigReg(BAR0, device);
			pci1ArrayPointer->bar0Type = memBaseAddress & 1;
			pci1ArrayPointer->bar0Base =
			    memBaseAddress & 0xfffff000;
			pci1WriteConfigReg(BAR0, device, 0xffffffff);
			memSize = pci1ReadConfigReg(BAR0, device);
			if (memSize == 0) {	/* case of an empty BAR */
				pci1ArrayPointer->bar0Size = 0;
			} else {
				if (pci1ArrayPointer->bar0Type == 0)	/* memory space */
					memSize =
					    ~(memSize & 0xfffffff0) + 1;
				else	/* IO space */
					memSize =
					    ~(memSize & 0xfffffffc) + 1;
				pci1ArrayPointer->bar0Size = memSize;
			}
			pci1WriteConfigReg(BAR0, device, memBaseAddress);
			/* BAR1 parameters */
			memBaseAddress = pci1ReadConfigReg(BAR1, device);
			pci1ArrayPointer->bar1Type = memBaseAddress & 1;
			pci1ArrayPointer->bar1Base =
			    memBaseAddress & 0xfffff000;
			pci1WriteConfigReg(BAR1, device, 0xffffffff);
			memSize = pci1ReadConfigReg(BAR1, device);
			if (memSize == 0) {	/* case of an empty BAR */
				pci1ArrayPointer->bar1Size = 0;
			} else {
				if (pci1ArrayPointer->bar1Type == 0)	/* memory space */
					memSize =
					    ~(memSize & 0xfffffff0) + 1;
				else	/* IO space */
					memSize =
					    ~(memSize & 0xfffffffc) + 1;
				pci1ArrayPointer->bar1Size = memSize;
			}
			pci1WriteConfigReg(BAR1, device, memBaseAddress);
			/* BAR2 parameters */
			memBaseAddress = pci1ReadConfigReg(BAR2, device);
			pci1ArrayPointer->bar2Type = memBaseAddress & 1;
			pci1ArrayPointer->bar2Base =
			    memBaseAddress & 0xfffff000;
			pci1WriteConfigReg(BAR2, device, 0xffffffff);
			memSize = pci1ReadConfigReg(BAR2, device);
			if (memSize == 0) {	/* case of an empty BAR */
				pci1ArrayPointer->bar2Size = 0;
			} else {
				if (pci1ArrayPointer->bar2Type == 0)	/* memory space */
					memSize =
					    ~(memSize & 0xfffffff0) + 1;
				else	/* IO space */
					memSize =
					    ~(memSize & 0xfffffffc) + 1;
				pci1ArrayPointer->bar2Size = memSize;
			}
			pci1WriteConfigReg(BAR2, device, memBaseAddress);
			/* BAR3 parameters */
			memBaseAddress = pci1ReadConfigReg(BAR3, device);
			pci1ArrayPointer->bar3Type = memBaseAddress & 1;
			pci1ArrayPointer->bar3Base =
			    memBaseAddress & 0xfffff000;
			pci1WriteConfigReg(BAR3, device, 0xffffffff);
			memSize = pci1ReadConfigReg(BAR3, device);
			if (memSize == 0) {	/* case of an empty BAR */
				pci1ArrayPointer->bar3Size = 0;
			} else {
				if (pci1ArrayPointer->bar3Type == 0)	/* memory space */
					memSize =
					    ~(memSize & 0xfffffff0) + 1;
				else	/* IO space */
					memSize =
					    ~(memSize & 0xfffffffc) + 1;
				pci1ArrayPointer->bar3Size = memSize;
			}
			pci1WriteConfigReg(BAR3, device, memBaseAddress);
			/* BAR4 parameters */
			memBaseAddress = pci1ReadConfigReg(BAR4, device);
			pci1ArrayPointer->bar4Type = memBaseAddress & 1;
			pci1ArrayPointer->bar4Base =
			    memBaseAddress & 0xfffff000;
			pci1WriteConfigReg(BAR4, device, 0xffffffff);
			memSize = pci1ReadConfigReg(BAR4, device);
			if (memSize == 0) {	/* case of an empty BAR */
				pci1ArrayPointer->bar4Size = 0;